xref: /plan9-contrib/sys/src/nboot/bitsy/uart.c (revision 529c1f209803c78c4f2cda11b13818a57f01c872)
1 #include	"u.h"
2 #include	"lib.h"
3 #include	"mem.h"
4 #include	"dat.h"
5 #include	"fns.h"
6 #include	"io.h"
7 
8 enum
9 {
10 	/* ctl[0] bits */
11 	Parity=		1<<0,
12 	Even=		1<<1,
13 	Stop2=		1<<2,
14 	Bits8=		1<<3,
15 	SCE=		1<<4,	/* synchronous clock enable */
16 	RCE=		1<<5,	/* rx on falling edge of clock */
17 	TCE=		1<<6,	/* tx on falling edge of clock */
18 
19 	/* ctl[3] bits */
20 	Rena=		1<<0,	/* receiver enable */
21 	Tena=		1<<1,	/* transmitter enable */
22 	Break=		1<<2,	/* force TXD3 low */
23 	Rintena=	1<<3,	/* enable receive interrupt */
24 	Tintena=	1<<4,	/* enable transmitter interrupt */
25 	Loopback=	1<<5,	/* loop back data */
26 
27 	/* data bits */
28 	DEparity=	1<<8,	/* parity error */
29 	DEframe=	1<<9,	/* framing error */
30 	DEoverrun=	1<<10,	/* overrun error */
31 
32 	/* status[0] bits */
33 	Tint=		1<<0,	/* transmit fifo half full interrupt */
34 	Rint0=		1<<1,	/* receiver fifo 1/3-2/3 full */
35 	Rint1=		1<<2,	/* receiver fifo not empty and receiver idle */
36 	Breakstart=	1<<3,
37 	Breakend=	1<<4,
38 	Fifoerror=	1<<5,	/* fifo error */
39 
40 	/* status[1] bits */
41 	Tbusy=		1<<0,	/* transmitting */
42 	Rnotempty=	1<<1,	/* receive fifo not empty */
43 	Tnotfull=	1<<2,	/* transmit fifo not full */
44 	ParityError=	1<<3,
45 	FrameError=	1<<4,
46 	Overrun=	1<<5,
47 };
48 
49 Uartregs *uart3regs = (Uartregs*)UART3REGS;
50 
51 
52 /*
53  *  for iprint, just write it
54  */
55 void
serialputs(char * str,int n)56 serialputs(char *str, int n)
57 {
58 	Uartregs *ur;
59 
60 	ur = uart3regs;
61 	while(n-- > 0){
62 		/* wait for output ready */
63 		while((ur->status[1] & Tnotfull) == 0)
64 			;
65 		ur->data = *str++;
66 	}
67 	while((ur->status[1] & Tbusy))
68 		;
69 }
70