1*529c1f20SDavid du Colombier /* 2*529c1f20SDavid du Colombier * Definitions for IO devices. Used only in C. 3*529c1f20SDavid du Colombier */ 4*529c1f20SDavid du Colombier 5*529c1f20SDavid du Colombier enum 6*529c1f20SDavid du Colombier { 7*529c1f20SDavid du Colombier /* hardware counter frequency */ 8*529c1f20SDavid du Colombier ClockFreq= 3686400, 9*529c1f20SDavid du Colombier }; 10*529c1f20SDavid du Colombier 11*529c1f20SDavid du Colombier /* 12*529c1f20SDavid du Colombier * IRQ's defined by SA1100 13*529c1f20SDavid du Colombier */ 14*529c1f20SDavid du Colombier enum 15*529c1f20SDavid du Colombier { 16*529c1f20SDavid du Colombier IRQgpio0= 0, 17*529c1f20SDavid du Colombier IRQgpio1= 1, 18*529c1f20SDavid du Colombier IRQgpio2= 2, 19*529c1f20SDavid du Colombier IRQgpio3= 3, 20*529c1f20SDavid du Colombier IRQgpio4= 4, 21*529c1f20SDavid du Colombier IRQgpio5= 5, 22*529c1f20SDavid du Colombier IRQgpio6= 6, 23*529c1f20SDavid du Colombier IRQgpio7= 7, 24*529c1f20SDavid du Colombier IRQgpio8= 8, 25*529c1f20SDavid du Colombier IRQgpio9= 9, 26*529c1f20SDavid du Colombier IRQgpio10= 10, 27*529c1f20SDavid du Colombier IRQgpiohi= 11, 28*529c1f20SDavid du Colombier IRQlcd= 12, 29*529c1f20SDavid du Colombier IRQudc= 13, 30*529c1f20SDavid du Colombier IRQuart1b= 15, 31*529c1f20SDavid du Colombier IRQuart2= 16, 32*529c1f20SDavid du Colombier IRQuart3= 17, 33*529c1f20SDavid du Colombier IRQmcp= 18, 34*529c1f20SDavid du Colombier IRQssp= 19, 35*529c1f20SDavid du Colombier IRQdma0= 20, 36*529c1f20SDavid du Colombier IRQdma1= 21, 37*529c1f20SDavid du Colombier IRQdma2= 22, 38*529c1f20SDavid du Colombier IRQdma3= 23, 39*529c1f20SDavid du Colombier IRQdma4= 24, 40*529c1f20SDavid du Colombier IRQdma5= 25, 41*529c1f20SDavid du Colombier IRQtimer0= 26, 42*529c1f20SDavid du Colombier IRQtimer1= 27, 43*529c1f20SDavid du Colombier IRQtimer2= 28, 44*529c1f20SDavid du Colombier IRQtimer3= 29, 45*529c1f20SDavid du Colombier IRQsecond= 30, 46*529c1f20SDavid du Colombier IRQrtc= 31, 47*529c1f20SDavid du Colombier }; 48*529c1f20SDavid du Colombier 49*529c1f20SDavid du Colombier /* 50*529c1f20SDavid du Colombier * GPIO lines (signal names from compaq document). _i indicates input 51*529c1f20SDavid du Colombier * and _o output. 52*529c1f20SDavid du Colombier */ 53*529c1f20SDavid du Colombier enum 54*529c1f20SDavid du Colombier { 55*529c1f20SDavid du Colombier GPIO_PWR_ON_i= 1<<0, /* power button */ 56*529c1f20SDavid du Colombier GPIO_UP_IRQ_i= 1<<1, /* microcontroller interrupts */ 57*529c1f20SDavid du Colombier GPIO_LDD8_o= 1<<2, /* LCD data 8-15 */ 58*529c1f20SDavid du Colombier GPIO_LDD9_o= 1<<3, 59*529c1f20SDavid du Colombier GPIO_LDD10_o= 1<<4, 60*529c1f20SDavid du Colombier GPIO_LDD11_o= 1<<5, 61*529c1f20SDavid du Colombier GPIO_LDD12_o= 1<<6, 62*529c1f20SDavid du Colombier GPIO_LDD13_o= 1<<7, 63*529c1f20SDavid du Colombier GPIO_LDD14_o= 1<<8, 64*529c1f20SDavid du Colombier GPIO_LDD15_o= 1<<9, 65*529c1f20SDavid du Colombier GPIO_CARD_IND1_i= 1<<10, /* card inserted in PCMCIA socket 1 */ 66*529c1f20SDavid du Colombier GPIO_CARD_IRQ1_i= 1<<11, /* PCMCIA socket 1 interrupt */ 67*529c1f20SDavid du Colombier GPIO_CLK_SET0_o= 1<<12, /* clock selects for audio codec */ 68*529c1f20SDavid du Colombier GPIO_CLK_SET1_o= 1<<13, 69*529c1f20SDavid du Colombier GPIO_L3_SDA_io= 1<<14, /* UDA1341 interface */ 70*529c1f20SDavid du Colombier GPIO_L3_MODE_o= 1<<15, 71*529c1f20SDavid du Colombier GPIO_L3_SCLK_o= 1<<16, 72*529c1f20SDavid du Colombier GPIO_CARD_IND0_i= 1<<17, /* card inserted in PCMCIA socket 0 */ 73*529c1f20SDavid du Colombier GPIO_KEY_ACT_i= 1<<18, /* hot key from cradle */ 74*529c1f20SDavid du Colombier GPIO_SYS_CLK_i= 1<<19, /* clock from codec */ 75*529c1f20SDavid du Colombier GPIO_BAT_FAULT_i= 1<<20, /* battery fault */ 76*529c1f20SDavid du Colombier GPIO_CARD_IRQ0_i= 1<<21, /* PCMCIA socket 0 interrupt */ 77*529c1f20SDavid du Colombier GPIO_LOCK_i= 1<<22, /* expansion pack lock/unlock */ 78*529c1f20SDavid du Colombier GPIO_COM_DCD_i= 1<<23, /* DCD from UART3 */ 79*529c1f20SDavid du Colombier GPIO_OPT_IRQ_i= 1<<24, /* expansion pack IRQ */ 80*529c1f20SDavid du Colombier GPIO_COM_CTS_i= 1<<25, /* CTS from UART3 */ 81*529c1f20SDavid du Colombier GPIO_COM_RTS_o= 1<<26, /* RTS to UART3 */ 82*529c1f20SDavid du Colombier GPIO_OPT_IND_i= 1<<27, /* expansion pack inserted */ 83*529c1f20SDavid du Colombier 84*529c1f20SDavid du Colombier /* Peripheral Unit GPIO pin assignments: alternate functions */ 85*529c1f20SDavid du Colombier GPIO_SSP_TXD_o= 1<<10, /* SSP Transmit Data */ 86*529c1f20SDavid du Colombier GPIO_SSP_RXD_i= 1<<11, /* SSP Receive Data */ 87*529c1f20SDavid du Colombier GPIO_SSP_SCLK_o= 1<<12, /* SSP Sample CLocK */ 88*529c1f20SDavid du Colombier GPIO_SSP_SFRM_o= 1<<13, /* SSP Sample FRaMe */ 89*529c1f20SDavid du Colombier /* ser. port 1: */ 90*529c1f20SDavid du Colombier GPIO_UART_TXD_o= 1<<14, /* UART Transmit Data */ 91*529c1f20SDavid du Colombier GPIO_UART_RXD_i= 1<<15, /* UART Receive Data */ 92*529c1f20SDavid du Colombier GPIO_SDLC_SCLK_io= 1<<16, /* SDLC Sample CLocK (I/O) */ 93*529c1f20SDavid du Colombier GPIO_SDLC_AAF_o= 1<<17, /* SDLC Abort After Frame */ 94*529c1f20SDavid du Colombier GPIO_UART_SCLK1_i= 1<<18, /* UART Sample CLocK 1 */ 95*529c1f20SDavid du Colombier /* ser. port 4: */ 96*529c1f20SDavid du Colombier GPIO_SSP_CLK_i= 1<<19, /* SSP external CLocK */ 97*529c1f20SDavid du Colombier /* ser. port 3: */ 98*529c1f20SDavid du Colombier GPIO_UART_SCLK3_i= 1<<20, /* UART Sample CLocK 3 */ 99*529c1f20SDavid du Colombier /* ser. port 4: */ 100*529c1f20SDavid du Colombier GPIO_MCP_CLK_i= 1<<21, /* MCP CLocK */ 101*529c1f20SDavid du Colombier /* test controller: */ 102*529c1f20SDavid du Colombier GPIO_TIC_ACK_o= 1<<21, /* TIC ACKnowledge */ 103*529c1f20SDavid du Colombier GPIO_MBGNT_o= 1<<21, /* Memory Bus GraNT */ 104*529c1f20SDavid du Colombier GPIO_TREQA_i= 1<<22, /* TIC REQuest A */ 105*529c1f20SDavid du Colombier GPIO_MBREQ_i= 1<<22, /* Memory Bus REQuest */ 106*529c1f20SDavid du Colombier GPIO_TREQB_i= 1<<23, /* TIC REQuest B */ 107*529c1f20SDavid du Colombier GPIO_1Hz_o= 1<<25, /* 1 Hz clock */ 108*529c1f20SDavid du Colombier GPIO_RCLK_o= 1<<26, /* internal (R) CLocK (O, fcpu/2) */ 109*529c1f20SDavid du Colombier GPIO_32_768kHz_o= 1<<27, /* 32.768 kHz clock (O, RTC) */ 110*529c1f20SDavid du Colombier }; 111*529c1f20SDavid du Colombier 112*529c1f20SDavid du Colombier /* 113*529c1f20SDavid du Colombier * types of interrupts 114*529c1f20SDavid du Colombier */ 115*529c1f20SDavid du Colombier enum 116*529c1f20SDavid du Colombier { 117*529c1f20SDavid du Colombier GPIOrising, 118*529c1f20SDavid du Colombier GPIOfalling, 119*529c1f20SDavid du Colombier GPIOboth, 120*529c1f20SDavid du Colombier IRQ, 121*529c1f20SDavid du Colombier }; 122*529c1f20SDavid du Colombier 123*529c1f20SDavid du Colombier /* hardware registers */ 124*529c1f20SDavid du Colombier typedef struct Uartregs Uartregs; 125*529c1f20SDavid du Colombier struct Uartregs 126*529c1f20SDavid du Colombier { 127*529c1f20SDavid du Colombier ulong ctl[4]; 128*529c1f20SDavid du Colombier ulong dummya; 129*529c1f20SDavid du Colombier ulong data; 130*529c1f20SDavid du Colombier ulong dummyb; 131*529c1f20SDavid du Colombier ulong status[2]; 132*529c1f20SDavid du Colombier }; 133*529c1f20SDavid du Colombier Uartregs *uart3regs; 134*529c1f20SDavid du Colombier 135*529c1f20SDavid du Colombier /* general purpose I/O lines control registers */ 136*529c1f20SDavid du Colombier typedef struct GPIOregs GPIOregs; 137*529c1f20SDavid du Colombier struct GPIOregs 138*529c1f20SDavid du Colombier { 139*529c1f20SDavid du Colombier ulong level; /* 1 == high */ 140*529c1f20SDavid du Colombier ulong direction; /* 1 == output */ 141*529c1f20SDavid du Colombier ulong set; /* a 1 sets the bit, 0 leaves it alone */ 142*529c1f20SDavid du Colombier ulong clear; /* a 1 clears the bit, 0 leaves it alone */ 143*529c1f20SDavid du Colombier ulong rising; /* rising edge detect enable */ 144*529c1f20SDavid du Colombier ulong falling; /* falling edge detect enable */ 145*529c1f20SDavid du Colombier ulong edgestatus; /* writing a 1 bit clears */ 146*529c1f20SDavid du Colombier ulong altfunc; /* turn on alternate function for any set bits */ 147*529c1f20SDavid du Colombier }; 148*529c1f20SDavid du Colombier 149*529c1f20SDavid du Colombier extern GPIOregs *gpioregs; 150*529c1f20SDavid du Colombier 151*529c1f20SDavid du Colombier /* extra general purpose I/O bits, output only */ 152*529c1f20SDavid du Colombier enum 153*529c1f20SDavid du Colombier { 154*529c1f20SDavid du Colombier EGPIO_prog_flash= 1<<0, 155*529c1f20SDavid du Colombier EGPIO_pcmcia_reset= 1<<1, 156*529c1f20SDavid du Colombier EGPIO_exppack_reset= 1<<2, 157*529c1f20SDavid du Colombier EGPIO_codec_reset= 1<<3, 158*529c1f20SDavid du Colombier EGPIO_exp_nvram_power= 1<<4, 159*529c1f20SDavid du Colombier EGPIO_exp_full_power= 1<<5, 160*529c1f20SDavid du Colombier EGPIO_lcd_3v= 1<<6, 161*529c1f20SDavid du Colombier EGPIO_rs232_power= 1<<7, 162*529c1f20SDavid du Colombier EGPIO_lcd_ic_power= 1<<8, 163*529c1f20SDavid du Colombier EGPIO_ir_power= 1<<9, 164*529c1f20SDavid du Colombier EGPIO_audio_power= 1<<10, 165*529c1f20SDavid du Colombier EGPIO_audio_ic_power= 1<<11, 166*529c1f20SDavid du Colombier EGPIO_audio_mute= 1<<12, 167*529c1f20SDavid du Colombier EGPIO_fir= 1<<13, /* not set is sir */ 168*529c1f20SDavid du Colombier EGPIO_lcd_5v= 1<<14, 169*529c1f20SDavid du Colombier EGPIO_lcd_9v= 1<<15, 170*529c1f20SDavid du Colombier }; 171*529c1f20SDavid du Colombier extern ulong *egpioreg; 172*529c1f20SDavid du Colombier 173*529c1f20SDavid du Colombier /* Peripheral pin controller registers */ 174*529c1f20SDavid du Colombier typedef struct PPCregs PPCregs; 175*529c1f20SDavid du Colombier struct PPCregs { 176*529c1f20SDavid du Colombier ulong direction; 177*529c1f20SDavid du Colombier ulong state; 178*529c1f20SDavid du Colombier ulong assignment; 179*529c1f20SDavid du Colombier ulong sleepdir; 180*529c1f20SDavid du Colombier ulong flags; 181*529c1f20SDavid du Colombier }; 182*529c1f20SDavid du Colombier extern PPCregs *ppcregs; 183*529c1f20SDavid du Colombier 184*529c1f20SDavid du Colombier /* Synchronous Serial Port controller registers */ 185*529c1f20SDavid du Colombier typedef struct SSPregs SSPregs; 186*529c1f20SDavid du Colombier struct SSPregs { 187*529c1f20SDavid du Colombier ulong control0; 188*529c1f20SDavid du Colombier ulong control1; 189*529c1f20SDavid du Colombier ulong dummy0; 190*529c1f20SDavid du Colombier ulong data; 191*529c1f20SDavid du Colombier ulong dummy1; 192*529c1f20SDavid du Colombier ulong status; 193*529c1f20SDavid du Colombier }; 194*529c1f20SDavid du Colombier extern SSPregs *sspregs; 195*529c1f20SDavid du Colombier 196*529c1f20SDavid du Colombier /* Multimedia Communications Port controller registers */ 197*529c1f20SDavid du Colombier typedef struct MCPregs MCPregs; 198*529c1f20SDavid du Colombier struct MCPregs { 199*529c1f20SDavid du Colombier ulong control0; 200*529c1f20SDavid du Colombier ulong reserved0; 201*529c1f20SDavid du Colombier ulong data0; 202*529c1f20SDavid du Colombier ulong data1; 203*529c1f20SDavid du Colombier ulong data2; 204*529c1f20SDavid du Colombier ulong reserved1; 205*529c1f20SDavid du Colombier ulong status; 206*529c1f20SDavid du Colombier ulong reserved[11]; 207*529c1f20SDavid du Colombier ulong control1; 208*529c1f20SDavid du Colombier }; 209*529c1f20SDavid du Colombier extern MCPregs *mcpregs; 210*529c1f20SDavid du Colombier 211*529c1f20SDavid du Colombier /* 212*529c1f20SDavid du Colombier * memory configuration 213*529c1f20SDavid du Colombier */ 214*529c1f20SDavid du Colombier enum 215*529c1f20SDavid du Colombier { 216*529c1f20SDavid du Colombier /* bit shifts for pcmcia access time counters */ 217*529c1f20SDavid du Colombier MECR_io0= 0, 218*529c1f20SDavid du Colombier MECR_attr0= 5, 219*529c1f20SDavid du Colombier MECR_mem0= 10, 220*529c1f20SDavid du Colombier MECR_fast0= 11, 221*529c1f20SDavid du Colombier MECR_io1= MECR_io0+16, 222*529c1f20SDavid du Colombier MECR_attr1= MECR_attr0+16, 223*529c1f20SDavid du Colombier MECR_mem1= MECR_mem0+16, 224*529c1f20SDavid du Colombier MECR_fast1= MECR_fast0+16, 225*529c1f20SDavid du Colombier }; 226*529c1f20SDavid du Colombier 227*529c1f20SDavid du Colombier typedef struct MemConfRegs MemConfRegs; 228*529c1f20SDavid du Colombier struct MemConfRegs 229*529c1f20SDavid du Colombier { 230*529c1f20SDavid du Colombier ulong mdcnfg; /* dram */ 231*529c1f20SDavid du Colombier ulong mdcas00; /* dram banks 0/1 */ 232*529c1f20SDavid du Colombier ulong mdcas01; 233*529c1f20SDavid du Colombier ulong mdcas02; 234*529c1f20SDavid du Colombier ulong msc0; /* static */ 235*529c1f20SDavid du Colombier ulong msc1; 236*529c1f20SDavid du Colombier ulong mecr; /* pcmcia */ 237*529c1f20SDavid du Colombier ulong mdrefr; /* dram refresh */ 238*529c1f20SDavid du Colombier ulong mdcas20; /* dram banks 2/3 */ 239*529c1f20SDavid du Colombier ulong mdcas21; 240*529c1f20SDavid du Colombier ulong mdcas22; 241*529c1f20SDavid du Colombier ulong msc2; /* static */ 242*529c1f20SDavid du Colombier ulong smcnfg; /* SMROM config */ 243*529c1f20SDavid du Colombier }; 244*529c1f20SDavid du Colombier extern MemConfRegs *memconfregs; 245*529c1f20SDavid du Colombier 246*529c1f20SDavid du Colombier /* 247*529c1f20SDavid du Colombier * power management 248*529c1f20SDavid du Colombier */ 249*529c1f20SDavid du Colombier typedef struct PowerRegs PowerRegs; 250*529c1f20SDavid du Colombier struct PowerRegs 251*529c1f20SDavid du Colombier { 252*529c1f20SDavid du Colombier ulong pmcr; /* Power manager control register */ 253*529c1f20SDavid du Colombier ulong pssr; /* Power manager sleep status register */ 254*529c1f20SDavid du Colombier ulong pspr; /* Power manager scratch pad register */ 255*529c1f20SDavid du Colombier ulong pwer; /* Power manager wakeup enable register */ 256*529c1f20SDavid du Colombier ulong pcfr; /* Power manager general configuration register */ 257*529c1f20SDavid du Colombier ulong ppcr; /* Power manager PPL configuration register */ 258*529c1f20SDavid du Colombier ulong pgsr; /* Power manager GPIO sleep state register */ 259*529c1f20SDavid du Colombier ulong posr; /* Power manager oscillator status register */ 260*529c1f20SDavid du Colombier }; 261*529c1f20SDavid du Colombier extern PowerRegs *powerregs; 262