1 /* 2 * Definitions for IO devices. Used only in C. 3 */ 4 5 enum 6 { 7 /* hardware counter frequency */ 8 ClockFreq= 3686400, 9 }; 10 11 /* 12 * IRQ's defined by SA1100 13 */ 14 enum 15 { 16 IRQgpio0= 0, 17 IRQgpio1= 1, 18 IRQgpio2= 2, 19 IRQgpio3= 3, 20 IRQgpio4= 4, 21 IRQgpio5= 5, 22 IRQgpio6= 6, 23 IRQgpio7= 7, 24 IRQgpio8= 8, 25 IRQgpio9= 9, 26 IRQgpio10= 10, 27 IRQgpiohi= 11, 28 IRQlcd= 12, 29 IRQudc= 13, 30 IRQuart1b= 15, 31 IRQuart2= 16, 32 IRQuart3= 17, 33 IRQmcp= 18, 34 IRQssp= 19, 35 IRQdma0= 20, 36 IRQdma1= 21, 37 IRQdma2= 22, 38 IRQdma3= 23, 39 IRQdma4= 24, 40 IRQdma5= 25, 41 IRQtimer0= 26, 42 IRQtimer1= 27, 43 IRQtimer2= 28, 44 IRQtimer3= 29, 45 IRQsecond= 30, 46 IRQrtc= 31, 47 }; 48 49 /* 50 * GPIO lines (signal names from compaq document). _i indicates input 51 * and _o output. 52 */ 53 enum 54 { 55 GPIO_PWR_ON_i= 1<<0, /* power button */ 56 GPIO_UP_IRQ_i= 1<<1, /* microcontroller interrupts */ 57 GPIO_LDD8_o= 1<<2, /* LCD data 8-15 */ 58 GPIO_LDD9_o= 1<<3, 59 GPIO_LDD10_o= 1<<4, 60 GPIO_LDD11_o= 1<<5, 61 GPIO_LDD12_o= 1<<6, 62 GPIO_LDD13_o= 1<<7, 63 GPIO_LDD14_o= 1<<8, 64 GPIO_LDD15_o= 1<<9, 65 GPIO_CARD_IND1_i= 1<<10, /* card inserted in PCMCIA socket 1 */ 66 GPIO_CARD_IRQ1_i= 1<<11, /* PCMCIA socket 1 interrupt */ 67 GPIO_CLK_SET0_o= 1<<12, /* clock selects for audio codec */ 68 GPIO_CLK_SET1_o= 1<<13, 69 GPIO_L3_SDA_io= 1<<14, /* UDA1341 interface */ 70 GPIO_L3_MODE_o= 1<<15, 71 GPIO_L3_SCLK_o= 1<<16, 72 GPIO_CARD_IND0_i= 1<<17, /* card inserted in PCMCIA socket 0 */ 73 GPIO_KEY_ACT_i= 1<<18, /* hot key from cradle */ 74 GPIO_SYS_CLK_i= 1<<19, /* clock from codec */ 75 GPIO_BAT_FAULT_i= 1<<20, /* battery fault */ 76 GPIO_CARD_IRQ0_i= 1<<21, /* PCMCIA socket 0 interrupt */ 77 GPIO_LOCK_i= 1<<22, /* expansion pack lock/unlock */ 78 GPIO_COM_DCD_i= 1<<23, /* DCD from UART3 */ 79 GPIO_OPT_IRQ_i= 1<<24, /* expansion pack IRQ */ 80 GPIO_COM_CTS_i= 1<<25, /* CTS from UART3 */ 81 GPIO_COM_RTS_o= 1<<26, /* RTS to UART3 */ 82 GPIO_OPT_IND_i= 1<<27, /* expansion pack inserted */ 83 84 /* Peripheral Unit GPIO pin assignments: alternate functions */ 85 GPIO_SSP_TXD_o= 1<<10, /* SSP Transmit Data */ 86 GPIO_SSP_RXD_i= 1<<11, /* SSP Receive Data */ 87 GPIO_SSP_SCLK_o= 1<<12, /* SSP Sample CLocK */ 88 GPIO_SSP_SFRM_o= 1<<13, /* SSP Sample FRaMe */ 89 /* ser. port 1: */ 90 GPIO_UART_TXD_o= 1<<14, /* UART Transmit Data */ 91 GPIO_UART_RXD_i= 1<<15, /* UART Receive Data */ 92 GPIO_SDLC_SCLK_io= 1<<16, /* SDLC Sample CLocK (I/O) */ 93 GPIO_SDLC_AAF_o= 1<<17, /* SDLC Abort After Frame */ 94 GPIO_UART_SCLK1_i= 1<<18, /* UART Sample CLocK 1 */ 95 /* ser. port 4: */ 96 GPIO_SSP_CLK_i= 1<<19, /* SSP external CLocK */ 97 /* ser. port 3: */ 98 GPIO_UART_SCLK3_i= 1<<20, /* UART Sample CLocK 3 */ 99 /* ser. port 4: */ 100 GPIO_MCP_CLK_i= 1<<21, /* MCP CLocK */ 101 /* test controller: */ 102 GPIO_TIC_ACK_o= 1<<21, /* TIC ACKnowledge */ 103 GPIO_MBGNT_o= 1<<21, /* Memory Bus GraNT */ 104 GPIO_TREQA_i= 1<<22, /* TIC REQuest A */ 105 GPIO_MBREQ_i= 1<<22, /* Memory Bus REQuest */ 106 GPIO_TREQB_i= 1<<23, /* TIC REQuest B */ 107 GPIO_1Hz_o= 1<<25, /* 1 Hz clock */ 108 GPIO_RCLK_o= 1<<26, /* internal (R) CLocK (O, fcpu/2) */ 109 GPIO_32_768kHz_o= 1<<27, /* 32.768 kHz clock (O, RTC) */ 110 }; 111 112 /* 113 * types of interrupts 114 */ 115 enum 116 { 117 GPIOrising, 118 GPIOfalling, 119 GPIOboth, 120 IRQ, 121 }; 122 123 /* hardware registers */ 124 typedef struct Uartregs Uartregs; 125 struct Uartregs 126 { 127 ulong ctl[4]; 128 ulong dummya; 129 ulong data; 130 ulong dummyb; 131 ulong status[2]; 132 }; 133 Uartregs *uart3regs; 134 135 /* general purpose I/O lines control registers */ 136 typedef struct GPIOregs GPIOregs; 137 struct GPIOregs 138 { 139 ulong level; /* 1 == high */ 140 ulong direction; /* 1 == output */ 141 ulong set; /* a 1 sets the bit, 0 leaves it alone */ 142 ulong clear; /* a 1 clears the bit, 0 leaves it alone */ 143 ulong rising; /* rising edge detect enable */ 144 ulong falling; /* falling edge detect enable */ 145 ulong edgestatus; /* writing a 1 bit clears */ 146 ulong altfunc; /* turn on alternate function for any set bits */ 147 }; 148 149 extern GPIOregs *gpioregs; 150 151 /* extra general purpose I/O bits, output only */ 152 enum 153 { 154 EGPIO_prog_flash= 1<<0, 155 EGPIO_pcmcia_reset= 1<<1, 156 EGPIO_exppack_reset= 1<<2, 157 EGPIO_codec_reset= 1<<3, 158 EGPIO_exp_nvram_power= 1<<4, 159 EGPIO_exp_full_power= 1<<5, 160 EGPIO_lcd_3v= 1<<6, 161 EGPIO_rs232_power= 1<<7, 162 EGPIO_lcd_ic_power= 1<<8, 163 EGPIO_ir_power= 1<<9, 164 EGPIO_audio_power= 1<<10, 165 EGPIO_audio_ic_power= 1<<11, 166 EGPIO_audio_mute= 1<<12, 167 EGPIO_fir= 1<<13, /* not set is sir */ 168 EGPIO_lcd_5v= 1<<14, 169 EGPIO_lcd_9v= 1<<15, 170 }; 171 extern ulong *egpioreg; 172 173 /* Peripheral pin controller registers */ 174 typedef struct PPCregs PPCregs; 175 struct PPCregs { 176 ulong direction; 177 ulong state; 178 ulong assignment; 179 ulong sleepdir; 180 ulong flags; 181 }; 182 extern PPCregs *ppcregs; 183 184 /* Synchronous Serial Port controller registers */ 185 typedef struct SSPregs SSPregs; 186 struct SSPregs { 187 ulong control0; 188 ulong control1; 189 ulong dummy0; 190 ulong data; 191 ulong dummy1; 192 ulong status; 193 }; 194 extern SSPregs *sspregs; 195 196 /* Multimedia Communications Port controller registers */ 197 typedef struct MCPregs MCPregs; 198 struct MCPregs { 199 ulong control0; 200 ulong reserved0; 201 ulong data0; 202 ulong data1; 203 ulong data2; 204 ulong reserved1; 205 ulong status; 206 ulong reserved[11]; 207 ulong control1; 208 }; 209 extern MCPregs *mcpregs; 210 211 /* 212 * memory configuration 213 */ 214 enum 215 { 216 /* bit shifts for pcmcia access time counters */ 217 MECR_io0= 0, 218 MECR_attr0= 5, 219 MECR_mem0= 10, 220 MECR_fast0= 11, 221 MECR_io1= MECR_io0+16, 222 MECR_attr1= MECR_attr0+16, 223 MECR_mem1= MECR_mem0+16, 224 MECR_fast1= MECR_fast0+16, 225 }; 226 227 typedef struct MemConfRegs MemConfRegs; 228 struct MemConfRegs 229 { 230 ulong mdcnfg; /* dram */ 231 ulong mdcas00; /* dram banks 0/1 */ 232 ulong mdcas01; 233 ulong mdcas02; 234 ulong msc0; /* static */ 235 ulong msc1; 236 ulong mecr; /* pcmcia */ 237 ulong mdrefr; /* dram refresh */ 238 ulong mdcas20; /* dram banks 2/3 */ 239 ulong mdcas21; 240 ulong mdcas22; 241 ulong msc2; /* static */ 242 ulong smcnfg; /* SMROM config */ 243 }; 244 extern MemConfRegs *memconfregs; 245 246 /* 247 * power management 248 */ 249 typedef struct PowerRegs PowerRegs; 250 struct PowerRegs 251 { 252 ulong pmcr; /* Power manager control register */ 253 ulong pssr; /* Power manager sleep status register */ 254 ulong pspr; /* Power manager scratch pad register */ 255 ulong pwer; /* Power manager wakeup enable register */ 256 ulong pcfr; /* Power manager general configuration register */ 257 ulong ppcr; /* Power manager PPL configuration register */ 258 ulong pgsr; /* Power manager GPIO sleep state register */ 259 ulong posr; /* Power manager oscillator status register */ 260 }; 261 extern PowerRegs *powerregs; 262