1 /* 2 * RISC-V RV64 definition 3 */ 4 #include <u.h> 5 #include <libc.h> 6 #include <bio.h> 7 #include "/riscv64/include/ureg.h" 8 #include <mach.h> 9 10 #define REGOFF(x) (u64int)(&((struct Ureg *) 0)->x) 11 #define REGSIZE sizeof(struct Ureg) 12 13 #define RCURMODE REGOFF(curmode) 14 #define FP_REG(x) (RCURMODE+8+8*(x)) 15 #define FPREGSIZE (8*33) 16 17 Reglist riscv64reglist[] = { 18 {"STATUS", REGOFF(status), RINT|RRDONLY, 'Y'}, 19 {"CAUSE", REGOFF(cause), RINT|RRDONLY, 'Y'}, 20 {"IE", REGOFF(ie), RINT|RRDONLY, 'Y'}, 21 {"TVAL", REGOFF(tval), RINT|RRDONLY, 'Y'}, 22 {"CURMODE", REGOFF(curmode), RINT|RRDONLY, 'Y'}, 23 {"PC", REGOFF(pc), RINT, 'Y'}, 24 {"SP", REGOFF(r2), RINT, 'Y'}, 25 {"R31", REGOFF(r31), RINT, 'Y'}, 26 {"R30", REGOFF(r30), RINT, 'Y'}, 27 {"R28", REGOFF(r28), RINT, 'Y'}, 28 {"R27", REGOFF(r27), RINT, 'Y'}, 29 {"R26", REGOFF(r26), RINT, 'Y'}, 30 {"R25", REGOFF(r25), RINT, 'Y'}, 31 {"R24", REGOFF(r24), RINT, 'Y'}, 32 {"R23", REGOFF(r23), RINT, 'Y'}, 33 {"R22", REGOFF(r22), RINT, 'Y'}, 34 {"R21", REGOFF(r21), RINT, 'Y'}, 35 {"R20", REGOFF(r20), RINT, 'Y'}, 36 {"R19", REGOFF(r19), RINT, 'Y'}, 37 {"R18", REGOFF(r18), RINT, 'Y'}, 38 {"R17", REGOFF(r17), RINT, 'Y'}, 39 {"R16", REGOFF(r16), RINT, 'Y'}, 40 {"R15", REGOFF(r15), RINT, 'Y'}, 41 {"R14", REGOFF(r14), RINT, 'Y'}, 42 {"R13", REGOFF(r13), RINT, 'Y'}, 43 {"R12", REGOFF(r12), RINT, 'Y'}, 44 {"R11", REGOFF(r11), RINT, 'Y'}, 45 {"R10", REGOFF(r10), RINT, 'Y'}, 46 {"R9", REGOFF(r9), RINT, 'Y'}, 47 {"R8", REGOFF(r8), RINT, 'Y'}, 48 {"R7", REGOFF(r7), RINT, 'Y'}, 49 {"R6", REGOFF(r6), RINT, 'Y'}, 50 {"R5", REGOFF(r5), RINT, 'Y'}, 51 {"R4", REGOFF(r4), RINT, 'Y'}, 52 {"R3", REGOFF(r3), RINT, 'Y'}, 53 {"R2", REGOFF(r2), RINT, 'Y'}, 54 {"R1", REGOFF(r1), RINT, 'Y'}, 55 {"F0", FP_REG(0), RFLT, 'F'}, 56 {"F1", FP_REG(1), RFLT, 'F'}, 57 {"F2", FP_REG(2), RFLT, 'F'}, 58 {"F3", FP_REG(3), RFLT, 'F'}, 59 {"F4", FP_REG(4), RFLT, 'F'}, 60 {"F5", FP_REG(5), RFLT, 'F'}, 61 {"F6", FP_REG(6), RFLT, 'F'}, 62 {"F7", FP_REG(7), RFLT, 'F'}, 63 {"F8", FP_REG(8), RFLT, 'F'}, 64 {"F9", FP_REG(9), RFLT, 'F'}, 65 {"F10", FP_REG(10), RFLT, 'F'}, 66 {"F11", FP_REG(11), RFLT, 'F'}, 67 {"F12", FP_REG(12), RFLT, 'F'}, 68 {"F13", FP_REG(13), RFLT, 'F'}, 69 {"F14", FP_REG(14), RFLT, 'F'}, 70 {"F15", FP_REG(15), RFLT, 'F'}, 71 {"F16", FP_REG(16), RFLT, 'F'}, 72 {"F17", FP_REG(17), RFLT, 'F'}, 73 {"F18", FP_REG(18), RFLT, 'F'}, 74 {"F19", FP_REG(19), RFLT, 'F'}, 75 {"F20", FP_REG(20), RFLT, 'F'}, 76 {"F21", FP_REG(21), RFLT, 'F'}, 77 {"F22", FP_REG(22), RFLT, 'F'}, 78 {"F23", FP_REG(23), RFLT, 'F'}, 79 {"F24", FP_REG(24), RFLT, 'F'}, 80 {"F25", FP_REG(25), RFLT, 'F'}, 81 {"F26", FP_REG(26), RFLT, 'F'}, 82 {"F27", FP_REG(27), RFLT, 'F'}, 83 {"F28", FP_REG(28), RFLT, 'F'}, 84 {"F29", FP_REG(29), RFLT, 'F'}, 85 {"F30", FP_REG(30), RFLT, 'F'}, 86 {"F31", FP_REG(31), RFLT, 'F'}, 87 {"FPCSR", FP_REG(32)+4, RFLT, 'X'}, 88 { 0 } 89 }; 90 91 /* the machine description */ 92 Mach mriscv64 = 93 { 94 "riscv64", 95 MRISCV64, /* machine type */ 96 riscv64reglist, /* register set */ 97 REGSIZE, /* register set size */ 98 FPREGSIZE, /* FP register set size */ 99 "PC", /* name of PC */ 100 "SP", /* name of SP */ 101 "R1", /* name of link register */ 102 "setSB", /* static base register name */ 103 0, /* static base register value */ 104 0x1000, /* page size */ 105 /* these are Sv39 values */ 106 0xffffffc080000000ULL, /* kernel base */ 107 0x8000000000000000ULL, /* kernel text mask for all Sv* */ 108 0x0000003fffffffffULL, /* user stack top */ 109 2, /* quantization of pc */ 110 8, /* szaddr */ 111 8, /* szreg */ 112 4, /* szfloat */ 113 8, /* szdouble */ 114 }; 115