1 #include "l.h" 2 3 Optab optab[] = 4 { 5 { ATEXT, C_LEXT, C_NONE, C_NONE, C_LCON, 0, 0, 0 }, 6 { ATEXT, C_LEXT, C_REG, C_NONE, C_LCON, 0, 0, 0 }, 7 { ATEXT, C_LEXT, C_NONE, C_LCON, C_LCON, 0, 0, 0 }, 8 { ATEXT, C_LEXT, C_REG, C_LCON, C_LCON, 0, 0, 0 }, 9 { ATEXT, C_ADDR, C_NONE, C_NONE, C_LCON, 0, 0, 0 }, 10 { ATEXT, C_ADDR, C_REG, C_NONE, C_LCON, 0, 0, 0 }, 11 { ATEXT, C_ADDR, C_NONE, C_LCON, C_LCON, 0, 0, 0 }, 12 { ATEXT, C_ADDR, C_REG, C_LCON, C_LCON, 0, 0, 0 }, 13 14 /* move register */ 15 { AMOVD, C_REG, C_NONE, C_NONE, C_REG, 1, 4, 0 }, 16 { AMOVB, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0 }, 17 { AMOVBZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0 }, 18 { AMOVW, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0 }, 19 { AMOVWZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0 }, 20 21 { AADD, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0 }, 22 { AADD, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0 }, 23 { AADD, C_ADDCON,C_REG, C_NONE, C_REG, 4, 4, 0 }, 24 { AADD, C_ADDCON,C_NONE, C_NONE, C_REG, 4, 4, 0 }, 25 { AADD, C_UCON, C_REG, C_NONE, C_REG, 20, 4, 0 }, 26 { AADD, C_UCON, C_NONE, C_NONE, C_REG, 20, 4, 0 }, 27 { AADD, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0 }, 28 { AADD, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0 }, 29 30 { AADDC, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0 }, 31 { AADDC, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0 }, 32 { AADDC, C_ADDCON,C_REG, C_NONE, C_REG, 4, 4, 0 }, 33 { AADDC, C_ADDCON,C_NONE, C_NONE, C_REG, 4, 4, 0 }, 34 { AADDC, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0 }, 35 { AADDC, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0 }, 36 37 { AAND, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0 }, /* logical, no literal */ 38 { AAND, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0 }, 39 { AANDCC, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0 }, 40 { AANDCC, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0 }, 41 42 { AANDCC, C_ANDCON,C_NONE, C_NONE, C_REG, 58, 4, 0 }, 43 { AANDCC, C_ANDCON,C_REG, C_NONE, C_REG, 58, 4, 0 }, 44 { AANDCC, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0 }, 45 { AANDCC, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0 }, 46 { AANDCC, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0 }, 47 { AANDCC, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0 }, 48 49 { AMULLW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0 }, 50 { AMULLW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0 }, 51 { AMULLW, C_ADDCON,C_REG, C_NONE, C_REG, 4, 4, 0 }, 52 { AMULLW, C_ADDCON,C_NONE, C_NONE, C_REG, 4, 4, 0 }, 53 { AMULLW, C_ANDCON,C_REG, C_NONE, C_REG, 4, 4, 0 }, 54 { AMULLW, C_ANDCON, C_NONE, C_NONE, C_REG, 4, 4, 0 }, 55 { AMULLW, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 56 { AMULLW, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 57 58 { ASUBC, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0 }, 59 { ASUBC, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0 }, 60 { ASUBC, C_REG, C_NONE, C_ADDCON, C_REG, 27, 4, 0 }, 61 { ASUBC, C_REG, C_NONE, C_LCON, C_REG, 28, 12, 0}, 62 63 { AOR, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0 }, /* logical, literal not cc (or/xor) */ 64 { AOR, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0 }, 65 { AOR, C_ANDCON, C_NONE, C_NONE, C_REG, 58, 4, 0 }, 66 { AOR, C_ANDCON, C_REG, C_NONE, C_REG, 58, 4, 0 }, 67 { AOR, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0 }, 68 { AOR, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0 }, 69 { AOR, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0 }, 70 { AOR, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0 }, 71 72 { ADIVW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0 }, /* op r1[,r2],r3 */ 73 { ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0 }, 74 { ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0 }, /* op r2[,r1],r3 */ 75 { ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0 }, 76 77 { ASLW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0 }, 78 { ASLW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0 }, 79 { ASLD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0 }, 80 { ASLD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0 }, 81 { ASLD, C_SCON, C_REG, C_NONE, C_REG, 25, 4, 0 }, 82 { ASLD, C_SCON, C_NONE, C_NONE, C_REG, 25, 4, 0 }, 83 { ASLW, C_SCON, C_REG, C_NONE, C_REG, 57, 4, 0 }, 84 { ASLW, C_SCON, C_NONE, C_NONE, C_REG, 57, 4, 0 }, 85 86 { ASRAW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0 }, 87 { ASRAW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0 }, 88 { ASRAW, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0 }, 89 { ASRAW, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0 }, 90 { ASRAD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0 }, 91 { ASRAD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0 }, 92 { ASRAD, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0 }, 93 { ASRAD, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0 }, 94 95 { ARLWMI, C_SCON, C_REG, C_LCON, C_REG, 62, 4, 0 }, 96 { ARLWMI, C_REG, C_REG, C_LCON, C_REG, 63, 4, 0 }, 97 { ARLDMI, C_SCON, C_REG, C_LCON, C_REG, 30, 4, 0 }, 98 99 { ARLDC, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0 }, 100 { ARLDCL, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0 }, 101 { ARLDCL, C_REG, C_REG, C_LCON, C_REG, 14, 4, 0 }, 102 { ARLDCL, C_REG, C_NONE, C_LCON, C_REG, 14, 4, 0 }, 103 104 { AFADD, C_FREG, C_NONE, C_NONE, C_FREG, 2, 4, 0 }, 105 { AFADD, C_FREG, C_REG, C_NONE, C_FREG, 2, 4, 0 }, 106 { AFABS, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0 }, 107 { AFABS, C_NONE, C_NONE, C_NONE, C_FREG, 33, 4, 0 }, 108 { AFMOVD, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0 }, 109 110 { AFMADD, C_FREG, C_REG, C_FREG, C_FREG, 34, 4, 0 }, 111 { AFMUL, C_FREG, C_NONE, C_NONE, C_FREG, 32, 4, 0 }, 112 { AFMUL, C_FREG, C_REG, C_NONE, C_FREG, 32, 4, 0 }, 113 114 /* store, short offset */ 115 { AMOVD, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO }, 116 { AMOVW, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO }, 117 { AMOVWZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO }, 118 { AMOVBZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO }, 119 { AMOVBZU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO }, 120 { AMOVB, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO }, 121 { AMOVBU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO }, 122 { AMOVD, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB }, 123 { AMOVW, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB }, 124 { AMOVWZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB }, 125 { AMOVBZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB }, 126 { AMOVB, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB }, 127 { AMOVD, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP }, 128 { AMOVW, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP }, 129 { AMOVWZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP }, 130 { AMOVBZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP }, 131 { AMOVB, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP }, 132 { AMOVD, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO }, 133 { AMOVW, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO }, 134 { AMOVWZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO }, 135 { AMOVBZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO }, 136 { AMOVBZU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO }, 137 { AMOVB, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO }, 138 { AMOVBU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO }, 139 140 /* load, short offset */ 141 { AMOVD, C_ZOREG,C_REG, C_NONE, C_REG, 8, 4, REGZERO }, 142 { AMOVW, C_ZOREG,C_REG, C_NONE, C_REG, 8, 4, REGZERO }, 143 { AMOVWZ, C_ZOREG,C_REG, C_NONE, C_REG, 8, 4, REGZERO }, 144 { AMOVBZ, C_ZOREG,C_REG, C_NONE, C_REG, 8, 4, REGZERO }, 145 { AMOVBZU, C_ZOREG,C_REG, C_NONE, C_REG, 8, 4, REGZERO }, 146 { AMOVB, C_ZOREG,C_REG, C_NONE, C_REG, 9, 8, REGZERO }, 147 { AMOVBU, C_ZOREG,C_REG, C_NONE, C_REG, 9, 8, REGZERO }, 148 { AMOVD, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB }, 149 { AMOVW, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB }, 150 { AMOVWZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB }, 151 { AMOVBZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB }, 152 { AMOVB, C_SEXT, C_NONE, C_NONE, C_REG, 9, 8, REGSB }, 153 { AMOVD, C_SAUTO,C_NONE, C_NONE, C_REG, 8, 4, REGSP }, 154 { AMOVW, C_SAUTO,C_NONE, C_NONE, C_REG, 8, 4, REGSP }, 155 { AMOVWZ, C_SAUTO,C_NONE, C_NONE, C_REG, 8, 4, REGSP }, 156 { AMOVBZ, C_SAUTO,C_NONE, C_NONE, C_REG, 8, 4, REGSP }, 157 { AMOVB, C_SAUTO,C_NONE, C_NONE, C_REG, 9, 8, REGSP }, 158 { AMOVD, C_SOREG,C_NONE, C_NONE, C_REG, 8, 4, REGZERO }, 159 { AMOVW, C_SOREG,C_NONE, C_NONE, C_REG, 8, 4, REGZERO }, 160 { AMOVWZ, C_SOREG,C_NONE, C_NONE, C_REG, 8, 4, REGZERO }, 161 { AMOVBZ, C_SOREG,C_NONE, C_NONE, C_REG, 8, 4, REGZERO }, 162 { AMOVBZU, C_SOREG,C_NONE, C_NONE, C_REG, 8, 4, REGZERO }, 163 { AMOVB, C_SOREG,C_NONE, C_NONE, C_REG, 9, 8, REGZERO }, 164 { AMOVBU, C_SOREG,C_NONE, C_NONE, C_REG, 9, 8, REGZERO }, 165 166 /* store, long offset */ 167 { AMOVD, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB }, 168 { AMOVW, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB }, 169 { AMOVWZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB }, 170 { AMOVBZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB }, 171 { AMOVB, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB }, 172 { AMOVD, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP }, 173 { AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP }, 174 { AMOVWZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP }, 175 { AMOVBZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP }, 176 { AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP }, 177 { AMOVD, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO }, 178 { AMOVWZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO }, 179 { AMOVBZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO }, 180 { AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO }, 181 { AMOVD, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0 }, 182 { AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0 }, 183 { AMOVWZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0 }, 184 { AMOVBZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0 }, 185 { AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0 }, 186 187 /* load, long offset */ 188 { AMOVD, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB }, 189 { AMOVW, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB }, 190 { AMOVWZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB }, 191 { AMOVBZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB }, 192 { AMOVB, C_LEXT, C_NONE, C_NONE, C_REG, 37, 12, REGSB }, 193 { AMOVD, C_LAUTO,C_NONE, C_NONE, C_REG, 36, 8, REGSP }, 194 { AMOVW, C_LAUTO,C_NONE, C_NONE, C_REG, 36, 8, REGSP }, 195 { AMOVWZ, C_LAUTO,C_NONE, C_NONE, C_REG, 36, 8, REGSP }, 196 { AMOVBZ, C_LAUTO,C_NONE, C_NONE, C_REG, 36, 8, REGSP }, 197 { AMOVB, C_LAUTO,C_NONE, C_NONE, C_REG, 37, 12, REGSP }, 198 { AMOVD, C_LOREG,C_NONE, C_NONE, C_REG, 36, 8, REGZERO }, 199 { AMOVW, C_LOREG,C_NONE, C_NONE, C_REG, 36, 8, REGZERO }, 200 { AMOVWZ, C_LOREG,C_NONE, C_NONE, C_REG, 36, 8, REGZERO }, 201 { AMOVBZ, C_LOREG,C_NONE, C_NONE, C_REG, 36, 8, REGZERO }, 202 { AMOVB, C_LOREG,C_NONE, C_NONE, C_REG, 37, 12, REGZERO }, 203 { AMOVD, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0 }, 204 { AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0 }, 205 { AMOVWZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0 }, 206 { AMOVBZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0 }, 207 { AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, 76, 12, 0 }, 208 209 /* load constant */ 210 { AMOVD, C_SECON,C_NONE, C_NONE, C_REG, 3, 4, REGSB }, 211 { AMOVD, C_SACON,C_NONE, C_NONE, C_REG, 3, 4, REGSP }, 212 { AMOVD, C_LECON,C_NONE, C_NONE, C_REG, 26, 8, REGSB }, 213 { AMOVD, C_LACON,C_NONE, C_NONE, C_REG, 26, 8, REGSP }, 214 { AMOVD, C_ADDCON,C_NONE, C_NONE, C_REG, 3, 4, REGZERO }, 215 { AMOVW, C_SECON,C_NONE, C_NONE, C_REG, 3, 4, REGSB }, /* TO DO: check */ 216 { AMOVW, C_SACON,C_NONE, C_NONE, C_REG, 3, 4, REGSP }, 217 { AMOVW, C_LECON,C_NONE, C_NONE, C_REG, 26, 8, REGSB }, 218 { AMOVW, C_LACON,C_NONE, C_NONE, C_REG, 26, 8, REGSP }, 219 { AMOVW, C_ADDCON,C_NONE, C_NONE, C_REG, 3, 4, REGZERO }, 220 { AMOVWZ, C_SECON,C_NONE, C_NONE, C_REG, 3, 4, REGSB }, /* TO DO: check */ 221 { AMOVWZ, C_SACON,C_NONE, C_NONE, C_REG, 3, 4, REGSP }, 222 { AMOVWZ, C_LECON,C_NONE, C_NONE, C_REG, 26, 8, REGSB }, 223 { AMOVWZ, C_LACON,C_NONE, C_NONE, C_REG, 26, 8, REGSP }, 224 { AMOVWZ, C_ADDCON,C_NONE, C_NONE, C_REG, 3, 4, REGZERO }, 225 226 /* load unsigned/long constants (TO DO: check) */ 227 { AMOVD, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO }, 228 { AMOVD, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0 }, 229 { AMOVW, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO }, 230 { AMOVW, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0 }, 231 { AMOVWZ, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO }, 232 { AMOVWZ, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0 }, 233 234 { AMOVHBR, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0 }, 235 { AMOVHBR, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0 }, 236 { AMOVHBR, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0 }, 237 { AMOVHBR, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0 }, 238 239 { ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0 }, 240 241 { ABEQ, C_NONE, C_NONE, C_NONE, C_SBRA, 16, 4, 0 }, 242 { ABEQ, C_CREG, C_NONE, C_NONE, C_SBRA, 16, 4, 0 }, 243 244 { ABR, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0 }, 245 246 { ABC, C_SCON, C_REG, C_NONE, C_SBRA, 16, 4, 0 }, 247 { ABC, C_SCON, C_REG, C_NONE, C_LBRA, 17, 4, 0 }, 248 249 { ABR, C_NONE, C_NONE, C_NONE, C_LR, 18, 4, 0 }, 250 { ABR, C_NONE, C_NONE, C_NONE, C_CTR, 18, 4, 0 }, 251 { ABR, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0 }, 252 253 { ABC, C_NONE, C_REG, C_NONE, C_LR, 18, 4, 0 }, 254 { ABC, C_NONE, C_REG, C_NONE, C_CTR, 18, 4, 0 }, 255 { ABC, C_SCON, C_REG, C_NONE, C_LR, 18, 4, 0 }, 256 { ABC, C_SCON, C_REG, C_NONE, C_CTR, 18, 4, 0 }, 257 { ABC, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0 }, 258 259 { AFMOVD, C_SEXT, C_NONE, C_NONE, C_FREG, 8, 4, REGSB }, 260 { AFMOVD, C_SAUTO,C_NONE, C_NONE, C_FREG, 8, 4, REGSP }, 261 { AFMOVD, C_SOREG,C_NONE, C_NONE, C_FREG, 8, 4, REGZERO }, 262 263 { AFMOVD, C_LEXT, C_NONE, C_NONE, C_FREG, 8, 4, REGSB }, 264 { AFMOVD, C_LAUTO,C_NONE, C_NONE, C_FREG, 8, 4, REGSP }, 265 { AFMOVD, C_LOREG,C_NONE, C_NONE, C_FREG, 8, 4, REGZERO }, 266 { AFMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, 75, 8, 0 }, 267 268 { AFMOVD, C_FREG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB }, 269 { AFMOVD, C_FREG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP }, 270 { AFMOVD, C_FREG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO }, 271 272 { AFMOVD, C_FREG, C_NONE, C_NONE, C_LEXT, 7, 4, REGSB }, 273 { AFMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, 7, 4, REGSP }, 274 { AFMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, 7, 4, REGZERO }, 275 { AFMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, 74, 8, 0 }, 276 277 { ASYNC, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0 }, 278 { AWORD, C_LCON, C_NONE, C_NONE, C_NONE, 40, 4, 0 }, 279 { ADWORD, C_LCON, C_NONE, C_NONE, C_NONE, 31, 8, 0 }, 280 281 { AADDME, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0 }, 282 283 { AEXTSB, C_REG, C_NONE, C_NONE, C_REG, 48, 4, 0 }, 284 { AEXTSB, C_NONE, C_NONE, C_NONE, C_REG, 48, 4, 0 }, 285 286 { ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0 }, 287 { ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 4, 0 }, 288 289 { AREM, C_REG, C_NONE, C_NONE, C_REG, 50, 12, 0 }, 290 { AREM, C_REG, C_REG, C_NONE, C_REG, 50, 12, 0 }, 291 { AREMD, C_REG, C_NONE, C_NONE, C_REG, 51, 12, 0 }, 292 { AREMD, C_REG, C_REG, C_NONE, C_REG, 51, 12, 0 }, 293 294 { AMTFSB0, C_SCON, C_NONE, C_NONE, C_NONE, 52, 4, 0 }, 295 { AMOVFL, C_FPSCR, C_NONE, C_NONE, C_FREG, 53, 4, 0 }, 296 { AMOVFL, C_FREG, C_NONE, C_NONE, C_FPSCR, 64, 4, 0 }, 297 { AMOVFL, C_FREG, C_NONE, C_LCON, C_FPSCR, 64, 4, 0 }, 298 { AMOVFL, C_LCON, C_NONE, C_NONE, C_FPSCR, 65, 4, 0 }, 299 300 { AMOVD, C_MSR, C_NONE, C_NONE, C_REG, 54, 4, 0 }, /* mfmsr */ 301 { AMOVD, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0 }, /* mtmsrd */ 302 { AMOVWZ, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0 }, /* mtmsr */ 303 304 /* 64-bit special registers */ 305 { AMOVD, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0 }, 306 { AMOVD, C_REG, C_NONE, C_NONE, C_LR, 66, 4, 0 }, 307 { AMOVD, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0 }, 308 { AMOVD, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0 }, 309 { AMOVD, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0 }, 310 { AMOVD, C_LR, C_NONE, C_NONE, C_REG, 66, 4, 0 }, 311 { AMOVD, C_CTR, C_NONE, C_NONE, C_REG, 66, 4, 0 }, 312 { AMOVD, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0 }, 313 314 /* 32-bit special registers (gloss over sign-extension or not?) */ 315 { AMOVW, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0 }, 316 { AMOVW, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0 }, 317 { AMOVW, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0 }, 318 { AMOVW, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0 }, 319 { AMOVW, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0 }, 320 321 { AMOVWZ, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0 }, 322 { AMOVWZ, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0 }, 323 { AMOVWZ, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0 }, 324 { AMOVWZ, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0 }, 325 { AMOVWZ, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0 }, 326 327 { AMOVFL, C_FPSCR, C_NONE, C_NONE, C_CREG, 73, 4, 0 }, 328 { AMOVFL, C_CREG, C_NONE, C_NONE, C_CREG, 67, 4, 0 }, 329 { AMOVW, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0 }, 330 { AMOVWZ, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0 }, 331 { AMOVFL, C_REG, C_NONE, C_LCON, C_CREG, 69, 4, 0 }, 332 { AMOVFL, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0 }, 333 { AMOVW, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0 }, 334 { AMOVWZ, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0 }, 335 336 { ACMP, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0 }, 337 { ACMP, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0 }, 338 { ACMP, C_REG, C_NONE, C_NONE, C_ADDCON, 71, 4, 0 }, 339 { ACMP, C_REG, C_REG, C_NONE, C_ADDCON, 71, 4, 0 }, 340 341 { ACMPU, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0 }, 342 { ACMPU, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0 }, 343 { ACMPU, C_REG, C_NONE, C_NONE, C_ANDCON, 71, 4, 0 }, 344 { ACMPU, C_REG, C_REG, C_NONE, C_ANDCON, 71, 4, 0 }, 345 346 { AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 4, 0 }, 347 { AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 4, 0 }, 348 349 { ATW, C_LCON, C_REG, C_NONE, C_REG, 60, 4, 0 }, 350 { ATW, C_LCON, C_REG, C_NONE, C_ADDCON, 61, 4, 0 }, 351 352 { ADCBF, C_ZOREG, C_NONE, C_NONE, C_NONE, 43, 4, 0 }, 353 { ADCBF, C_ZOREG, C_REG, C_NONE, C_NONE, 43, 4, 0 }, 354 355 { AECOWX, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0 }, 356 { AECIWX, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0 }, 357 { AECOWX, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0 }, 358 { AECIWX, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0 }, 359 360 { AEIEIO, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0 }, 361 { ATLBIE, C_REG, C_NONE, C_NONE, C_NONE, 49, 4, 0 }, 362 { ATLBIE, C_SCON, C_NONE, C_NONE, C_REG, 49, 4, 0 }, 363 { ASLBMFEE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0 }, 364 { ASLBMTE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0 }, 365 366 { ASTSW, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0 }, 367 { ASTSW, C_REG, C_NONE, C_LCON, C_ZOREG, 41, 4, 0 }, 368 { ALSW, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0 }, 369 { ALSW, C_ZOREG, C_NONE, C_LCON, C_REG, 42, 4, 0 }, 370 371 { AXXX, C_NONE, C_NONE, C_NONE, C_NONE, 0, 4, 0 }, 372 }; 373