1/* virtex5 ppc440x5 bootstrap tlb entries */ 2#include "mem.h" 3 4#define MB (1024*1024) 5 6/* 7 * TLB prototype entries, loaded once-for-all at startup, 8 * remaining unchanged thereafter. 9 * Limit the table size to ensure it fits in small TLBs. 10 * First entry will be tlb entry #63 and we count down from there. 11 * 12 * Add TLBW for write-through caching. 13 * TLBM doesn't help on the Xilinx virtex 5, alas. 14 * The low 4 bits of the middle word are high bits (33-36) of the RPN; 15 * we set them to zero. 16 */ 17#define TLBE(hi, md, lo) WORD $(hi); WORD $(md); WORD $(lo) 18 19TEXT tlbtab(SB), 1, $-4 20 21 /* 22 * SRAM, 128K. put vectors here. 23 * the `microboot' at the end of SRAM has already installed these 24 * TLB entries for SRAM. 25 */ 26 TLBE(PHYSSRAM | TLB64K | TLBVALID, PHYSSRAM, 27 TLBSR | TLBSX | TLBSW) 28 TLBE(PHYSSRAM+(64*1024) | TLB64K | TLBVALID, PHYSSRAM+(64*1024), 29 TLBSR | TLBSX | TLBSW) 30 31 /* DRAM, 512MB */ 32 TLBE(PHYSDRAM | TLB256MB | TLBVALID, PHYSDRAM, 33 TLBSR | TLBSX | TLBSW) 34 TLBE(PHYSDRAM+(256*MB) | TLB256MB | TLBVALID, PHYSDRAM+(256*MB), 35 TLBSR | TLBSX | TLBSW) 36 37 /* memory-mapped IO, 1MB */ 38 TLBE(PHYSMMIO | TLB1MB | TLBVALID, PHYSMMIO, 39 TLBSR | TLBSW | TLBI | TLBG) 40 41TEXT tlbtabe(SB), 1, $-4 42 RETURN 43