1 typedef struct Mii Mii; 2 typedef struct MiiPhy MiiPhy; 3 4 enum { /* registers */ 5 Bmcr = 0x00, /* Basic Mode Control */ 6 Bmsr = 0x01, /* Basic Mode Status */ 7 Phyidr1 = 0x02, /* PHY Identifier #1 */ 8 Phyidr2 = 0x03, /* PHY Identifier #2 */ 9 Anar = 0x04, /* Auto-Negotiation Advertisement */ 10 Anlpar = 0x05, /* AN Link Partner Ability */ 11 Aner = 0x06, /* AN Expansion */ 12 Annptr = 0x07, /* AN Next Page TX */ 13 Annprr = 0x08, /* AN Next Page RX */ 14 Mscr = 0x09, /* MASTER-SLAVE Control */ 15 Mssr = 0x0a, /* MASTER-SLAVE Status */ 16 Esr = 0x0f, /* Extended Status */ 17 18 NMiiPhyr = 32, 19 NMiiPhy = 32, 20 }; 21 22 enum { /* Bmcr */ 23 BmcrSs1 = 0x0040, /* Speed Select[1] */ 24 BmcrCte = 0x0080, /* Collision Test Enable */ 25 BmcrDm = 0x0100, /* Duplex Mode */ 26 BmcrRan = 0x0200, /* Restart Auto-Negotiation */ 27 BmcrI = 0x0400, /* Isolate */ 28 BmcrPd = 0x0800, /* Power Down */ 29 BmcrAne = 0x1000, /* Auto-Negotiation Enable */ 30 BmcrSs0 = 0x2000, /* Speed Select[0] */ 31 BmcrLe = 0x4000, /* Loopback Enable */ 32 BmcrR = 0x8000, /* Reset */ 33 }; 34 35 enum { /* Bmsr */ 36 BmsrEc = 0x0001, /* Extended Capability */ 37 BmsrJd = 0x0002, /* Jabber Detect */ 38 BmsrLs = 0x0004, /* Link Status */ 39 BmsrAna = 0x0008, /* Auto-Negotiation Ability */ 40 BmsrRf = 0x0010, /* Remote Fault */ 41 BmsrAnc = 0x0020, /* Auto-Negotiation Complete */ 42 BmsrPs = 0x0040, /* Preamble Suppression Capable */ 43 BmsrEs = 0x0100, /* Extended Status */ 44 Bmsr100T2HD = 0x0200, /* 100BASE-T2 HD Capable */ 45 Bmsr100T2FD = 0x0400, /* 100BASE-T2 FD Capable */ 46 Bmsr10THD = 0x0800, /* 10BASE-T HD Capable */ 47 Bmsr10TFD = 0x1000, /* 10BASE-T FD Capable */ 48 Bmsr100TXHD = 0x2000, /* 100BASE-TX HD Capable */ 49 Bmsr100TXFD = 0x4000, /* 100BASE-TX FD Capable */ 50 Bmsr100T4 = 0x8000, /* 100BASE-T4 Capable */ 51 }; 52 53 enum { /* Anar/Anlpar */ 54 Ana10G = 0x0001, 55 56 Ana10HD = 0x0020, /* Advertise 10BASE-T */ 57 Ana10FD = 0x0040, /* Advertise 10BASE-T FD */ 58 AnaTXHD = 0x0080, /* Advertise 100BASE-TX */ 59 AnaTXFD = 0x0100, /* Advertise 100BASE-TX FD */ 60 AnaT4 = 0x0200, /* Advertise 100BASE-T4 */ 61 AnaP = 0x0400, /* Pause */ 62 AnaAP = 0x0800, /* Asymmetrical Pause */ 63 AnaRf = 0x2000, /* Remote Fault */ 64 AnaAck = 0x4000, /* Acknowledge */ 65 AnaNp = 0x8000, /* Next Page Indication */ 66 }; 67 68 enum { /* Mscr */ 69 Mscr1000THD = 0x0100, /* Advertise 1000BASE-T HD */ 70 Mscr1000TFD = 0x0200, /* Advertise 1000BASE-T FD */ 71 }; 72 73 enum { /* Mssr */ 74 Mssr1000THD = 0x0400, /* Link Partner 1000BASE-T HD able */ 75 Mssr1000TFD = 0x0800, /* Link Partner 1000BASE-T FD able */ 76 }; 77 78 enum { /* Esr */ 79 Esr1000THD = 0x1000, /* 1000BASE-T HD Capable */ 80 Esr1000TFD = 0x2000, /* 1000BASE-T FD Capable */ 81 Esr1000XHD = 0x4000, /* 1000BASE-X HD Capable */ 82 Esr1000XFD = 0x8000, /* 1000BASE-X FD Capable */ 83 }; 84 85 typedef struct Mii { 86 Lock; 87 int nphy; 88 int mask; 89 MiiPhy* phy[NMiiPhy]; 90 MiiPhy* curphy; 91 92 void* ctlr; 93 int (*rw)(Mii*, int, int, int, int); 94 } Mii; 95 96 typedef struct MiiPhy { 97 Mii* mii; 98 int phyno; 99 int phyid; 100 int oui; 101 102 int anar; 103 int fc; 104 int mscr; 105 106 int link; 107 int speed; 108 int fd; 109 int rfc; 110 int tfc; 111 }; 112 113 extern int miiane(Mii*, int, int, int); 114 extern Mii* miiattach(void*, int, int (*)(Mii*, int, int, int, int)); 115 extern void miidetach(Mii* mii); 116 extern char* miidumpphy(Mii*, char*, char*); 117 extern int miimir(Mii*, int); 118 extern int miimiw(Mii*, int, int); 119 extern int miireset(Mii*); 120 extern int miistatus(Mii*); 121