1 /* 2 * MultiProcessor Specification Version 1.[14]. 3 */ 4 5 enum { /* table entry types */ 6 PcmpPROCESSOR = 0x00, /* one entry per processor */ 7 PcmpBUS = 0x01, /* one entry per bus */ 8 PcmpIOAPIC = 0x02, /* one entry per I/O APIC */ 9 PcmpIOINTR = 0x03, /* one entry per bus interrupt source */ 10 PcmpLINTR = 0x04, /* one entry per system interrupt source */ 11 12 PcmpSASM = 0x80, 13 PcmpHIERARCHY = 0x81, 14 PcmpCBASM = 0x82, 15 16 /* PCMPprocessor and PCMPioapic flags */ 17 PcmpEN = 0x01, /* enabled */ 18 PcmpBP = 0x02, /* bootstrap processor */ 19 20 /* PCMPiointr and PCMPlintr flags */ 21 PcmpPOMASK = 0x03, /* polarity conforms to specifications of bus */ 22 PcmpHIGH = 0x01, /* active high */ 23 PcmpLOW = 0x03, /* active low */ 24 PcmpELMASK = 0x0C, /* trigger mode of APIC input signals */ 25 PcmpEDGE = 0x04, /* edge-triggered */ 26 PcmpLEVEL = 0x0C, /* level-triggered */ 27 28 /* PCMPiointr and PCMPlintr interrupt type */ 29 PcmpINT = 0x00, /* vectored interrupt from APIC Rdt */ 30 PcmpNMI = 0x01, /* non-maskable interrupt */ 31 PcmpSMI = 0x02, /* system management interrupt */ 32 PcmpExtINT = 0x03, /* vectored interrupt from external PIC */ 33 34 /* PCMPsasm addrtype */ 35 PcmpIOADDR = 0x00, /* I/O address */ 36 PcmpMADDR = 0x01, /* memory address */ 37 PcmpPADDR = 0x02, /* prefetch address */ 38 39 /* PCMPhierarchy info */ 40 PcmpSD = 0x01, /* subtractive decode bus */ 41 42 /* PCMPcbasm modifier */ 43 PcmpPR = 0x01, /* predefined range list */ 44 }; 45 46 enum { 47 MaxAPICNO = 254, /* 255 is physical broadcast */ 48 }; 49 50 enum { /* I/O APIC registers */ 51 IoapicID = 0x00, /* ID */ 52 IoapicVER = 0x01, /* version */ 53 IoapicARB = 0x02, /* arbitration ID */ 54 IoapicRDT = 0x10, /* redirection table */ 55 }; 56 57 /* 58 * Common bits for 59 * I/O APIC Redirection Table Entry; 60 * Local APIC Local Interrupt Vector Table; 61 * Local APIC Inter-Processor Interrupt; 62 * Local APIC Timer Vector Table. 63 */ 64 enum { 65 ApicFIXED = 0x00000000, /* [10:8] Delivery Mode */ 66 ApicLOWEST = 0x00000100, /* Lowest priority */ 67 ApicSMI = 0x00000200, /* System Management Interrupt */ 68 ApicRR = 0x00000300, /* Remote Read */ 69 ApicNMI = 0x00000400, 70 ApicINIT = 0x00000500, /* INIT/RESET */ 71 ApicSTARTUP = 0x00000600, /* Startup IPI */ 72 ApicExtINT = 0x00000700, 73 74 ApicPHYSICAL = 0x00000000, /* [11] Destination Mode (RW) */ 75 ApicLOGICAL = 0x00000800, 76 77 ApicDELIVS = 0x00001000, /* [12] Delivery Status (RO) */ 78 ApicHIGH = 0x00000000, /* [13] Interrupt Input Pin Polarity (RW) */ 79 ApicLOW = 0x00002000, 80 ApicRemoteIRR = 0x00004000, /* [14] Remote IRR (RO) */ 81 ApicEDGE = 0x00000000, /* [15] Trigger Mode (RW) */ 82 ApicLEVEL = 0x00008000, 83 ApicIMASK = 0x00010000, /* [16] Interrupt Mask */ 84 }; 85 86