1 /* 2 * Memory-mapped IO 3 */ 4 5 /* 6 * virtex5 system loses top 1/5th of 512MB to ECC in the secure memory system. 7 */ 8 #define MEMTOP(phys) ((((((phys)/32)*4)/5) * 8*BY2WD) & -128) 9 // #define MAXMEM (512*MB) 10 #define MAXMEM (256*MB) 11 12 /* memory map for rae's virtex5 design */ 13 #define PHYSDRAM 0 14 #define PHYSSRAM 0xfffe0000 /* 128K long, in top 128M */ 15 16 #define PHYSMMIO Io 17 18 #define Io 0xf0000000 /* ~512K of IO registers */ 19 #define Uartlite 0xf0000000 20 #define Gpio 0xf0010000 21 #define Intctlr 0xf0020000 22 #define Temac 0xf0030000 23 #define Llfifo 0xf0040000 24 #define Dmactlr 0xf0050000 25 #define Dmactlr2 0xf0060000 26 /* 27 * if these devices exist in a given hardware configuration, 28 * they will be at these addresses. 29 */ 30 #define Qtm 0xf0070000 /* encrypted memory control */ 31 #define Mpmc 0xf0080000 /* multi-port memory controller */ 32 /* setting low bit interrupts cpu0; don't set Hie */ 33 #define Intctlr2 0xf0090000 /* sw interrupt controller */ 34 35 #define VECBASE PHYSDRAM /* vectors need to be near(ish) handlers */ 36