1 /* 2 * Time. 3 * 4 * HZ should divide 1000 evenly, ideally. 5 * 100, 125, 200, 250 and 333 are okay. 6 */ 7 #define HZ 100 /* clock frequency */ 8 #define MS2HZ (1000/HZ) /* millisec per clock tick */ 9 #define TK2SEC(t) ((t)/HZ) /* ticks to seconds */ 10 11 enum { 12 Mhz = 1000 * 1000, 13 Dogsectimeout = 4, /* must be ≤ 34 s. to fit in a ulong */ 14 }; 15 16 /* 17 * More accurate time 18 */ 19 #define MS2TMR(t) ((ulong)(((uvlong)(t) * m->cpuhz)/1000)) 20 #define US2TMR(t) ((ulong)(((uvlong)(t) * m->cpuhz)/1000000)) 21 22 #define CONSOLE 0 23 24 typedef struct Conf Conf; 25 typedef struct Confmem Confmem; 26 typedef struct FPsave FPsave; 27 typedef struct ISAConf ISAConf; 28 typedef struct Isolated Isolated; 29 typedef struct Label Label; 30 typedef struct Lock Lock; 31 typedef struct Lowmemcache Lowmemcache; 32 typedef struct Memcache Memcache; 33 typedef struct MMMU MMMU; 34 typedef struct Mach Mach; 35 typedef u32int Mreg; /* Msr - bloody UART */ 36 typedef struct Page Page; 37 typedef struct Pcisiz Pcisiz; 38 typedef struct Pcidev Pcidev; 39 typedef struct PhysUart PhysUart; 40 typedef struct PMMU PMMU; 41 typedef struct Proc Proc; 42 typedef u32int PTE; 43 typedef struct Soc Soc; 44 typedef struct Uart Uart; 45 typedef struct Ureg Ureg; 46 typedef uvlong Tval; 47 48 #pragma incomplete Pcidev 49 #pragma incomplete Ureg 50 51 #define MAXSYSARG 5 /* for mount(fd, mpt, flag, arg, srv) */ 52 53 /* 54 * parameters for sysproc.c 55 */ 56 #define AOUT_MAGIC (E_MAGIC) 57 58 struct Lock 59 { 60 ulong key; 61 u32int sr; 62 uintptr pc; 63 Proc* p; 64 Mach* m; 65 int isilock; 66 }; 67 68 struct Label 69 { 70 uintptr sp; 71 uintptr pc; 72 }; 73 74 enum { 75 Maxfpregs = 32, /* could be 16 or 32, see Mach.fpnregs */ 76 Nfpctlregs = 16, 77 }; 78 79 /* 80 * emulated or vfp3 floating point 81 */ 82 struct FPsave 83 { 84 ulong status; 85 ulong control; 86 /* 87 * vfp3 with ieee fp regs; uvlong is sufficient for hardware but 88 * each must be able to hold an Internal from fpi.h for sw emulation. 89 */ 90 ulong regs[Maxfpregs][3]; 91 92 int fpstate; 93 uintptr pc; /* of failed fp instr. */ 94 }; 95 96 /* 97 * FPsave.fpstate 98 */ 99 enum 100 { 101 FPinit, 102 FPactive, 103 FPinactive, 104 FPemu, 105 106 /* bit or'd with the state */ 107 FPillegal= 0x100, 108 }; 109 110 struct Confmem 111 { 112 uintptr base; 113 usize npage; 114 uintptr limit; 115 uintptr kbase; 116 uintptr klimit; 117 }; 118 119 struct Conf 120 { 121 ulong nmach; /* processors */ 122 ulong nproc; /* processes */ 123 Confmem mem[1]; /* physical memory */ 124 ulong npage; /* total physical pages of memory */ 125 usize upages; /* user page pool */ 126 ulong copymode; /* 0 is copy on write, 1 is copy on reference */ 127 ulong ialloc; /* max interrupt time allocation in bytes */ 128 ulong pipeqsize; /* size in bytes of pipe queues */ 129 ulong nimage; /* number of page cache image headers */ 130 ulong nswap; /* number of swap pages */ 131 int nswppo; /* max # of pageouts per segment pass */ 132 ulong hz; /* processor cycle freq */ 133 ulong mhz; 134 int monitor; /* flag */ 135 }; 136 137 /* 138 * MMU stuff in Mach. 139 */ 140 struct MMMU 141 { 142 PTE* mmul1; /* l1 for this processor */ 143 int mmul1lo; 144 int mmul1hi; 145 int mmupid; 146 }; 147 148 /* 149 * MMU stuff in proc 150 */ 151 #define NCOLOR 1 /* 1 level cache, don't worry about VCE's */ 152 struct PMMU 153 { 154 Page* mmul2; 155 Page* mmul2cache; /* free mmu pages */ 156 }; 157 158 #include "../port/portdat.h" 159 160 struct Mach 161 { 162 /* offsets known to asm */ 163 int machno; /* physical id of processor */ 164 uintptr splpc; /* pc of last caller to splhi */ 165 166 Proc* proc; /* current process */ 167 168 MMMU; 169 /* end of offsets known to asm */ 170 int flushmmu; /* flush current proc mmu state */ 171 172 ulong ticks; /* of the clock since boot time */ 173 Label sched; /* scheduler wakeup */ 174 Lock alarmlock; /* access to alarm list */ 175 void* alarm; /* alarms bound to this clock */ 176 int inclockintr; 177 178 Proc* readied; /* for runproc */ 179 ulong schedticks; /* next forced context switch */ 180 181 int cputype; 182 ulong delayloop; 183 184 /* stats */ 185 int tlbfault; 186 int tlbpurge; 187 int pfault; 188 int cs; 189 int syscall; 190 int load; 191 int intr; 192 uvlong fastclock; /* last sampled value */ 193 ulong spuriousintr; 194 int lastintr; 195 int ilockdepth; 196 Perf perf; /* performance counters */ 197 198 int probing; /* probeaddr() state */ 199 int trapped; 200 Lock probelock; 201 int inidlehands; 202 203 int cpumhz; 204 uvlong cpuhz; /* speed of cpu */ 205 uvlong cyclefreq; /* Frequency of user readable cycle counter */ 206 207 /* vfp3 fpu */ 208 int havefp; 209 int havefpvalid; 210 int fpon; 211 int fpconfiged; 212 int fpnregs; 213 ulong fpscr; /* sw copy */ 214 int fppid; /* pid of last fault */ 215 uintptr fppc; /* addr of last fault */ 216 int fpcnt; /* how many consecutive at that addr */ 217 218 /* save areas for exceptions, hold R0-R4 */ 219 u32int sfiq[5]; 220 u32int sirq[5]; 221 u32int sund[5]; 222 u32int sabt[5]; 223 u32int smon[5]; /* probably not needed */ 224 u32int ssys[5]; 225 226 int stack[1]; 227 }; 228 229 /* 230 * Fake kmap. 231 */ 232 typedef void KMap; 233 #define VA(k) ((uintptr)(k)) 234 #define kmap(p) (KMap*)((p)->pa|kseg0) 235 #define kunmap(k) 236 237 struct 238 { 239 Lock; 240 int machs; /* bitmap of active CPUs */ 241 int wfi; /* bitmap of CPUs in WFI state */ 242 int stopped; /* bitmap of CPUs stopped */ 243 int exiting; /* shutdown */ 244 int ispanic; /* shutdown in response to a panic */ 245 int thunderbirdsarego; /* lets the added processors continue to schedinit */ 246 }active; 247 248 extern register Mach* m; /* R10 */ 249 extern register Proc* up; /* R9 */ 250 251 /* an object guaranteed to be in its own cache line */ 252 typedef uchar Cacheline[CACHELINESZ]; 253 struct Isolated { 254 Cacheline c0; 255 ulong word; 256 Cacheline c1; 257 }; 258 259 extern Memcache cachel[]; /* arm arch v7 supports 1-7 */ 260 extern ulong intrcount[MAXMACH]; 261 extern int irqtooearly; 262 extern uintptr kseg0; 263 extern Isolated l1ptstable; 264 extern uchar *l2pages; 265 extern Mach* machaddr[MAXMACH]; 266 extern ulong memsize; 267 extern int navailcpus; 268 extern int normalprint; 269 270 /* 271 * a parsed plan9.ini line 272 */ 273 #define NISAOPT 8 274 275 struct ISAConf { 276 char *type; 277 ulong port; 278 int irq; 279 ulong dma; 280 ulong mem; 281 ulong size; 282 ulong freq; 283 284 int nopt; 285 char *opt[NISAOPT]; 286 }; 287 288 #define MACHP(n) machaddr[n] 289 290 /* 291 * Horrid. But the alternative is 'defined'. 292 */ 293 #ifdef _DBGC_ 294 #define DBGFLG (dbgflg[_DBGC_]) 295 #else 296 #define DBGFLG (0) 297 #endif /* _DBGC_ */ 298 299 int vflag; 300 extern char dbgflg[256]; 301 302 #define dbgprint print /* for now */ 303 304 /* 305 * hardware info about a device 306 */ 307 typedef struct { 308 ulong port; 309 int size; 310 } Devport; 311 312 struct DevConf 313 { 314 ulong intnum; /* interrupt number */ 315 char *type; /* card type, malloced */ 316 int nports; /* Number of ports */ 317 Devport *ports; /* The ports themselves */ 318 }; 319 320 /* characteristics of a given arm cache level */ 321 struct Memcache { 322 uint waysh; /* shifts for set/way register */ 323 uint setsh; 324 325 uint log2linelen; 326 327 uint level; /* 1 is nearest processor, 2 further away */ 328 uint type; 329 uint external; /* flag */ 330 uint l1ip; /* l1 I policy */ 331 332 uint nways; /* associativity */ 333 uint nsets; 334 uint linelen; /* bytes per cache line */ 335 uint setsways; 336 }; 337 enum Cachetype { 338 Nocache, 339 Ionly, 340 Donly, 341 Splitid, 342 Unified, 343 }; 344 enum { 345 Intcache, 346 Extcache, 347 }; 348 349 /* 350 * characteristics of cache level, kept at low, fixed address (CACHECONF). 351 * all offsets are known to cache.v7.s. 352 */ 353 struct Lowmemcache { 354 uint l1waysh; /* shifts for set/way register */ 355 uint l1setsh; 356 uint l2waysh; 357 uint l2setsh; 358 }; 359 360 /* 361 * cache capabilities. write-back vs write-through is controlled 362 * by the Buffered bit in PTEs. 363 * 364 * see cache.v7.s and Memcache in dat.h 365 */ 366 enum { 367 Cawt = 1 << 31, 368 Cawb = 1 << 30, 369 Cara = 1 << 29, 370 Cawa = 1 << 28, 371 }; 372 373 /* non-architectural L2 cache */ 374 typedef struct Cacheimpl Cacheimpl; 375 struct Cacheimpl { 376 void (*info)(Memcache *); 377 void (*on)(void); 378 void (*off)(void); 379 380 void (*inv)(void); 381 void (*wb)(void); 382 void (*wbinv)(void); 383 384 void (*invse)(void *, int); 385 void (*wbse)(void *, int); 386 void (*wbinvse)(void *, int); 387 }; 388 /* extern */ Cacheimpl *l2cache, *allcache, *nocache, *l1cache; 389 390 enum Dmamode { 391 Const, 392 Postincr, 393 Index, 394 Index2, 395 }; 396 397 /* pmu = power management unit */ 398 enum Irqs { 399 /* 400 * 1st 32 gic irqs reserved for cpu; private interrupts. 401 * 0—15 are software-generated by other cpus; 402 * 16—31 are private peripheral intrs. 403 */ 404 Cpu0irq = 0, 405 Cpu1irq, 406 /* ... */ 407 Cpu15irq = 15, 408 Glbtmrirq = 27, 409 Loctmrirq = 29, 410 Wdtmrirq = 30, 411 412 /* shared interrupts */ 413 Ctlr0base = (1+0)*32, /* primary ctlr */ 414 Tn0irq = Ctlr0base + 0, /* tegra timers */ 415 Tn1irq = Ctlr0base + 1, 416 Rtcirq = Ctlr0base + 2, 417 418 Ctlr1base = (1+1)*32, /* secondary ctlr */ 419 Uartirq = Ctlr1base + 4, 420 Tn2irq = Ctlr1base + 9, /* tegra timers */ 421 Tn3irq = Ctlr1base + 10, 422 /* +24 is cpu0_pmu_intr, +25 is cpu1_pum_intr */ 423 424 Ctlr2base = (1+2)*32, /* ternary ctlr */ 425 Extpmuirq = Ctlr2base + 22, 426 427 Ctlr3base = (1+3)*32, /* quad ctlr */ 428 Pcieirq = Ctlr3base + 2, 429 }; 430 431 struct Soc { /* addr's of SoC controllers */ 432 uintptr clkrst; 433 uintptr power; 434 uintptr exceptvec; 435 uintptr sema; 436 uintptr l2cache; 437 uintptr flow; 438 439 /* private memory region */ 440 uintptr scu; 441 uintptr intr; /* `cpu interface' */ 442 /* private-peripheral-interrupt cortex-a clocks */ 443 uintptr glbtmr; 444 uintptr loctmr; 445 446 uintptr intrdist; 447 448 uintptr uart[5]; 449 450 /* shared-peripheral-interrupt tegra2 clocks */ 451 uintptr rtc; /* real-time clock */ 452 uintptr tmr[4]; 453 uintptr µs; 454 455 uintptr pci; 456 uintptr ether; 457 458 uintptr ehci; 459 uintptr ide; 460 461 uintptr nand; 462 uintptr nor; 463 464 uintptr spi[4]; 465 uintptr twsi; 466 uintptr mmc[4]; 467 uintptr gpio[7]; 468 } soc; 469 extern Soc soc; 470