1/* 2 * mips 24k machine assist 3 */ 4#undef MASK 5#define MASK(w) ((1<<(w))-1) 6 7#define SP R29 8 9#define NOP NOR R0, R0, R0 10/* a SPECIAL2 op-code from MIPS32 */ 11#define CLZ(rs,rd) WORD $(0x70000020 | (rs)<<21 | (rd)<<16 | (rd)<<11) 12 13#define CONST(x,r) MOVW $((x)&0xffff0000), r; OR $((x)&0xffff), r 14 15/* a mips 24k erratum requires a NOP after; experience dictates EHB before */ 16#define ERET EHB; WORD $0x42000018; NOP 17 18#define RETURN RET; NOP 19 20/* 21 * R4000 instructions 22 */ 23#define LL(base, rt) WORD $((060<<26)|((base)<<21)|((rt)<<16)) 24#define SC(base, rt) WORD $((070<<26)|((base)<<21)|((rt)<<16)) 25 26/* new instructions in mips 24k (mips32r2) */ 27#define DI(rt) WORD $(0x41606000|((rt)<<16)) /* interrupts off */ 28#define EI(rt) WORD $(0x41606020|((rt)<<16)) /* interrupts on */ 29#define EHB WORD $0xc0 30/* jalr with hazard barrier, link in R22 */ 31#define JALRHB(r) WORD $(((r)<<21)|(22<<11)|(1<<10)|9); NOP 32/* jump register with hazard barrier */ 33#define JRHB(r) WORD $(((r)<<21)|(1<<10)|8); NOP 34#define MFC0(src,sel,dst) WORD $(0x40000000|((src)<<11)|((dst)<<16)|(sel)) 35#define MTC0(src,dst,sel) WORD $(0x40800000|((dst)<<11)|((src)<<16)|(sel)) 36#define MIPS24KNOP NOP /* for erratum #48 */ 37#define RDHWR(hwr, r) WORD $(0x7c00003b|((hwr)<<11)|((r)<<16)) 38#define SYNC WORD $0xf /* all sync barriers */ 39#define WAIT WORD $0x42000020 /* wait for interrupt */ 40 41/* all barriers, clears all hazards; clobbers r/Reg and R22 */ 42#define BARRIERS(r, Reg, label) \ 43 SYNC; EHB; MOVW $ret(SB), Reg; JALRHB(r) 44/* same but return to KSEG1 */ 45#define UBARRIERS(r, Reg, label) \ 46 SYNC; EHB; MOVW $ret(SB), Reg; OR $KSEG1, Reg; JALRHB(r) 47 48#define PUTC(c, r1, r2) CONST(PHYSCONS, r1); MOVW $(c), r2; MOVW r2, (r1); NOP 49 50/* 51 * cache manipulation 52 */ 53 54#define CACHE BREAK /* overloaded op-code */ 55 56#define PI R((0 /* primary I cache */ 57#define PD R((1 /* primary D cache */ 58#define TD R((2 /* tertiary I/D cache */ 59#define SD R((3 /* secondary combined I/D cache */ 60 61#define IWBI (0<<2))) /* index write-back invalidate */ 62#define ILT (1<<2))) /* index load tag */ 63#define IST (2<<2))) /* index store tag */ 64/* #define CDE (3<<2))) /* create dirty exclusive */ 65#define HINV (4<<2))) /* hit invalidate */ 66#define HWBI (5<<2))) /* hit write back invalidate */ 67#define HWB (6<<2))) /* hit write back */ 68/* #define HSV (7<<2))) /* hit set virtual */ 69