1 /* 2 * on return from this function we will be running in virtual mode. 3 * We set up the Block Address Translation (BAT) registers thus: 4 * 1) first 3 BATs are 256M blocks, starting from KZERO->0 5 * 2) remaining BAT maps last 256M directly 6 */ 7 TEXT mmuinit0(SB), $0 8 /* reset all the tlbs */ 9 MOVW $64, R3 10 MOVW R3, CTR 11 MOVW $0, R4 12 tlbloop: 13 TLBIE R4 14 SYNC 15 ADD $BIT(19), R4 16 BDNZ tlbloop 17 TLBSYNC 18 19 /* BATs 0 and 1 cover memory from 0x00000000 to 0x20000000 */ 20 21 /* KZERO -> 0, IBAT and DBAT, 256 MB */ 22 MOVW $(KZERO|(0x7ff<<2)|2), R3 23 MOVW $(PTEVALID|PTEWRITE), R4 /* PTEVALID => Cache coherency on */ 24 MOVW R3, SPR(IBATU(0)) 25 MOVW R4, SPR(IBATL(0)) 26 MOVW R3, SPR(DBATU(0)) 27 MOVW R4, SPR(DBATL(0)) 28 29 /* KZERO+256M -> 256M, IBAT and DBAT, 256 MB */ 30 ADD $(1<<28), R3 31 ADD $(1<<28), R4 32 MOVW R3, SPR(IBATU(1)) 33 MOVW R4, SPR(IBATL(1)) 34 MOVW R3, SPR(DBATU(1)) 35 MOVW R4, SPR(DBATL(1)) 36 37 /* FPGABASE -> FPGABASE, DBAT, 16 MB */ 38 MOVW $(FPGABASE|(0x7f<<2)|2), R3 39 MOVW $(FPGABASE|PTEWRITE|PTEUNCACHED), R4 /* FPGA memory, don't cache */ 40 MOVW R3, SPR(DBATU(2)) 41 MOVW R4, SPR(DBATL(2)) 42 43 /* IBAT 2 unused */ 44 MOVW R0, SPR(IBATU(2)) 45 MOVW R0, SPR(IBATL(2)) 46 47 /* direct map last block, uncached, (not guarded, doesn't work for BAT), DBAT only */ 48 MOVW $(INTMEM|(0x7ff<<2)|2), R3 49 MOVW $(INTMEM|PTEWRITE|PTEUNCACHED), R4 /* Don't set PTEVALID here */ 50 MOVW R3, SPR(DBATU(3)) 51 MOVW R4, SPR(DBATL(3)) 52 53 /* IBAT 3 unused */ 54 MOVW R0, SPR(IBATU(3)) 55 MOVW R0, SPR(IBATL(3)) 56 57 /* enable MMU */ 58 MOVW LR, R3 59 OR $KZERO, R3 60 MOVW R3, SPR(SRR0) /* Stored PC for RFI instruction */ 61 MOVW MSR, R4 62 OR $(MSR_IR|MSR_DR|MSR_RI|MSR_FP), R4 63 MOVW R4, SPR(SRR1) 64 RFI /* resume in kernel mode in caller */ 65 66 RETURN 67