1 /* override default macros from ../port/usb.h */ 2 #undef dprint 3 #undef ddprint 4 #undef deprint 5 #undef ddeprint 6 #define dprint if(ehcidebug)print 7 #define ddprint if(ehcidebug>1)print 8 #define deprint if(ehcidebug || ep->debug)print 9 #define ddeprint if(ehcidebug>1 || ep->debug>1)print 10 11 typedef struct Ctlr Ctlr; 12 typedef struct Eopio Eopio; 13 typedef struct Isoio Isoio; 14 typedef struct Poll Poll; 15 typedef struct Qh Qh; 16 typedef struct Qtree Qtree; 17 18 #pragma incomplete Ctlr; 19 #pragma incomplete Eopio; 20 #pragma incomplete Isoio; 21 #pragma incomplete Poll; 22 #pragma incomplete Qh; 23 #pragma incomplete Qtree; 24 25 struct Poll 26 { 27 Lock; 28 Rendez; 29 int must; 30 int does; 31 }; 32 33 struct Ctlr 34 { 35 Rendez; /* for waiting to async advance doorbell */ 36 Lock; /* for ilock. qh lists and basic ctlr I/O */ 37 QLock portlck; /* for port resets/enable... (and doorbell) */ 38 int active; /* in use or not */ 39 Pcidev* pcidev; 40 Ecapio* capio; /* Capability i/o regs */ 41 Eopio* opio; /* Operational i/o regs */ 42 43 int nframes; /* 1024, 512, or 256 frames in the list */ 44 ulong* frames; /* periodic frame list (hw) */ 45 Qh* qhs; /* async Qh circular list for bulk/ctl */ 46 Qtree* tree; /* tree of Qhs for the periodic list */ 47 int ntree; /* number of dummy qhs in tree */ 48 Qh* intrqhs; /* list of (not dummy) qhs in tree */ 49 Isoio* iso; /* list of active Iso I/O */ 50 ulong load; 51 ulong isoload; 52 int nintr; /* number of interrupts attended */ 53 int ntdintr; /* number of intrs. with something to do */ 54 int nqhintr; /* number of async td intrs. */ 55 int nisointr; /* number of periodic td intrs. */ 56 int nreqs; 57 Poll poll; 58 }; 59 60 /* 61 * Operational registers (hw) 62 */ 63 struct Eopio 64 { 65 ulong cmd; /* 00 command */ 66 ulong sts; /* 04 status */ 67 ulong intr; /* 08 interrupt enable */ 68 ulong frno; /* 0c frame index */ 69 ulong seg; /* 10 bits 63:32 of EHCI datastructs (unused) */ 70 ulong frbase; /* 14 frame list base addr, 4096-byte boundary */ 71 ulong link; /* 18 link for async list */ 72 uchar d2c[0x40-0x1c]; /* 1c dummy */ 73 ulong config; /* 40 1: all ports default-routed to this HC */ 74 ulong portsc[1]; /* 44 Port status and control, one per port */ 75 }; 76 77 extern int ehcidebug; 78 extern Ecapio *ehcidebugcapio; 79 extern int ehcidebugport; 80 81 void ehcilinkage(Hci *hp); 82 void ehcimeminit(Ctlr *ctlr); 83 void ehcirun(Ctlr *ctlr, int on); 84