1 /*
2 * Ralink RT2860 driver
3 *
4 * Written without any documentation but Damien Bergaminis
5 * OpenBSD ral(4) driver sources. Requires ralink firmware
6 * to be present in /lib/firmware/ral-rt2860 on attach.
7 */
8
9 #include "u.h"
10 #include "../port/lib.h"
11 #include "mem.h"
12 #include "dat.h"
13 #include "fns.h"
14 #include "io.h"
15 #include "../port/error.h"
16 #include "../port/netif.h"
17
18 #include "etherif.h"
19 #include "wifi.h"
20
21 /* for consistency */
22 typedef signed char s8int;
23
24 enum {
25 /* PCI registers */
26 PciCfg = 0x0000,
27 PciCfgUsb = (1 << 17),
28 PciCfgPci = (1 << 16),
29 PciEectrl = 0x0004,
30 EectrlC = (1 << 0),
31 EectrlS = (1 << 1),
32 EectrlD = (1 << 2),
33 EectrlShiftD = 2,
34 EectrlQ = (1 << 3),
35 EectrlShiftQ = 3,
36 PciMcuctrl = 0x0008,
37 PciSysctrl = 0x000c,
38 PcieJtag = 0x0010,
39
40 Rt3090AuxCtrl = 0x010c,
41
42 Rt3070Opt14 = 0x0114,
43 };
44
45 enum {
46 /* SCH/DMA registers */
47 IntStatus = 0x0200,
48 /* flags for registers IntStatus/IntMask */
49 TxCoherent = (1 << 17),
50 RxCoherent = (1 << 16),
51 MacInt4 = (1 << 15),
52 MacInt3 = (1 << 14),
53 MacInt2 = (1 << 13),
54 MacInt1 = (1 << 12),
55 MacInt0 = (1 << 11),
56 TxRxCoherent = (1 << 10),
57 McuCmdInt = (1 << 9),
58 TxDoneInt5 = (1 << 8),
59 TxDoneInt4 = (1 << 7),
60 TxDoneInt3 = (1 << 6),
61 TxDoneInt2 = (1 << 5),
62 TxDoneInt1 = (1 << 4),
63 TxDoneInt0 = (1 << 3),
64 RxDoneInt = (1 << 2),
65 TxDlyInt = (1 << 1),
66 RxDlyInt = (1 << 0),
67 IntMask = 0x0204,
68 WpdmaGloCfg = 0x0208,
69 HdrSegLenShift = 8,
70 BigEndian = (1 << 7),
71 TxWbDdone = (1 << 6),
72 WpdmaBtSizeShift = 4,
73 WpdmaBtSize16 = 0,
74 WpdmaBtSize32 = 1,
75 WpdmaBtSize64 = 2,
76 WpdmaBtSize128 = 3,
77 RxDmaBusy = (1 << 3),
78 RxDmaEn = (1 << 2),
79 TxDmaBusy = (1 << 1),
80 TxDmaEn = (1 << 0),
81 WpdmaRstIdx = 0x020c,
82 DelayIntCfg = 0x0210,
83 TxdlyIntEn = (1 << 31),
84 TxmaxPintShift = 24,
85 TxmaxPtimeShift = 16,
86 RxdlyIntEn = (1 << 15),
87 RxmaxPintShift = 8,
88 RxmaxPtimeShift = 0,
89 WmmAifsnCfg = 0x0214,
90 WmmCwminCfg = 0x0218,
91 WmmCwmaxCfg = 0x021c,
92 WmmTxop0Cfg = 0x0220,
93 WmmTxop1Cfg = 0x0224,
94 GpioCtrl = 0x0228,
95 GpioDShift = 8,
96 GpioOShift = 0,
97 McuCmdReg = 0x022c,
98 #define TxBasePtr(qid) (0x0230 + (qid) * 16)
99 #define TxMaxCnt(qid) (0x0234 + (qid) * 16)
100 #define TxCtxIdx(qid) (0x0238 + (qid) * 16)
101 #define TxDtxIdx(qid) (0x023c + (qid) * 16)
102 RxBasePtr = 0x0290,
103 RxMaxCnt = 0x0294,
104 RxCalcIdx = 0x0298,
105 FsDrxIdx = 0x029c,
106 UsbDmaCfg = 0x02a0 /* RT2870 only */,
107 UsbTxBusy = (1 << 31),
108 UsbRxBusy = (1 << 30),
109 UsbEpoutVldShift = 24,
110 UsbTxEn = (1 << 23),
111 UsbRxEn = (1 << 22),
112 UsbRxAggEn = (1 << 21),
113 UsbTxopHalt = (1 << 20),
114 UsbTxClear = (1 << 19),
115 UsbPhyWdEn = (1 << 16),
116 UsbPhyManRst = (1 << 15),
117 #define UsbRxAggLmt(x) ((x) << 8) /* in unit of 1KB */
118 #define UsbRxAggTo(x) ((x) & 0xff) /* in unit of 33ns */
119 UsCycCnt = 0x02a4,
120 TestEn = (1 << 24),
121 TestSelShift = 16,
122 BtModeEn = (1 << 8),
123 UsCycCntShift = 0,
124 };
125
126 enum {
127 /* PBF registers */
128 SysCtrl = 0x0400,
129 HstPmSel = (1 << 16),
130 CapMode = (1 << 14),
131 PmeOen = (1 << 13),
132 Clkselect = (1 << 12),
133 PbfClkEn = (1 << 11),
134 MacClkEn = (1 << 10),
135 DmaClkEn = (1 << 9),
136 McuReady = (1 << 7),
137 AsyReset = (1 << 4),
138 PbfReset = (1 << 3),
139 MacReset = (1 << 2),
140 DmaReset = (1 << 1),
141 McuReset = (1 << 0),
142 HostCmd = 0x0404,
143 McuCmdSleep = 0x30,
144 McuCmdWakeup = 0x31,
145 McuCmdLeds = 0x50,
146 LedRadio = (1 << 13),
147 LedLink2ghz = (1 << 14),
148 LedLink5ghz = (1 << 15),
149 McuCmdLedRssi = 0x51,
150 McuCmdLed1 = 0x52,
151 McuCmdLed2 = 0x53,
152 McuCmdLed3 = 0x54,
153 McuCmdRfreset = 0x72,
154 McuCmdAntsel = 0x73,
155 McuCmdBbp = 0x80,
156 McuCmdPslevel = 0x83,
157 PbfCfg = 0x0408,
158 Tx1qNumShift = 21,
159 Tx2qNumShift = 16,
160 Null0Mode = (1 << 15),
161 Null1Mode = (1 << 14),
162 RxDropMode = (1 << 13),
163 Tx0qManual = (1 << 12),
164 Tx1qManual = (1 << 11),
165 Tx2qManual = (1 << 10),
166 Rx0qManual = (1 << 9),
167 HccaEn = (1 << 8),
168 Tx0qEn = (1 << 4),
169 Tx1qEn = (1 << 3),
170 Tx2qEn = (1 << 2),
171 Rx0qEn = (1 << 1),
172 MaxPcnt = 0x040c,
173 BufCtrl = 0x0410,
174 #define WriteTxq(qid) (1 << (11 - (qid)))
175 Null0Kick = (1 << 7),
176 Null1Kick = (1 << 6),
177 BufReset = (1 << 5),
178 #define ReadTxq(qid) = (1 << (3 - (qid))
179 ReadRx0q = (1 << 0),
180 McuIntSta = 0x0414,
181 /* flags for registers McuIntSta/McuIntEna */
182 McuMacInt8 = (1 << 24),
183 McuMacInt7 = (1 << 23),
184 McuMacInt6 = (1 << 22),
185 McuMacInt4 = (1 << 20),
186 McuMacInt3 = (1 << 19),
187 McuMacInt2 = (1 << 18),
188 McuMacInt1 = (1 << 17),
189 McuMacInt0 = (1 << 16),
190 Dtx0Int = (1 << 11),
191 Dtx1Int = (1 << 10),
192 Dtx2Int = (1 << 9),
193 Drx0Int = (1 << 8),
194 HcmdInt = (1 << 7),
195 N0txInt = (1 << 6),
196 N1txInt = (1 << 5),
197 BcntxInt = (1 << 4),
198 Mtx0Int = (1 << 3),
199 Mtx1Int = (1 << 2),
200 Mtx2Int = (1 << 1),
201 Mrx0Int = (1 << 0),
202 McuIntEna = 0x0418,
203 #define TxqIo(qid) (0x041c + (qid) * 4)
204 Rx0qIo = 0x0424,
205 BcnOffset0 = 0x042c,
206 BcnOffset1 = 0x0430,
207 TxrxqSta = 0x0434,
208 TxrxqPcnt = 0x0438,
209 Rx0qPcntMask = 0xff000000,
210 Tx2qPcntMask = 0x00ff0000,
211 Tx1qPcntMask = 0x0000ff00,
212 Tx0qPcntMask = 0x000000ff,
213 PbfDbg = 0x043c,
214 CapCtrl = 0x0440,
215 CapAdcFeq = (1 << 31),
216 CapStart = (1 << 30),
217 ManTrig = (1 << 29),
218 TrigOffsetShift = 16,
219 StartAddrShift = 0,
220 };
221
222 enum {
223 /* RT3070 registers */
224 Rt3070RfCsrCfg = 0x0500,
225 Rt3070RfKick = (1 << 17),
226 Rt3070RfWrite = (1 << 16),
227 Rt3070EfuseCtrl = 0x0580,
228 Rt3070SelEfuse = (1 << 31),
229 Rt3070EfsromKick = (1 << 30),
230 Rt3070EfsromAinMask = 0x03ff0000,
231 Rt3070EfsromAinShift = 16,
232 Rt3070EfsromModeMask = 0x000000c0,
233 Rt3070EfuseAoutMask = 0x0000003f,
234 Rt3070EfuseData0 = 0x0590,
235 Rt3070EfuseData1 = 0x0594,
236 Rt3070EfuseData2 = 0x0598,
237 Rt3070EfuseData3 = 0x059c,
238 Rt3090OscCtrl = 0x05a4,
239 Rt3070LdoCfg0 = 0x05d4,
240 Rt3070GpioSwitch = 0x05dc,
241 };
242
243 enum {
244 /* MAC registers */
245 AsicVerId = 0x1000,
246 MacSysCtrl = 0x1004,
247 RxTsEn = (1 << 7),
248 WlanHaltEn = (1 << 6),
249 PbfLoopEn = (1 << 5),
250 ContTxTest = (1 << 4),
251 MacRxEn = (1 << 3),
252 MacTxEn = (1 << 2),
253 BbpHrst = (1 << 1),
254 MacSrst = (1 << 0),
255 MacAddrDw0 = 0x1008,
256 MacAddrDw1 = 0x100c,
257 MacBssidDw0 = 0x1010,
258 MacBssidDw1 = 0x1014,
259 MultiBcnNumShift = 18,
260 MultiBssidModeShift = 16,
261 MaxLenCfg = 0x1018,
262 MinMpduLenShift = 16,
263 MaxPsduLenShift = 12,
264 MaxPsduLen8k = 0,
265 MaxPsduLen16k = 1,
266 MaxPsduLen32k = 2,
267 MaxPsduLen64k = 3,
268 MaxMpduLenShift = 0,
269 BbpCsrCfg = 0x101c,
270 BbpRwParallel = (1 << 19),
271 BbpParDur1125 = (1 << 18),
272 BbpCsrKick = (1 << 17),
273 BbpCsrRead = (1 << 16),
274 BbpAddrShift = 8,
275 BbpDataShift = 0,
276 RfCsrCfg0 = 0x1020,
277 RfRegCtrl = (1 << 31),
278 RfLeSel1 = (1 << 30),
279 RfLeStby = (1 << 29),
280 RfRegWidthShift = 24,
281 RfReg0Shift = 0,
282 RfCsrCfg1 = 0x1024,
283 RfDur5 = (1 << 24),
284 RfReg1Shift = 0,
285 RfCsrCfg2 = 0x1028,
286 LedCfg = 0x102c,
287 LedPol = (1 << 30),
288 YLedModeShift = 28,
289 GLedModeShift = 26,
290 RLedModeShift = 24,
291 LedModeOff = 0,
292 LedModeBlinkTx = 1,
293 LedModeSlowBlink = 2,
294 LedModeOn = 3,
295 SlowBlkTimeShift = 16,
296 LedOffTimeShift = 8,
297 LedOnTimeShift = 0,
298 };
299
300 enum {
301 /* undocumented registers */
302 Debug = 0x10f4,
303 };
304
305 enum {
306 /* MAC Timing control registers */
307 XifsTimeCfg = 0x1100,
308 BbRxendEn = (1 << 29),
309 EifsTimeShift = 20,
310 OfdmXifsTimeShift = 16,
311 OfdmSifsTimeShift = 8,
312 CckSifsTimeShift = 0,
313 BkoffSlotCfg = 0x1104,
314 CcDelayTimeShift = 8,
315 SlotTime = 0,
316 NavTimeCfg = 0x1108,
317 NavUpd = (1 << 31),
318 NavUpdValShift = 16,
319 NavClrEn = (1 << 15),
320 NavTimerShift = 0,
321 ChTimeCfg = 0x110c,
322 EifsAsChBusy = (1 << 4),
323 NavAsChBusy = (1 << 3),
324 RxAsChBusy = (1 << 2),
325 TxAsChBusy = (1 << 1),
326 ChStaTimerEn = (1 << 0),
327 PbfLifeTimer = 0x1110,
328 BcnTimeCfg = 0x1114,
329 TsfInsCompShift = 24,
330 BcnTxEn = (1 << 20),
331 TbttTimerEn = (1 << 19),
332 TsfSyncModeShift = 17,
333 TsfSyncModeDis = 0,
334 TsfSyncModeSta = 1,
335 TsfSyncModeIbss = 2,
336 TsfSyncModeHostap = 3,
337 TsfTimerEn = (1 << 16),
338 BcnIntvalShift = 0,
339 TbttSyncCfg = 0x1118,
340 BcnCwminShift = 20,
341 BcnAifsnShift = 16,
342 BcnExpWinShift = 8,
343 TbttAdjustShift = 0,
344 TsfTimerDw0 = 0x111c,
345 TsfTimerDw1 = 0x1120,
346 TbttTimer = 0x1124,
347 IntTimerCfg = 0x1128,
348 GpTimerShift = 16,
349 PreTbttTimerShift = 0,
350 IntTimerEn = 0x112c,
351 GpTimerEn = (1 << 1),
352 PreTbttIntEn = (1 << 0),
353 ChIdleTime = 0x1130,
354 };
355
356 enum {
357 /* MAC Power Save configuration registers */
358 MacStatusReg = 0x1200,
359 RxStatusBusy = (1 << 1),
360 TxStatusBusy = (1 << 0),
361 PwrPinCfg = 0x1204,
362 IoAddaPd = (1 << 3),
363 IoPllPd = (1 << 2),
364 IoRaPe = (1 << 1),
365 IoRfPe = (1 << 0),
366 AutoWakeupCfg = 0x1208,
367 AutoWakeupEn = (1 << 15),
368 SleepTbttNumShift = 8,
369 WakeupLeadTimeShift = 0,
370 };
371
372 enum {
373 /* MAC TX configuration registers */
374 #define EdcaAcCfg(aci) (0x1300 + (aci) * 4)
375 EdcaTidAcMap = 0x1310,
376 #define TxPwrCfg(ridx) (0x1314 + (ridx) * 4)
377 TxPinCfg = 0x1328,
378 Rt3593LnaPeG2Pol = (1 << 31),
379 Rt3593LnaPeA2Pol = (1 << 30),
380 Rt3593LnaPeG2En = (1 << 29),
381 Rt3593LnaPeA2En = (1 << 28),
382 Rt3593LnaPe2En = (Rt3593LnaPeA2En | Rt3593LnaPeG2En),
383 Rt3593PaPeG2Pol = (1 << 27),
384 Rt3593PaPeA2Pol = (1 << 26),
385 Rt3593PaPeG2En = (1 << 25),
386 Rt3593PaPeA2En = (1 << 24),
387 TrswPol = (1 << 19),
388 TrswEn = (1 << 18),
389 RftrPol = (1 << 17),
390 RftrEn = (1 << 16),
391 LnaPeG1Pol = (1 << 15),
392 LnaPeA1Pol = (1 << 14),
393 LnaPeG0Pol = (1 << 13),
394 LnaPeA0Pol = (1 << 12),
395 LnaPeG1En = (1 << 11),
396 LnaPeA1En = (1 << 10),
397 LnaPe1En = (LnaPeA1En | LnaPeG1En),
398 LnaPeG0En = (1 << 9),
399 LnaPeA0En = (1 << 8),
400 LnaPe0En = (LnaPeA0En | LnaPeG0En),
401 PaPeG1Pol = (1 << 7),
402 PaPeA1Pol = (1 << 6),
403 PaPeG0Pol = (1 << 5),
404 PaPeA0Pol = (1 << 4),
405 PaPeG1En = (1 << 3),
406 PaPeA1En = (1 << 2),
407 PaPeG0En = (1 << 1),
408 PaPeA0En = (1 << 0),
409 TxBandCfg = 0x132c,
410 Tx5gBandSelN = (1 << 2),
411 Tx5gBandSelP = (1 << 1),
412 TxBandSel = (1 << 0),
413 TxSwCfg0 = 0x1330,
414 DlyRftrEnShift = 24,
415 DlyTrswEnShift = 16,
416 DlyPapeEnShift = 8,
417 DlyTxpeEnShift = 0,
418 TxSwCfg1 = 0x1334,
419 DlyRftrDisShift = 16,
420 DlyTrswDisShift = 8,
421 DlyPapeDisShift = 0,
422 TxSwCfg2 = 0x1338,
423 DlyLnaEnShift = 24,
424 DlyLnaDisShift = 16,
425 DlyDacEnShift = 8,
426 DlyDacDisShift = 0,
427 TxopThresCfg = 0x133c,
428 TxopRemThresShift = 24,
429 CfEndThresShift = 16,
430 RdgInThres = 8,
431 RdgOutThres = 0,
432 TxopCtrlCfg = 0x1340,
433 ExtCwMinShift = 16,
434 ExtCcaDlyShift = 8,
435 ExtCcaEn = (1 << 7),
436 LsigTxopEn = (1 << 6),
437 TxopTrunEnMimops = (1 << 4),
438 TxopTrunEnTxop = (1 << 3),
439 TxopTrunEnRate = (1 << 2),
440 TxopTrunEnAc = (1 << 1),
441 TxopTrunEnTimeout = (1 << 0),
442 TxRtsCfg = 0x1344,
443 RtsFbkEn = (1 << 24),
444 RtsThresShift = 8,
445 RtsRtyLimitShift = 0,
446 TxTimeoutCfg = 0x1348,
447 TxopTimeoutShift = 16,
448 RxAckTimeoutShift = 8,
449 MpduLifeTimeShift = 4,
450 TxRtyCfg = 0x134c,
451 TxAutofbEn = (1 << 30),
452 AggRtyModeTimer = (1 << 29),
453 NagRtyModeTimer = (1 << 28),
454 LongRtyThresShift = 16,
455 LongRtyLimitShift = 8,
456 ShortRtyLimitShift = 0,
457 TxLinkCfg = 0x1350,
458 RemoteMfsShift = 24,
459 RemoteMfbShift = 16,
460 TxCfackEn = (1 << 12),
461 TxRdgEn = (1 << 11),
462 TxMrqEn = (1 << 10),
463 RemoteUmfsEn = (1 << 9),
464 TxMfbEn = (1 << 8),
465 RemoteMfbLtShift = 0,
466 HtFbkCfg0 = 0x1354,
467 HtFbkCfg1 = 0x1358,
468 LgFbkCfg0 = 0x135c,
469 LgFbkCfg1 = 0x1360,
470 CckProtCfg = 0x1364,
471 /* possible flags for registers *ProtCfg */
472 RtsthEn = (1 << 26),
473 TxopAllowGf40 = (1 << 25),
474 TxopAllowGf20 = (1 << 24),
475 TxopAllowMm40 = (1 << 23),
476 TxopAllowMm20 = (1 << 22),
477 TxopAllowOfdm = (1 << 21),
478 TxopAllowCck = (1 << 20),
479 TxopAllowAll = (0x3f << 20),
480 ProtNavShort = (1 << 18),
481 ProtNavLong = (2 << 18),
482 ProtCtrlRtsCts = (1 << 16),
483 ProtCtrlCts = (2 << 16),
484 OfdmProtCfg = 0x1368,
485 Mm20ProtCfg = 0x136c,
486 Mm40ProtCfg = 0x1370,
487 Gf20ProtCfg = 0x1374,
488 Gf40ProtCfg = 0x1378,
489 ExpCtsTime = 0x137c,
490 /* possible flags for registers EXP_{CTS,ACK}_TIME */
491 ExpOfdmTimeShift = 16,
492 ExpCckTimeShift = 0,
493 ExpAckTime = 0x1380,
494 };
495
496 enum {
497 /* MAC RX configuration registers */
498 RxFiltrCfg = 0x1400,
499 DropCtrlRsv = (1 << 16),
500 DropBar = (1 << 15),
501 DropBa = (1 << 14),
502 DropPspoll = (1 << 13),
503 DropRts = (1 << 12),
504 DropCts = (1 << 11),
505 DropAck = (1 << 10),
506 DropCfend = (1 << 9),
507 DropCfack = (1 << 8),
508 DropDupl = (1 << 7),
509 DropBc = (1 << 6),
510 DropMc = (1 << 5),
511 DropVerErr = (1 << 4),
512 DropNotMybss = (1 << 3),
513 DropUcNome = (1 << 2),
514 DropPhyErr = (1 << 1),
515 DropCrcErr = (1 << 0),
516 AutoRspCfg = 0x1404,
517 CtrlPwrBit = (1 << 7),
518 BacAckPolicy = (1 << 6),
519 CckShortEn = (1 << 4),
520 Cts40mRefEn = (1 << 3),
521 Cts40mModeEn = (1 << 2),
522 BacAckpolicyEn = (1 << 1),
523 AutoRspEn = (1 << 0),
524 LegacyBasicRate = 0x1408,
525 HtBasicRate = 0x140c,
526 HtCtrlCfg = 0x1410,
527 SifsCostCfg = 0x1414,
528 OfdmSifsCostShift = 8,
529 CckSifsCostShift = 0,
530 RxParserCfg = 0x1418,
531 };
532
533 enum {
534 /* MAC Security configuration registers */
535 TxSecCnt0 = 0x1500,
536 RxSecCnt0 = 0x1504,
537 CcmpFcMute = 0x1508,
538 };
539
540 enum {
541 /* MAC HCCA/PSMP configuration registers */
542 TxopHldrAddr0 = 0x1600,
543 TxopHldrAddr1 = 0x1604,
544 TxopHldrEt = 0x1608,
545 TxopEtm1En = (1 << 25),
546 TxopEtm0En = (1 << 24),
547 TxopEtmThresShift = 16,
548 TxopEtoEn = (1 << 8),
549 TxopEtoThresShift = 1,
550 PerRxRstEn = (1 << 0),
551 QosCfpollRaDw0 = 0x160c,
552 QosCfpollA1Dw1 = 0x1610,
553 QosCfpollQc = 0x1614,
554 };
555
556 enum {
557 /* MAC Statistics Counters */
558 RxStaCnt0 = 0x1700,
559 RxStaCnt1 = 0x1704,
560 RxStaCnt2 = 0x1708,
561 TxStaCnt0 = 0x170c,
562 TxStaCnt1 = 0x1710,
563 TxStaCnt2 = 0x1714,
564 TxStatFifo = 0x1718,
565 TxqMcsShift = 16,
566 TxqWcidShift = 8,
567 TxqAckreq = (1 << 7),
568 TxqAgg = (1 << 6),
569 TxqOk = (1 << 5),
570 TxqPidShift = 1,
571 TxqVld = (1 << 0),
572 };
573
574 /* RX WCID search table */
575 #define WcidEntry(wcid) (0x1800 + (wcid) * 8)
576
577 enum {
578 FwBase = 0x2000,
579 Rt2870FwBase = 0x3000,
580 };
581
582 /* Pair-wise key table */
583 #define Pkey(wcid) (0x4000 + (wcid) * 32)
584
585 /* IV/EIV table */
586 #define Iveiv(wcid) (0x6000 + (wcid) * 8)
587
588 /* WCID attribute table */
589 #define WcidAttr(wcid) (0x6800 + (wcid) * 4)
590
591 /* possible flags for register WCID_ATTR */
592 enum {
593 ModeNosec = 0,
594 ModeWep40 = 1,
595 ModeWep104 = 2,
596 ModeTkip = 3,
597 ModeAesCcmp = 4,
598 ModeCkip40 = 5,
599 ModeCkip104 = 6,
600 ModeCkip128 = 7,
601 RxPkeyEn = (1 << 0),
602 };
603
604 /* Shared Key Table */
605 #define Skey(vap, kidx) (0x6c00 + (vap) * 128 + (kidx) * 32)
606
607 /* Shared Key Mode */
608 enum {
609 SkeyMode07 = 0x7000,
610 SkeyMode815 = 0x7004,
611 SkeyMode1623 = 0x7008,
612 SkeyMode2431 = 0x700c,
613 };
614
615 enum {
616 /* Shared Memory between MCU and host */
617 H2mMailbox = 0x7010,
618 H2mBusy = (1 << 24),
619 TokenNoIntr = 0xff,
620 H2mMailboxCid = 0x7014,
621 H2mMailboxStatus = 0x701c,
622 H2mBbpagent = 0x7028,
623 #define BcnBase(vap) (0x7800 + (vap) * 512)
624 };
625
626 /*
627 * RT2860 TX descriptor
628 * --------------------
629 * u32int sdp0 Segment Data Pointer 0
630 * u16int sdl1 Segment Data Length 1
631 * u16int sdl0 Segment Data Length 0
632 * u32int sdp1 Segment Data Pointer 1
633 * u8int reserved[3]
634 * u8int flags
635 */
636
637 enum {
638 /* sdl1 flags */
639 TxBurst = (1 << 15),
640 TxLs1 = (1 << 14) /* SDP1 is the last segment */,
641 /* sdl0 flags */
642 TxDdone = (1 << 15),
643 TxLs0 = (1 << 14) /* SDP0 is the last segment */,
644 /* flags */
645 TxQselShift = 1,
646 TxQselMgmt = (0 << 1),
647 TxQselHcca = (1 << 1),
648 TxQselEdca = (2 << 1),
649 TxWiv = (1 << 0),
650 };
651
652 /*
653 * TX Wireless Information
654 * -----------------------
655 * u8int flags
656 * u8int txop
657 * u16int phy
658 * u8int xflags
659 * u8int wcid Wireless Client ID
660 * u16int len
661 * u32int iv
662 * u32int eiv
663 */
664
665 enum {
666 /* flags */
667 TxMpduDsityShift = 5,
668 TxAmpdu = (1 << 4),
669 TxTs = (1 << 3),
670 TxCfack = (1 << 2),
671 TxMmps = (1 << 1),
672 TxFrag = (1 << 0),
673 /* txop */
674 TxTxopHt = 0,
675 TxTxopPifs = 1,
676 TxTxopSifs = 2,
677 TxTxopBackoff = 3,
678 /* phy */
679 PhyMode = 0xc000,
680 PhyCck = (0 << 14),
681 PhyOfdm = (1 << 14),
682 PhyHt = (2 << 14),
683 PhyHtGf = (3 << 14),
684 PhySgi = (1 << 8),
685 PhyBw40 = (1 << 7),
686 PhyMcs = 0x7f,
687 PhyShpre = (1 << 3),
688 /* xflags */
689 TxBawinsizeShift = 2,
690 TxNseq = (1 << 1),
691 TxAck = (1 << 0),
692 /* len */
693 TxPidShift = 12,
694 };
695
696 /*
697 * RT2860 RX descriptor
698 * --------------------
699 * u32int sdp0
700 * u16int sdl1 unused
701 * u16int sdl0
702 * u32int sdp1 unused
703 * u32int flags
704 */
705
706 enum {
707 /* sdl flags */
708 RxDdone = (1 << 15),
709 RxLs0 = (1 << 14),
710 /* flags */
711 RxDec = (1 << 16),
712 RxAmpdu = (1 << 15),
713 RxL2pad = (1 << 14),
714 RxRssi = (1 << 13),
715 RxHtc = (1 << 12),
716 RxAmsdu = (1 << 11),
717 RxMicerr = (1 << 10),
718 RxIcverr = (1 << 9),
719 RxCrcerr = (1 << 8),
720 RxMybss = (1 << 7),
721 RxBc = (1 << 6),
722 RxMc = (1 << 5),
723 RxUc2me = (1 << 4),
724 RxFrag = (1 << 3),
725 RxNull = (1 << 2),
726 RxData = (1 << 1),
727 RxBa = (1 << 0),
728 };
729
730 /*
731 * RX Wireless Information
732 * -----------------------
733 * u8int wcid
734 * u8int keyidx
735 * u16int len
736 * u16int seq
737 * u16int phy
738 * u8int rssi[3]
739 * u8int reserved1
740 * u8int snr[2]
741 * u16int reserved2
742 */
743
744 enum {
745 /* keyidx flags */
746 RxUdfShift = 5,
747 RxBssIdxShift = 2,
748 /* len flags */
749 RxTidShift = 12,
750 };
751
752 enum {
753 WIFIHDRSIZE = 2+2+3*6+2,
754 Rdscsize = 16,
755 Tdscsize = 16,
756 Rbufsize = 4096,
757 Tbufsize = 4096,
758 Rxwisize = 16,
759 Txwisize = 16,
760 /* first DMA segment contains TXWI + 802.11 header + 32-bit padding */
761 TxwiDmaSz = Txwisize + WIFIHDRSIZE + 2
762 };
763
764 /* RF registers */
765 enum {
766 Rf1 = 0,
767 Rf2 = 2,
768 Rf3 = 1,
769 Rf4 = 3,
770 };
771
772 enum {
773 Rf2820 = 1 /* 2T3R */,
774 Rf2850 = 2 /* dual-band 2T3R */,
775 Rf2720 = 3 /* 1T2R */,
776 Rf2750 = 4 /* dual-band 1T2R */,
777 Rf3020 = 5 /* 1T1R */,
778 Rf2020 = 6 /* b/g */,
779 Rf3021 = 7 /* 1T2R */,
780 Rf3022 = 8 /* 2T2R */,
781 Rf3052 = 9 /* dual-band 2T2R */,
782 Rf3320 = 11 /* 1T1R */,
783 Rf3053 = 13 /* dual-band 3T3R */,
784 };
785
786 enum {
787 Rt3070RfBlock = (1 << 0),
788 Rt3070Rx0Pd = (1 << 2),
789 Rt3070Tx0Pd = (1 << 3),
790 Rt3070Rx1Pd = (1 << 4),
791 Rt3070Tx1Pd = (1 << 5),
792 Rt3070Rx2Pd = (1 << 6),
793 Rt3070Tx2Pd = (1 << 7),
794 Rt3070Tune = (1 << 0),
795 Rt3070TxLo2 = (1 << 3),
796 Rt3070TxLo1 = (1 << 3),
797 Rt3070RxLo1 = (1 << 3),
798 Rt3070RxLo2 = (1 << 3),
799 Rt3070RxCtb = (1 << 7),
800 Rt3070BbLoopback = (1 << 0),
801
802 Rt3593Vco = (1 << 0),
803 Rt3593Rescal = (1 << 7),
804 Rt3593Vcocal = (1 << 7),
805 Rt3593VcoIc = (1 << 6),
806 Rt3593LdoPllVcMask = 0x0e,
807 Rt3593LdoRfVcMask = 0xe0,
808 Rt3593CpIcMask = 0xe0,
809 Rt3593CpIcShift = 5,
810 Rt3593RxCtb = (1 << 5)
811 };
812
813 static const char* rfnames[] = {
814 [Rf2820] "RT2820",
815 [Rf2850] "RT2850",
816 [Rf2720] "RT2720",
817 [Rf2750] "RT2750",
818 [Rf3020] "RT3020",
819 [Rf2020] "RT2020",
820 [Rf3021] "RT3021",
821 [Rf3022] "RT3022",
822 [Rf3052] "RT3052",
823 [Rf3320] "RT3320",
824 [Rf3053] "RT3053",
825 };
826
827 enum {
828 /* USB commands, RT2870 only */
829 Rt2870Reset = 1,
830 Rt2870Write2 = 2,
831 Rt2870WriteRegion1 = 6,
832 Rt2870ReadRegion1 = 7,
833 Rt2870EepromRead = 9,
834 };
835
836 enum {
837 EepromDelay = 1 /* minimum hold time (microsecond) */,
838
839 EepromVersion = 0x01,
840 EepromMac01 = 0x02,
841 EepromMac23 = 0x03,
842 EepromMac45 = 0x04,
843 EepromPciePslevel = 0x11,
844 EepromRev = 0x12,
845 EepromAntenna = 0x1a,
846 EepromConfig = 0x1b,
847 EepromCountry = 0x1c,
848 EepromFreqLeds = 0x1d,
849 EepromLed1 = 0x1e,
850 EepromLed2 = 0x1f,
851 EepromLed3 = 0x20,
852 EepromLna = 0x22,
853 EepromRssi12ghz = 0x23,
854 EepromRssi22ghz = 0x24,
855 EepromRssi15ghz = 0x25,
856 EepromRssi25ghz = 0x26,
857 EepromDeltapwr = 0x28,
858 EepromPwr2ghzBase1 = 0x29,
859 EepromPwr2ghzBase2 = 0x30,
860 EepromTssi12ghz = 0x37,
861 EepromTssi22ghz = 0x38,
862 EepromTssi32ghz = 0x39,
863 EepromTssi42ghz = 0x3a,
864 EepromTssi52ghz = 0x3b,
865 EepromPwr5ghzBase1 = 0x3c,
866 EepromPwr5ghzBase2 = 0x53,
867 EepromTssi15ghz = 0x6a,
868 EepromTssi25ghz = 0x6b,
869 EepromTssi35ghz = 0x6c,
870 EepromTssi45ghz = 0x6d,
871 EepromTssi55ghz = 0x6e,
872 EepromRpwr = 0x6f,
873 EepromBbpBase = 0x78,
874 Rt3071EepromRfBase = 0x82,
875 };
876
877 enum {
878 RidxCck1 = 0,
879 RidxCck11 = 3,
880 RidxOfdm6 = 4,
881 RidxMax = 11,
882 };
883
884 /* ring and pool count */
885 enum {
886 Nrx = 128,
887 Ntx = 64,
888 Ntxpool = Ntx * 2
889 };
890
891 typedef struct FWImage FWImage;
892 typedef struct TXQ TXQ;
893 typedef struct RXQ RXQ;
894 typedef struct Pool Pool;
895
896 typedef struct Ctlr Ctlr;
897
898 struct FWImage {
899 uint size;
900 uchar *data;
901 };
902
903 struct TXQ
904 {
905 uint n; /* next */
906 uint i; /* current */
907 Block **b;
908 u32int *d; /* descriptors */
909
910 Rendez;
911 QLock;
912 };
913
914 struct RXQ
915 {
916 uint i;
917 Block **b;
918 u32int *p;
919 };
920
921 struct Pool
922 {
923 uint i; /* current */
924 uchar *p; /* txwi */
925 };
926
927 struct Ctlr {
928 Lock;
929 QLock;
930
931 Ctlr *link;
932 Pcidev *pdev;
933 Wifi *wifi;
934
935 u16int mac_ver;
936 u16int mac_rev;
937 u8int rf_rev;
938 u8int freq;
939 u8int ntxchains;
940 u8int nrxchains;
941 u8int pslevel;
942 s8int txpow1[54];
943 s8int txpow2[54];
944 s8int rssi_2ghz[3];
945 s8int rssi_5ghz[3];
946 u8int lna[4];
947 u8int rf24_20mhz;
948 u8int rf24_40mhz;
949 u8int patch_dac;
950 u8int rfswitch;
951 u8int ext_2ghz_lna;
952 u8int ext_5ghz_lna;
953 u8int calib_2ghz;
954 u8int calib_5ghz;
955 u8int txmixgain_2ghz;
956 u8int txmixgain_5ghz;
957 u8int tssi_2ghz[9];
958 u8int tssi_5ghz[9];
959 u8int step_2ghz;
960 u8int step_5ghz;
961 uint mgtqid;
962
963 struct {
964 u8int reg;
965 u8int val;
966 } bbp[8], rf[10];
967 u8int leds;
968 u16int led[3];
969 u32int txpow20mhz[5];
970 u32int txpow40mhz_2ghz[5];
971 u32int txpow40mhz_5ghz[5];
972
973 int flags;
974
975 int port;
976 int power;
977 int active;
978 int broken;
979 int attached;
980
981 u32int *nic;
982
983 /* assigned node ids in hardware node table or -1 if unassigned */
984 int bcastnodeid;
985 int bssnodeid;
986 u8int wcid;
987 /* current receiver settings */
988 uchar bssid[Eaddrlen];
989 int channel;
990 int prom;
991 int aid;
992
993 RXQ rx;
994 TXQ tx[6];
995 Pool pool;
996
997 FWImage *fw;
998 };
999
1000 /* controller flags */
1001 enum {
1002 AdvancedPs = 1 << 0,
1003 ConnPciE = 1 << 1,
1004 };
1005
1006 static const struct rt2860_rate {
1007 u8int rate;
1008 u8int mcs;
1009 /*enum ieee80211_phytype phy;*/
1010 u8int ctl_ridx;
1011 u16int sp_ack_dur;
1012 u16int lp_ack_dur;
1013 } rt2860_rates[] = {
1014 { 2, 0,/* IEEE80211_T_DS,*/ 0, 314, 314 },
1015 { 4, 1,/* IEEE80211_T_DS,*/ 1, 258, 162 },
1016 { 11, 2,/* IEEE80211_T_DS,*/ 2, 223, 127 },
1017 { 22, 3,/* IEEE80211_T_DS,*/ 3, 213, 117 },
1018 { 12, 0,/* IEEE80211_T_OFDM,*/ 4, 60, 60 },
1019 { 18, 1,/* IEEE80211_T_OFDM,*/ 4, 52, 52 },
1020 { 24, 2,/* IEEE80211_T_OFDM,*/ 6, 48, 48 },
1021 { 36, 3,/* IEEE80211_T_OFDM,*/ 6, 44, 44 },
1022 { 48, 4,/* IEEE80211_T_OFDM,*/ 8, 44, 44 },
1023 { 72, 5,/* IEEE80211_T_OFDM,*/ 8, 40, 40 },
1024 { 96, 6,/* IEEE80211_T_OFDM,*/ 8, 40, 40 },
1025 { 108, 7,/* IEEE80211_T_OFDM,*/ 8, 40, 40 }
1026 };
1027
1028 /*
1029 * Default values for MAC registers; values taken from the reference driver.
1030 */
1031 static const struct {
1032 u32int reg;
1033 u32int val;
1034 } rt2860_def_mac[] = {
1035 { BcnOffset0, 0xf8f0e8e0 },
1036 { LegacyBasicRate, 0x0000013f },
1037 { HtBasicRate, 0x00008003 },
1038 { MacSysCtrl, 0x00000000 },
1039 { BkoffSlotCfg, 0x00000209 },
1040 { TxSwCfg0, 0x00000000 },
1041 { TxSwCfg1, 0x00080606 },
1042 { TxLinkCfg, 0x00001020 },
1043 { TxTimeoutCfg, 0x000a2090 },
1044 { LedCfg, 0x7f031e46 },
1045 { WmmAifsnCfg, 0x00002273 },
1046 { WmmCwminCfg, 0x00002344 },
1047 { WmmCwmaxCfg, 0x000034aa },
1048 { MaxPcnt, 0x1f3fbf9f },
1049 { TxRtyCfg, 0x47d01f0f },
1050 { AutoRspCfg, 0x00000013 },
1051 { CckProtCfg, 0x05740003 },
1052 { OfdmProtCfg, 0x05740003 },
1053 { Gf20ProtCfg, 0x01744004 },
1054 { Gf40ProtCfg, 0x03f44084 },
1055 { Mm20ProtCfg, 0x01744004 },
1056 { Mm40ProtCfg, 0x03f54084 },
1057 { TxopCtrlCfg, 0x0000583f },
1058 { TxopHldrEt, 0x00000002 },
1059 { TxRtsCfg, 0x00092b20 },
1060 { ExpAckTime, 0x002400ca },
1061 { XifsTimeCfg, 0x33a41010 },
1062 { PwrPinCfg, 0x00000003 },
1063 };
1064
1065 /*
1066 * Default values for BBP registers; values taken from the reference driver.
1067 */
1068 static const struct {
1069 u8int reg;
1070 u8int val;
1071 } rt2860_def_bbp[] = {
1072 { 65, 0x2c },
1073 { 66, 0x38 },
1074 { 69, 0x12 },
1075 { 70, 0x0a },
1076 { 73, 0x10 },
1077 { 81, 0x37 },
1078 { 82, 0x62 },
1079 { 83, 0x6a },
1080 { 84, 0x99 },
1081 { 86, 0x00 },
1082 { 91, 0x04 },
1083 { 92, 0x00 },
1084 { 103, 0x00 },
1085 { 105, 0x05 },
1086 { 106, 0x35 },
1087 };
1088
1089 /*
1090 * Default settings for RF registers; values derived from the reference driver.
1091 */
1092 static const struct rfprog {
1093 u8int chan;
1094 u32int r1, r2, r3, r4;
1095 } rt2860_rf2850[] = {
1096 { 1, 0x100bb3, 0x1301e1, 0x05a014, 0x001402 },
1097 { 2, 0x100bb3, 0x1301e1, 0x05a014, 0x001407 },
1098 { 3, 0x100bb3, 0x1301e2, 0x05a014, 0x001402 },
1099 { 4, 0x100bb3, 0x1301e2, 0x05a014, 0x001407 },
1100 { 5, 0x100bb3, 0x1301e3, 0x05a014, 0x001402 },
1101 { 6, 0x100bb3, 0x1301e3, 0x05a014, 0x001407 },
1102 { 7, 0x100bb3, 0x1301e4, 0x05a014, 0x001402 },
1103 { 8, 0x100bb3, 0x1301e4, 0x05a014, 0x001407 },
1104 { 9, 0x100bb3, 0x1301e5, 0x05a014, 0x001402 },
1105 { 10, 0x100bb3, 0x1301e5, 0x05a014, 0x001407 },
1106 { 11, 0x100bb3, 0x1301e6, 0x05a014, 0x001402 },
1107 { 12, 0x100bb3, 0x1301e6, 0x05a014, 0x001407 },
1108 { 13, 0x100bb3, 0x1301e7, 0x05a014, 0x001402 },
1109 { 14, 0x100bb3, 0x1301e8, 0x05a014, 0x001404 },
1110 { 36, 0x100bb3, 0x130266, 0x056014, 0x001408 },
1111 { 38, 0x100bb3, 0x130267, 0x056014, 0x001404 },
1112 { 40, 0x100bb2, 0x1301a0, 0x056014, 0x001400 },
1113 { 44, 0x100bb2, 0x1301a0, 0x056014, 0x001408 },
1114 { 46, 0x100bb2, 0x1301a1, 0x056014, 0x001402 },
1115 { 48, 0x100bb2, 0x1301a1, 0x056014, 0x001406 },
1116 { 52, 0x100bb2, 0x1301a2, 0x056014, 0x001404 },
1117 { 54, 0x100bb2, 0x1301a2, 0x056014, 0x001408 },
1118 { 56, 0x100bb2, 0x1301a3, 0x056014, 0x001402 },
1119 { 60, 0x100bb2, 0x1301a4, 0x056014, 0x001400 },
1120 { 62, 0x100bb2, 0x1301a4, 0x056014, 0x001404 },
1121 { 64, 0x100bb2, 0x1301a4, 0x056014, 0x001408 },
1122 { 100, 0x100bb2, 0x1301ac, 0x05e014, 0x001400 },
1123 { 102, 0x100bb2, 0x1701ac, 0x15e014, 0x001404 },
1124 { 104, 0x100bb2, 0x1701ac, 0x15e014, 0x001408 },
1125 { 108, 0x100bb3, 0x17028c, 0x15e014, 0x001404 },
1126 { 110, 0x100bb3, 0x13028d, 0x05e014, 0x001400 },
1127 { 112, 0x100bb3, 0x13028d, 0x05e014, 0x001406 },
1128 { 116, 0x100bb3, 0x13028e, 0x05e014, 0x001408 },
1129 { 118, 0x100bb3, 0x13028f, 0x05e014, 0x001404 },
1130 { 120, 0x100bb1, 0x1300e0, 0x05e014, 0x001400 },
1131 { 124, 0x100bb1, 0x1300e0, 0x05e014, 0x001404 },
1132 { 126, 0x100bb1, 0x1300e0, 0x05e014, 0x001406 },
1133 { 128, 0x100bb1, 0x1300e0, 0x05e014, 0x001408 },
1134 { 132, 0x100bb1, 0x1300e1, 0x05e014, 0x001402 },
1135 { 134, 0x100bb1, 0x1300e1, 0x05e014, 0x001404 },
1136 { 136, 0x100bb1, 0x1300e1, 0x05e014, 0x001406 },
1137 { 140, 0x100bb1, 0x1300e2, 0x05e014, 0x001400 },
1138 { 149, 0x100bb1, 0x1300e2, 0x05e014, 0x001409 },
1139 { 151, 0x100bb1, 0x1300e3, 0x05e014, 0x001401 },
1140 { 153, 0x100bb1, 0x1300e3, 0x05e014, 0x001403 },
1141 { 157, 0x100bb1, 0x1300e3, 0x05e014, 0x001407 },
1142 { 159, 0x100bb1, 0x1300e3, 0x05e014, 0x001409 },
1143 { 161, 0x100bb1, 0x1300e4, 0x05e014, 0x001401 },
1144 { 165, 0x100bb1, 0x1300e4, 0x05e014, 0x001405 },
1145 { 167, 0x100bb1, 0x1300f4, 0x05e014, 0x001407 },
1146 { 169, 0x100bb1, 0x1300f4, 0x05e014, 0x001409 },
1147 { 171, 0x100bb1, 0x1300f5, 0x05e014, 0x001401 },
1148 { 173, 0x100bb1, 0x1300f5, 0x05e014, 0x001403 },
1149 };
1150
1151 struct {
1152 u8int n;
1153 u8int r;
1154 u8int k;
1155 } rt3090_freqs[] = {
1156 { 0xf1, 2, 2 },
1157 { 0xf1, 2, 7 },
1158 { 0xf2, 2, 2 },
1159 { 0xf2, 2, 7 },
1160 { 0xf3, 2, 2 },
1161 { 0xf3, 2, 7 },
1162 { 0xf4, 2, 2 },
1163 { 0xf4, 2, 7 },
1164 { 0xf5, 2, 2 },
1165 { 0xf5, 2, 7 },
1166 { 0xf6, 2, 2 },
1167 { 0xf6, 2, 7 },
1168 { 0xf7, 2, 2 },
1169 { 0xf8, 2, 4 },
1170 { 0x56, 0, 4 },
1171 { 0x56, 0, 6 },
1172 { 0x56, 0, 8 },
1173 { 0x57, 0, 0 },
1174 { 0x57, 0, 2 },
1175 { 0x57, 0, 4 },
1176 { 0x57, 0, 8 },
1177 { 0x57, 0, 10 },
1178 { 0x58, 0, 0 },
1179 { 0x58, 0, 4 },
1180 { 0x58, 0, 6 },
1181 { 0x58, 0, 8 },
1182 { 0x5b, 0, 8 },
1183 { 0x5b, 0, 10 },
1184 { 0x5c, 0, 0 },
1185 { 0x5c, 0, 4 },
1186 { 0x5c, 0, 6 },
1187 { 0x5c, 0, 8 },
1188 { 0x5d, 0, 0 },
1189 { 0x5d, 0, 2 },
1190 { 0x5d, 0, 4 },
1191 { 0x5d, 0, 8 },
1192 { 0x5d, 0, 10 },
1193 { 0x5e, 0, 0 },
1194 { 0x5e, 0, 4 },
1195 { 0x5e, 0, 6 },
1196 { 0x5e, 0, 8 },
1197 { 0x5f, 0, 0 },
1198 { 0x5f, 0, 9 },
1199 { 0x5f, 0, 11 },
1200 { 0x60, 0, 1 },
1201 { 0x60, 0, 5 },
1202 { 0x60, 0, 7 },
1203 { 0x60, 0, 9 },
1204 { 0x61, 0, 1 },
1205 { 0x61, 0, 3 },
1206 { 0x61, 0, 5 },
1207 { 0x61, 0, 7 },
1208 { 0x61, 0, 9 }
1209 };
1210
1211 static const struct {
1212 u8int reg;
1213 u8int val;
1214 } rt3090_def_rf[] = {
1215 { 4, 0x40 },
1216 { 5, 0x03 },
1217 { 6, 0x02 },
1218 { 7, 0x70 },
1219 { 9, 0x0f },
1220 { 10, 0x41 },
1221 { 11, 0x21 },
1222 { 12, 0x7b },
1223 { 14, 0x90 },
1224 { 15, 0x58 },
1225 { 16, 0xb3 },
1226 { 17, 0x92 },
1227 { 18, 0x2c },
1228 { 19, 0x02 },
1229 { 20, 0xba },
1230 { 21, 0xdb },
1231 { 24, 0x16 },
1232 { 25, 0x01 },
1233 { 29, 0x1f }
1234 };
1235
1236 /* vendors */
1237 enum {
1238 Ralink = 0x1814,
1239 Awt = 0x1a3b,
1240 };
1241 /* products */
1242 enum {
1243 RalinkRT2890 = 0x0681,
1244 RalinkRT2790 = 0x0781,
1245 RalinkRT3090 = 0x3090,
1246 AwtRT2890 = 0x1059,
1247 };
1248
1249 #define csr32r(c, r) (*((c)->nic+((r)/4)))
1250 #define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v))
1251
1252 static int rbplant(Ctlr*, int);
1253 static void setchan(Ctlr*, uint);
1254 static void rt3090setchan(Ctlr*, uint);
1255 static void selchangroup(Ctlr*, int);
1256 static void setleds(Ctlr*, u16int);
1257
1258 static uint
get16(uchar * p)1259 get16(uchar *p){
1260 return *((u16int*)p);
1261 }
1262 static uint
get32(uchar * p)1263 get32(uchar *p){
1264 return *((u32int*)p);
1265 }
1266 static void
put32(uchar * p,uint v)1267 put32(uchar *p, uint v){
1268 *((u32int*)p) = v;
1269 }
1270 static void
put16(uchar * p,uint v)1271 put16(uchar *p, uint v){
1272 *((u16int*)p) = v;
1273 };
1274 static void
memwrite(Ctlr * ctlr,u32int off,uchar * data,uint size)1275 memwrite(Ctlr *ctlr, u32int off, uchar *data, uint size){
1276 memmove((uchar*)ctlr->nic + off, data, size);
1277 }
1278 static void
setregion(Ctlr * ctlr,u32int off,uint val,uint size)1279 setregion(Ctlr *ctlr, u32int off, uint val, uint size){
1280 memset((uchar*)ctlr->nic + off, val, size);
1281 }
1282
1283 static long
rt2860ctl(Ether * edev,void * buf,long n)1284 rt2860ctl(Ether *edev, void *buf, long n)
1285 {
1286 Ctlr *ctlr;
1287
1288 ctlr = edev->ctlr;
1289 if(ctlr->wifi)
1290 return wifictl(ctlr->wifi, buf, n);
1291 return 0;
1292 }
1293
1294 static long
rt2860ifstat(Ether * edev,void * buf,long n,ulong off)1295 rt2860ifstat(Ether *edev, void *buf, long n, ulong off)
1296 {
1297 Ctlr *ctlr;
1298
1299 ctlr = edev->ctlr;
1300 if(ctlr->wifi)
1301 return wifistat(ctlr->wifi, buf, n, off);
1302 return 0;
1303 }
1304
1305 static void
setoptions(Ether * edev)1306 setoptions(Ether *edev)
1307 {
1308 Ctlr *ctlr;
1309 int i;
1310
1311 ctlr = edev->ctlr;
1312 for(i = 0; i < edev->nopt; i++)
1313 wificfg(ctlr->wifi, edev->opt[i]);
1314 }
1315
1316 static void
rxon(Ether * edev,Wnode * bss)1317 rxon(Ether *edev, Wnode *bss)
1318 {
1319 u32int tmp;
1320 Ctlr *ctlr;
1321 int cap;
1322
1323 ctlr = edev->ctlr;
1324
1325 if(bss != nil){
1326 cap = bss->cap;
1327 ctlr->channel = bss->channel;
1328 memmove(ctlr->bssid, bss->bssid, Eaddrlen);
1329 ctlr->aid = bss->aid;
1330 if(ctlr->aid != 0){
1331 if(ctlr->wifi->debug)
1332 print("new assoc!");
1333 ctlr->bssnodeid = -1;
1334 }else
1335 ctlr->bcastnodeid = -1;
1336 }else{
1337 cap = 0;
1338 memmove(ctlr->bssid, edev->bcast, Eaddrlen);
1339 ctlr->aid = 0;
1340 ctlr->bcastnodeid = -1;
1341 ctlr->bssnodeid = -1;
1342 }
1343 if(ctlr->aid != 0)
1344 setleds(ctlr, LedRadio | LedLink2ghz);
1345 else
1346 setleds(ctlr, LedRadio);
1347
1348 if(ctlr->wifi->debug)
1349 print("#l%d: rxon: bssid %E, aid %x, channel %d wcid %d\n",
1350 edev->ctlrno, ctlr->bssid, ctlr->aid, ctlr->channel, ctlr->wcid);
1351
1352 /* Set channel */
1353 if(ctlr->mac_ver >= 0x3071)
1354 rt3090setchan(ctlr, ctlr->channel);
1355 else
1356 setchan(ctlr, ctlr->channel);
1357 selchangroup(ctlr, 0);
1358 microdelay(1000);
1359
1360 /* enable mrr(?) */
1361 #define CCK(mcs) (mcs)
1362 #define OFDM(mcs) (1 << 3 | (mcs))
1363 csr32w(ctlr, LgFbkCfg0,
1364 OFDM(6) << 28 | /* 54->48 */
1365 OFDM(5) << 24 | /* 48->36 */
1366 OFDM(4) << 20 | /* 36->24 */
1367 OFDM(3) << 16 | /* 24->18 */
1368 OFDM(2) << 12 | /* 18->12 */
1369 OFDM(1) << 8 | /* 12-> 9 */
1370 OFDM(0) << 4 | /* 9-> 6 */
1371 OFDM(0)); /* 6-> 6 */
1372
1373 csr32w(ctlr, LgFbkCfg1,
1374 CCK(2) << 12 | /* 11->5.5 */
1375 CCK(1) << 8 | /* 5.5-> 2 */
1376 CCK(0) << 4 | /* 2-> 1 */
1377 CCK(0)); /* 1-> 1 */
1378 #undef OFDM
1379 #undef CCK
1380 /* update slot */
1381 tmp = csr32r(ctlr, BkoffSlotCfg);
1382 tmp &= ~0xff;
1383 tmp |= (cap & (1<<10)) ? 9 : 20;
1384 csr32w(ctlr, BkoffSlotCfg, tmp);
1385
1386 /* set TX preamble */
1387 tmp = csr32r(ctlr, AutoRspCfg);
1388 tmp &= ~CckShortEn;
1389 if(cap & (1<<5)) tmp |= CckShortEn;
1390 csr32w(ctlr, AutoRspCfg, tmp);
1391
1392 /* set basic rates */
1393 csr32w(ctlr, LegacyBasicRate, 0x003); /* 11B */
1394
1395 /* Set BSSID */
1396 csr32w(ctlr, MacBssidDw0,
1397 ctlr->bssid[0] | ctlr->bssid[1] << 8 | ctlr->bssid[2] << 16 | ctlr->bssid[3] << 24);
1398 csr32w(ctlr, MacBssidDw1,
1399 ctlr->bssid[4] | ctlr->bssid[5] << 8);
1400
1401 if(ctlr->bcastnodeid == -1){
1402 ctlr->bcastnodeid = 0xff;
1403 memwrite(ctlr, WcidEntry(ctlr->bcastnodeid), edev->bcast, Eaddrlen);
1404 }
1405 if(ctlr->bssnodeid == -1 && bss != nil && ctlr->aid != 0){
1406 ctlr->bssnodeid = 0;
1407 memwrite(ctlr, WcidEntry(ctlr->bssnodeid), ctlr->bssid, Eaddrlen);
1408 }
1409 }
1410
1411 static void
rt2860promiscuous(void * arg,int on)1412 rt2860promiscuous(void *arg, int on)
1413 {
1414 Ether *edev;
1415 Ctlr *ctlr;
1416
1417 edev = arg;
1418 ctlr = edev->ctlr;
1419 if(ctlr->attached == 0)
1420 return;
1421 qlock(ctlr);
1422 ctlr->prom = on;
1423 rxon(edev, ctlr->wifi->bss);
1424 qunlock(ctlr);
1425 }
1426
1427 static void
rt2860multicast(void *,uchar *,int)1428 rt2860multicast(void *, uchar*, int)
1429 {
1430 }
1431
1432 static FWImage*
readfirmware(void)1433 readfirmware(void){
1434 static char name[] = "ral-rt2860";
1435 uchar dirbuf[sizeof(Dir)+100], *data;
1436 char buf[128];
1437 FWImage *fw;
1438 int n, r;
1439 Chan *c;
1440 Dir d;
1441
1442 if(!iseve())
1443 error(Eperm);
1444 if(!waserror()){
1445 snprint(buf, sizeof buf, "/boot/%s", name);
1446 c = namec(buf, Aopen, OREAD, 0);
1447 poperror();
1448 }else{
1449 snprint(buf, sizeof buf, "/lib/firmware/%s", name);
1450 c = namec(buf, Aopen, OREAD, 0);
1451 }
1452 if(waserror()){
1453 cclose(c);
1454 nexterror();
1455 }
1456 n = devtab[c->type]->stat(c, dirbuf, sizeof dirbuf);
1457 if(n <= 0)
1458 error("can't stat firmware");
1459 convM2D(dirbuf, n, &d, nil);
1460 fw = malloc(sizeof(*fw));
1461 fw->size = d.length;
1462 data = fw->data = smalloc(d.length);
1463 if(waserror()){
1464 free(fw);
1465 nexterror();
1466 }
1467 r = 0;
1468 while(r < d.length){
1469 n = devtab[c->type]->read(c, data+r, d.length-r, (vlong)r);
1470 if(n <= 0)
1471 break;
1472 r += n;
1473 }
1474 poperror();
1475 poperror();
1476 cclose(c);
1477 return fw;
1478 }
1479
1480 static char*
boot(Ctlr * ctlr)1481 boot(Ctlr *ctlr)
1482 {
1483 int ntries;
1484
1485 /* set "host program ram write selection" bit */
1486 csr32w(ctlr, SysCtrl, HstPmSel);
1487 /* write microcode image */
1488 memwrite(ctlr, FwBase, ctlr->fw->data, ctlr->fw->size);
1489 /* kick microcontroller unit */
1490 csr32w(ctlr, SysCtrl, 0);
1491 coherence();
1492 csr32w(ctlr, SysCtrl, McuReset);
1493
1494 csr32w(ctlr, H2mBbpagent, 0);
1495 csr32w(ctlr, H2mMailbox, 0);
1496
1497 /* wait until microcontroller is ready */
1498 coherence();
1499 for(ntries = 0; ntries < 1000; ntries++){
1500 if(csr32r(ctlr, SysCtrl) & McuReady)
1501 break;
1502 microdelay(1000);
1503 }
1504 if(ntries == 1000)
1505 return "timeout waiting for MCU to initialize";
1506 return 0;
1507 }
1508
1509 /*
1510 * Send a command to the 8051 microcontroller unit.
1511 */
1512 static int
mcucmd(Ctlr * ctlr,u8int cmd,u16int arg,int wait)1513 mcucmd(Ctlr *ctlr, u8int cmd, u16int arg, int wait)
1514 {
1515 int slot, ntries;
1516 u32int tmp;
1517 u8int cid;
1518
1519 SET(slot);
1520 for(ntries = 0; ntries < 100; ntries++){
1521 if(!(csr32r(ctlr, H2mMailbox) & H2mBusy))
1522 break;
1523 microdelay(2);
1524 }
1525 if(ntries == 100)
1526 return -1;
1527
1528 cid = wait ? cmd : TokenNoIntr;
1529 csr32w(ctlr, H2mMailbox, H2mBusy | cid << 16 | arg);
1530 coherence();
1531 csr32w(ctlr, HostCmd, cmd);
1532
1533 if(!wait)
1534 return 0;
1535 /* wait for the command to complete */
1536 for(ntries = 0; ntries < 200; ntries++){
1537 tmp = csr32r(ctlr, H2mMailboxCid);
1538 /* find the command slot */
1539 for(slot = 0; slot < 4; slot++, tmp >>= 8)
1540 if((tmp & 0xff) == cid)
1541 break;
1542 if(slot < 4)
1543 break;
1544 microdelay(100);
1545 }
1546 if(ntries == 200){
1547 /* clear command and status */
1548 csr32w(ctlr, H2mMailboxStatus, 0xffffffff);
1549 csr32w(ctlr, H2mMailboxCid, 0xffffffff);
1550 return -1;
1551 }
1552 /* get command status (1 means success) */
1553 tmp = csr32r(ctlr, H2mMailboxStatus);
1554 tmp = (tmp >> (slot * 8)) & 0xff;
1555 /* clear command and status */
1556 csr32w(ctlr, H2mMailboxStatus, 0xffffffff);
1557 csr32w(ctlr, H2mMailboxCid, 0xffffffff);
1558 return (tmp == 1) ? 0 : -1;
1559 }
1560
1561
1562 /*
1563 * Reading and writing from/to the BBP is different from RT2560 and RT2661.
1564 * We access the BBP through the 8051 microcontroller unit which means that
1565 * the microcode must be loaded first.
1566 */
1567 static void
bbpwrite(Ctlr * ctlr,u8int reg,u8int val)1568 bbpwrite(Ctlr *ctlr, u8int reg, u8int val)
1569 {
1570 int ntries;
1571
1572 for(ntries = 0; ntries < 100; ntries++){
1573 if(!(csr32r(ctlr, H2mBbpagent) & BbpCsrKick))
1574 break;
1575 microdelay(1);
1576 }
1577 if(ntries == 100){
1578 print("could not write to BBP through MCU\n");
1579 return;
1580 }
1581
1582 csr32w(ctlr, H2mBbpagent, BbpRwParallel |
1583 BbpCsrKick | reg << 8 | val);
1584 coherence();
1585
1586 mcucmd(ctlr, McuCmdBbp, 0, 0);
1587 microdelay(1000);
1588 }
1589
1590 static u8int
bbpread(Ctlr * ctlr,u8int reg)1591 bbpread(Ctlr *ctlr, u8int reg)
1592 {
1593 u32int val;
1594 int ntries;
1595
1596 for(ntries = 0; ntries < 100; ntries++){
1597 if(!(csr32r(ctlr, H2mBbpagent) & BbpCsrKick))
1598 break;
1599 microdelay(1);
1600 }
1601 if(ntries == 100){
1602 print("could not read from BBP through MCU");
1603 return 0;
1604 }
1605
1606 csr32w(ctlr, H2mBbpagent, BbpRwParallel |
1607 BbpCsrKick | BbpCsrRead | reg << 8);
1608 coherence();
1609
1610 mcucmd(ctlr, McuCmdBbp, 0, 0);
1611 microdelay(1000);
1612
1613 for(ntries = 0; ntries < 100; ntries++){
1614 val = csr32r(ctlr, H2mBbpagent);
1615 if(!(val & BbpCsrKick))
1616 return val & 0xff;
1617 microdelay(1);
1618 }
1619 print("could not read from BBP through MCU\n");
1620
1621 return 0;
1622 }
1623
1624 static char*
bbpinit(Ctlr * ctlr)1625 bbpinit(Ctlr *ctlr)
1626 {
1627 int i, ntries;
1628 char *err;
1629
1630 /* wait for BBP to wake up */
1631 for(ntries = 0; ntries < 20; ntries++){
1632 u8int bbp0 = bbpread(ctlr, 0);
1633 if(bbp0 != 0 && bbp0 != 0xff)
1634 break;
1635 }
1636 if(ntries == 20){
1637 err = "timeout waiting for BBP to wake up";
1638 return err;
1639 }
1640
1641 /* initialize BBP registers to default values */
1642 for(i = 0; i < nelem(rt2860_def_bbp); i++){
1643 bbpwrite(ctlr, rt2860_def_bbp[i].reg,
1644 rt2860_def_bbp[i].val);
1645 }
1646
1647 /* fix BBP84 for RT2860E */
1648 if(ctlr->mac_ver == 0x2860 && ctlr->mac_rev != 0x0101)
1649 bbpwrite(ctlr, 84, 0x19);
1650
1651 if(ctlr->mac_ver >= 0x3071){
1652 bbpwrite(ctlr, 79, 0x13);
1653 bbpwrite(ctlr, 80, 0x05);
1654 bbpwrite(ctlr, 81, 0x33);
1655 }else if(ctlr->mac_ver == 0x2860 && ctlr->mac_rev == 0x0100){
1656 bbpwrite(ctlr, 69, 0x16);
1657 bbpwrite(ctlr, 73, 0x12);
1658 }
1659
1660 return nil;
1661
1662 }
1663
1664 static void
setleds(Ctlr * ctlr,u16int which)1665 setleds(Ctlr *ctlr, u16int which)
1666 {
1667 mcucmd(ctlr, McuCmdLeds,
1668 which | (ctlr->leds & 0x7f), 0);
1669 }
1670
1671 static char*
txrxon(Ctlr * ctlr)1672 txrxon(Ctlr *ctlr)
1673 {
1674 u32int tmp;
1675 int ntries;
1676 char *err;
1677
1678 SET(tmp);
1679 /* enable Tx/Rx DMA engine */
1680 csr32w(ctlr, MacSysCtrl, MacTxEn);
1681 coherence();
1682 for(ntries = 0; ntries < 200; ntries++){
1683 tmp = csr32r(ctlr, WpdmaGloCfg);
1684 if((tmp & (TxDmaBusy | RxDmaBusy)) == 0)
1685 break;
1686 microdelay(1000);
1687 }
1688 if(ntries == 200){
1689 err = "timeout waiting for DMA engine";
1690 return err;
1691 }
1692
1693 microdelay(50);
1694
1695 tmp |= RxDmaEn | TxDmaEn |
1696 WpdmaBtSize64 << WpdmaBtSizeShift;
1697 csr32w(ctlr, WpdmaGloCfg, tmp);
1698
1699 /* set Rx filter */
1700 tmp = DropCrcErr | DropPhyErr;
1701 if(!ctlr->prom){
1702 tmp |= DropUcNome | DropDupl |
1703 DropCts | DropBa | DropAck |
1704 DropVerErr | DropCtrlRsv |
1705 DropCfack | DropCfend;
1706 tmp |= DropRts | DropPspoll;
1707 }
1708 csr32w(ctlr, RxFiltrCfg, tmp);
1709
1710 csr32w(ctlr, MacSysCtrl, MacRxEn | MacTxEn);
1711
1712 return 0;
1713 }
1714
1715 /*
1716 * Write to one of the 4 programmable 24-bit RF registers.
1717 */
1718 static void
rfwrite(Ctlr * ctlr,u8int reg,u32int val)1719 rfwrite(Ctlr *ctlr, u8int reg, u32int val)
1720 {
1721 u32int tmp;
1722 int ntries;
1723
1724 for(ntries = 0; ntries < 100; ntries++){
1725 if(!(csr32r(ctlr, RfCsrCfg0) & RfRegCtrl))
1726 break;
1727 microdelay(1);
1728 }
1729 if(ntries == 100){
1730 print("could not write to RF\n");
1731 return;
1732 }
1733
1734 /* RF registers are 24-bit on the RT2860 */
1735 tmp = RfRegCtrl | 24 << RfRegWidthShift |
1736 (val & 0x3fffff) << 2 | (reg & 3);
1737 csr32w(ctlr, RfCsrCfg0, tmp);
1738 }
1739
1740 u8int
rt3090rfread(Ctlr * ctlr,u8int reg)1741 rt3090rfread(Ctlr *ctlr, u8int reg)
1742 {
1743 u32int tmp;
1744 int ntries;
1745
1746 for(ntries = 0; ntries < 100; ntries++){
1747 if(!(csr32r(ctlr, Rt3070RfCsrCfg) & Rt3070RfKick))
1748 break;
1749 microdelay(1);
1750 }
1751 if(ntries == 100){
1752 print("could not read RF register\n");
1753 return 0xff;
1754 }
1755 tmp = Rt3070RfKick | reg << 8;
1756 csr32w(ctlr, Rt3070RfCsrCfg, tmp);
1757
1758 for(ntries = 0; ntries < 100; ntries++){
1759 tmp = csr32r(ctlr, Rt3070RfCsrCfg);
1760 if(!(tmp & Rt3070RfKick))
1761 break;
1762 microdelay(1);
1763 }
1764 if(ntries == 100){
1765 print("could not read RF register\n");
1766 return 0xff;
1767 }
1768 return tmp & 0xff;
1769 }
1770
1771 static void
rt3090rfwrite(Ctlr * ctlr,u8int reg,u8int val)1772 rt3090rfwrite(Ctlr *ctlr, u8int reg, u8int val)
1773 {
1774 u32int tmp;
1775 int ntries;
1776
1777 for(ntries = 0; ntries < 10; ntries++){
1778 if(!(csr32r(ctlr, Rt3070RfCsrCfg) & Rt3070RfKick))
1779 break;
1780 microdelay(10);
1781 }
1782 if(ntries == 10){
1783 print("could not write to RF\n");
1784 return;
1785 }
1786
1787 tmp = Rt3070RfWrite | Rt3070RfKick | reg << 8 | val;
1788 csr32w(ctlr, Rt3070RfCsrCfg, tmp);
1789 }
1790
1791 static void
selchangroup(Ctlr * ctlr,int group)1792 selchangroup(Ctlr *ctlr, int group)
1793 {
1794 u32int tmp;
1795 u8int agc;
1796
1797 bbpwrite(ctlr, 62, 0x37 - ctlr->lna[group]);
1798 bbpwrite(ctlr, 63, 0x37 - ctlr->lna[group]);
1799 bbpwrite(ctlr, 64, 0x37 - ctlr->lna[group]);
1800 bbpwrite(ctlr, 86, 0x00);
1801
1802 if(group == 0){
1803 if(ctlr->ext_2ghz_lna){
1804 bbpwrite(ctlr, 82, 0x62);
1805 bbpwrite(ctlr, 75, 0x46);
1806 }else{
1807 bbpwrite(ctlr, 82, 0x84);
1808 bbpwrite(ctlr, 75, 0x50);
1809 }
1810 }else{
1811 if(ctlr->ext_5ghz_lna){
1812 bbpwrite(ctlr, 82, 0xf2);
1813 bbpwrite(ctlr, 75, 0x46);
1814 }else{
1815 bbpwrite(ctlr, 82, 0xf2);
1816 bbpwrite(ctlr, 75, 0x50);
1817 }
1818 }
1819
1820 tmp = csr32r(ctlr, TxBandCfg);
1821 tmp &= ~(Tx5gBandSelN | Tx5gBandSelP);
1822 tmp |= (group == 0) ? Tx5gBandSelN : Tx5gBandSelP;
1823 csr32w(ctlr, TxBandCfg, tmp);
1824
1825 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */
1826 tmp = RftrEn | TrswEn | LnaPe0En;
1827 if(ctlr->nrxchains > 1)
1828 tmp |= LnaPe1En;
1829 if(ctlr->mac_ver == 0x3593 && ctlr->nrxchains > 2)
1830 tmp |= Rt3593LnaPe2En;
1831 if(group == 0){ /* 2GHz */
1832 tmp |= PaPeG0En;
1833 if(ctlr->ntxchains > 1)
1834 tmp |= PaPeG1En;
1835 if(ctlr->mac_ver == 0x3593 && ctlr->ntxchains > 2)
1836 tmp |= Rt3593PaPeG2En;
1837 }else{ /* 5GHz */
1838 tmp |= PaPeA0En;
1839 if(ctlr->ntxchains > 1)
1840 tmp |= PaPeA1En;
1841 if(ctlr->mac_ver == 0x3593 && ctlr->ntxchains > 2)
1842 tmp |= Rt3593PaPeA2En;
1843 }
1844 csr32w(ctlr, TxPinCfg, tmp);
1845
1846 if(ctlr->mac_ver == 0x3593){
1847 tmp = csr32r(ctlr, GpioCtrl);
1848 if(ctlr->flags & ConnPciE){
1849 tmp &= ~0x01010000;
1850 if(group == 0)
1851 tmp |= 0x00010000;
1852 }else{
1853 tmp &= ~0x00008080;
1854 if(group == 0)
1855 tmp |= 0x00000080;
1856 }
1857 tmp = (tmp & ~0x00001000) | 0x00000010;
1858 csr32w(ctlr, GpioCtrl, tmp);
1859 }
1860
1861 /* set initial AGC value */
1862 if(group == 0){ /* 2GHz band */
1863 if(ctlr->mac_ver >= 0x3071)
1864 agc = 0x1c + ctlr->lna[0] * 2;
1865 else
1866 agc = 0x2e + ctlr->lna[0];
1867 }else{ /* 5GHz band */
1868 agc = 0x32 + (ctlr->lna[group] * 5) / 3;
1869 }
1870 bbpwrite(ctlr, 66, agc);
1871
1872 microdelay(1000);
1873
1874 }
1875
1876 static void
setchan(Ctlr * ctlr,uint chan)1877 setchan(Ctlr *ctlr, uint chan)
1878 {
1879 const struct rfprog *rfprog = rt2860_rf2850;
1880 u32int r2, r3, r4;
1881 s8int txpow1, txpow2;
1882 uint i;
1883
1884 /* find the settings for this channel (we know it exists) */
1885 for(i = 0; rfprog[i].chan != chan; i++);
1886
1887 r2 = rfprog[i].r2;
1888 if(ctlr->ntxchains == 1)
1889 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */
1890 if(ctlr->nrxchains == 1)
1891 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */
1892 else if(ctlr->nrxchains == 2)
1893 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */
1894
1895 /* use Tx power values from EEPROM */
1896 txpow1 = ctlr->txpow1[i];
1897 txpow2 = ctlr->txpow2[i];
1898 if(chan > 14){
1899 if(txpow1 >= 0)
1900 txpow1 = txpow1 << 1 | 1;
1901 else
1902 txpow1 = (7 + txpow1) << 1;
1903 if(txpow2 >= 0)
1904 txpow2 = txpow2 << 1 | 1;
1905 else
1906 txpow2 = (7 + txpow2) << 1;
1907 }
1908 r3 = rfprog[i].r3 | txpow1 << 7;
1909 r4 = rfprog[i].r4 | ctlr->freq << 13 | txpow2 << 4;
1910
1911 rfwrite(ctlr, Rf1, rfprog[i].r1);
1912 rfwrite(ctlr, Rf2, r2);
1913 rfwrite(ctlr, Rf3, r3);
1914 rfwrite(ctlr, Rf4, r4);
1915
1916 microdelay(200);
1917
1918 rfwrite(ctlr, Rf1, rfprog[i].r1);
1919 rfwrite(ctlr, Rf2, r2);
1920 rfwrite(ctlr, Rf3, r3 | 1);
1921 rfwrite(ctlr, Rf4, r4);
1922
1923 microdelay(200);
1924
1925 rfwrite(ctlr, Rf1, rfprog[i].r1);
1926 rfwrite(ctlr, Rf2, r2);
1927 rfwrite(ctlr, Rf3, r3);
1928 rfwrite(ctlr, Rf4, r4);
1929 }
1930
1931 static void
rt3090setchan(Ctlr * ctlr,uint chan)1932 rt3090setchan(Ctlr *ctlr, uint chan)
1933 {
1934 s8int txpow1, txpow2;
1935 u8int rf;
1936 int i;
1937
1938 assert(chan >= 1 && chan <= 14); /* RT3090 is 2GHz only */
1939
1940 /* find the settings for this channel (we know it exists) */
1941 for(i = 0; rt2860_rf2850[i].chan != chan; i++);
1942
1943 /* use Tx power values from EEPROM */
1944 txpow1 = ctlr->txpow1[i];
1945 txpow2 = ctlr->txpow2[i];
1946
1947 rt3090rfwrite(ctlr, 2, rt3090_freqs[i].n);
1948 rf = rt3090rfread(ctlr, 3);
1949 rf = (rf & ~0x0f) | rt3090_freqs[i].k;
1950 rt3090rfwrite(ctlr, 3, rf);
1951 rf = rt3090rfread(ctlr, 6);
1952 rf = (rf & ~0x03) | rt3090_freqs[i].r;
1953 rt3090rfwrite(ctlr, 6, rf);
1954
1955 /* set Tx0 power */
1956 rf = rt3090rfread(ctlr, 12);
1957 rf = (rf & ~0x1f) | txpow1;
1958 rt3090rfwrite(ctlr, 12, rf);
1959
1960 /* set Tx1 power */
1961 rf = rt3090rfread(ctlr, 13);
1962 rf = (rf & ~0x1f) | txpow2;
1963 rt3090rfwrite(ctlr, 13, rf);
1964
1965 rf = rt3090rfread(ctlr, 1);
1966 rf &= ~0xfc;
1967 if(ctlr->ntxchains == 1)
1968 rf |= Rt3070Tx1Pd | Rt3070Tx2Pd;
1969 else if(ctlr->ntxchains == 2)
1970 rf |= Rt3070Tx2Pd;
1971 if(ctlr->nrxchains == 1)
1972 rf |= Rt3070Rx1Pd | Rt3070Rx2Pd;
1973 else if(ctlr->nrxchains == 2)
1974 rf |= Rt3070Rx2Pd;
1975 rt3090rfwrite(ctlr, 1, rf);
1976
1977 /* set RF offset */
1978 rf = rt3090rfread(ctlr, 23);
1979 rf = (rf & ~0x7f) | ctlr->freq;
1980 rt3090rfwrite(ctlr, 23, rf);
1981
1982 /* program RF filter */
1983 rf = rt3090rfread(ctlr, 24); /* Tx */
1984 rf = (rf & ~0x3f) | ctlr->rf24_20mhz;
1985 rt3090rfwrite(ctlr, 24, rf);
1986 rf = rt3090rfread(ctlr, 31); /* Rx */
1987 rf = (rf & ~0x3f) | ctlr->rf24_20mhz;
1988 rt3090rfwrite(ctlr, 31, rf);
1989
1990 /* enable RF tuning */
1991 rf = rt3090rfread(ctlr, 7);
1992 rt3090rfwrite(ctlr, 7, rf | Rt3070Tune);
1993 }
1994
1995 static int
rt3090filtercalib(Ctlr * ctlr,u8int init,u8int target,u8int * val)1996 rt3090filtercalib(Ctlr *ctlr, u8int init, u8int target, u8int *val)
1997 {
1998 u8int rf22, rf24;
1999 u8int bbp55_pb, bbp55_sb, delta;
2000 int ntries;
2001
2002 /* program filter */
2003 rf24 = rt3090rfread(ctlr, 24);
2004 rf24 = (rf24 & 0xc0) | init; /* initial filter value */
2005 rt3090rfwrite(ctlr, 24, rf24);
2006
2007 /* enable baseband loopback mode */
2008 rf22 = rt3090rfread(ctlr, 22);
2009 rt3090rfwrite(ctlr, 22, rf22 | Rt3070BbLoopback);
2010
2011 /* set power and frequency of passband test tone */
2012 bbpwrite(ctlr, 24, 0x00);
2013 for(ntries = 0, bbp55_pb = 0; ntries < 100; ntries++){
2014 /* transmit test tone */
2015 bbpwrite(ctlr, 25, 0x90);
2016 microdelay(1000);
2017 /* read received power */
2018 bbp55_pb = bbpread(ctlr, 55);
2019 if(bbp55_pb != 0)
2020 break;
2021 }
2022 if(ntries == 100)
2023 return -1;
2024
2025 /* set power and frequency of stopband test tone */
2026 bbpwrite(ctlr, 24, 0x06);
2027 for(ntries = 0; ntries < 100; ntries++){
2028 /* transmit test tone */
2029 bbpwrite(ctlr, 25, 0x90);
2030 microdelay(1000);
2031 /* read received power */
2032 bbp55_sb = bbpread(ctlr, 55);
2033
2034 delta = bbp55_pb - bbp55_sb;
2035 if(delta > target)
2036 break;
2037
2038 /* reprogram filter */
2039 rf24++;
2040 rt3090rfwrite(ctlr, 24, rf24);
2041 }
2042 if(ntries < 100){
2043 if(rf24 != init)
2044 rf24--; /* backtrack */
2045 *val = rf24;
2046 rt3090rfwrite(ctlr, 24, rf24);
2047 }
2048
2049 /* restore initial state */
2050 bbpwrite(ctlr, 24, 0x00);
2051
2052 /* disable baseband loopback mode */
2053 rf22 = rt3090rfread(ctlr, 22);
2054 rt3090rfwrite(ctlr, 22, rf22 & ~Rt3070BbLoopback);
2055
2056 return 0;
2057 }
2058
2059 static void
rt3090setrxantenna(Ctlr * ctlr,int aux)2060 rt3090setrxantenna(Ctlr *ctlr, int aux)
2061 {
2062 u32int tmp;
2063
2064 if(aux){
2065 tmp = csr32r(ctlr, PciEectrl);
2066 csr32w(ctlr, PciEectrl, tmp & ~EectrlC);
2067 tmp = csr32r(ctlr, GpioCtrl);
2068 csr32w(ctlr, GpioCtrl, (tmp & ~0x0808) | 0x08);
2069 }else{
2070 tmp = csr32r(ctlr, PciEectrl);
2071 csr32w(ctlr, PciEectrl, tmp | EectrlC);
2072 tmp = csr32r(ctlr, GpioCtrl);
2073 csr32w(ctlr, GpioCtrl, tmp & ~0x0808);
2074 }
2075 }
2076
2077 static int
rt3090rfinit(Ctlr * ctlr)2078 rt3090rfinit(Ctlr *ctlr)
2079 {
2080 u32int tmp;
2081 u8int rf, bbp;
2082 int i;
2083
2084 rf = rt3090rfread(ctlr, 30);
2085 /* toggle RF R30 bit 7 */
2086 rt3090rfwrite(ctlr, 30, rf | 0x80);
2087 microdelay(1000);
2088 rt3090rfwrite(ctlr, 30, rf & ~0x80);
2089
2090 tmp = csr32r(ctlr, Rt3070LdoCfg0);
2091 tmp &= ~0x1f000000;
2092 if(ctlr->patch_dac && ctlr->mac_rev < 0x0211)
2093 tmp |= 0x0d000000; /* 1.35V */
2094 else
2095 tmp |= 0x01000000; /* 1.2V */
2096 csr32w(ctlr, Rt3070LdoCfg0, tmp);
2097
2098 /* patch LNA_PE_G1 */
2099 tmp = csr32r(ctlr, Rt3070GpioSwitch);
2100 csr32w(ctlr, Rt3070GpioSwitch, tmp & ~0x20);
2101
2102 /* initialize RF registers to default value */
2103 for(i = 0; i < nelem(rt3090_def_rf); i++){
2104 rt3090rfwrite(ctlr, rt3090_def_rf[i].reg,
2105 rt3090_def_rf[i].val);
2106 }
2107
2108 /* select 20MHz bandwidth */
2109 rt3090rfwrite(ctlr, 31, 0x14);
2110
2111 rf = rt3090rfread(ctlr, 6);
2112 rt3090rfwrite(ctlr, 6, rf | 0x40);
2113
2114 if(ctlr->mac_ver != 0x3593){
2115 /* calibrate filter for 20MHz bandwidth */
2116 ctlr->rf24_20mhz = 0x1f; /* default value */
2117 rt3090filtercalib(ctlr, 0x07, 0x16, &ctlr->rf24_20mhz);
2118
2119 /* select 40MHz bandwidth */
2120 bbp = bbpread(ctlr, 4);
2121 bbpwrite(ctlr, 4, (bbp & ~0x08) | 0x10);
2122 rf = rt3090rfread(ctlr, 31);
2123 rt3090rfwrite(ctlr, 31, rf | 0x20);
2124
2125 /* calibrate filter for 40MHz bandwidth */
2126 ctlr->rf24_40mhz = 0x2f; /* default value */
2127 rt3090filtercalib(ctlr, 0x27, 0x19, &ctlr->rf24_40mhz);
2128
2129 /* go back to 20MHz bandwidth */
2130 bbp = bbpread(ctlr, 4);
2131 bbpwrite(ctlr, 4, bbp & ~0x18);
2132 }
2133 if(ctlr->mac_rev < 0x0211)
2134 rt3090rfwrite(ctlr, 27, 0x03);
2135
2136 tmp = csr32r(ctlr, Rt3070Opt14);
2137 csr32w(ctlr, Rt3070Opt14, tmp | 1);
2138
2139 if(ctlr->rf_rev == Rf3020)
2140 rt3090setrxantenna(ctlr, 0);
2141
2142 bbp = bbpread(ctlr, 138);
2143 if(ctlr->mac_ver == 0x3593){
2144 if(ctlr->ntxchains == 1)
2145 bbp |= 0x60; /* turn off DAC1 and DAC2 */
2146 else if(ctlr->ntxchains == 2)
2147 bbp |= 0x40; /* turn off DAC2 */
2148 if(ctlr->nrxchains == 1)
2149 bbp &= ~0x06; /* turn off ADC1 and ADC2 */
2150 else if(ctlr->nrxchains == 2)
2151 bbp &= ~0x04; /* turn off ADC2 */
2152 }else{
2153 if(ctlr->ntxchains == 1)
2154 bbp |= 0x20; /* turn off DAC1 */
2155 if(ctlr->nrxchains == 1)
2156 bbp &= ~0x02; /* turn off ADC1 */
2157 }
2158 bbpwrite(ctlr, 138, bbp);
2159
2160 rf = rt3090rfread(ctlr, 1);
2161 rf &= ~(Rt3070Rx0Pd | Rt3070Tx0Pd);
2162 rf |= Rt3070RfBlock | Rt3070Rx1Pd | Rt3070Tx1Pd;
2163 rt3090rfwrite(ctlr, 1, rf);
2164
2165 rf = rt3090rfread(ctlr, 15);
2166 rt3090rfwrite(ctlr, 15, rf & ~Rt3070TxLo2);
2167
2168 rf = rt3090rfread(ctlr, 17);
2169 rf &= ~Rt3070TxLo1;
2170 if(ctlr->mac_rev >= 0x0211 && !ctlr->ext_2ghz_lna)
2171 rf |= 0x20; /* fix for long range Rx issue */
2172 if(ctlr->txmixgain_2ghz >= 2)
2173 rf = (rf & ~0x7) | ctlr->txmixgain_2ghz;
2174 rt3090rfwrite(ctlr, 17, rf);
2175
2176 rf = rt3090rfread(ctlr, 20);
2177 rt3090rfwrite(ctlr, 20, rf & ~Rt3070RxLo1);
2178
2179 rf = rt3090rfread(ctlr, 21);
2180 rt3090rfwrite(ctlr, 21, rf & ~Rt3070RxLo2);
2181
2182 return 0;
2183 }
2184
2185 static void
rt3090rfwakeup(Ctlr * ctlr)2186 rt3090rfwakeup(Ctlr *ctlr)
2187 {
2188 u32int tmp;
2189 u8int rf;
2190
2191 if(ctlr->mac_ver == 0x3593){
2192 /* enable VCO */
2193 rf = rt3090rfread(ctlr, 1);
2194 rt3090rfwrite(ctlr, 1, rf | Rt3593Vco);
2195
2196 /* initiate VCO calibration */
2197 rf = rt3090rfread(ctlr, 3);
2198 rt3090rfwrite(ctlr, 3, rf | Rt3593Vcocal);
2199
2200 /* enable VCO bias current control */
2201 rf = rt3090rfread(ctlr, 6);
2202 rt3090rfwrite(ctlr, 6, rf | Rt3593VcoIc);
2203
2204 /* initiate res calibration */
2205 rf = rt3090rfread(ctlr, 2);
2206 rt3090rfwrite(ctlr, 2, rf | Rt3593Rescal);
2207
2208 /* set reference current control to 0.33 mA */
2209 rf = rt3090rfread(ctlr, 22);
2210 rf &= ~Rt3593CpIcMask;
2211 rf |= 1 << Rt3593CpIcShift;
2212 rt3090rfwrite(ctlr, 22, rf);
2213
2214 /* enable RX CTB */
2215 rf = rt3090rfread(ctlr, 46);
2216 rt3090rfwrite(ctlr, 46, rf | Rt3593RxCtb);
2217
2218 rf = rt3090rfread(ctlr, 20);
2219 rf &= ~(Rt3593LdoRfVcMask | Rt3593LdoPllVcMask);
2220 rt3090rfwrite(ctlr, 20, rf);
2221 }else{
2222 /* enable RF block */
2223 rf = rt3090rfread(ctlr, 1);
2224 rt3090rfwrite(ctlr, 1, rf | Rt3070RfBlock);
2225
2226 /* enable VCO bias current control */
2227 rf = rt3090rfread(ctlr, 7);
2228 rt3090rfwrite(ctlr, 7, rf | 0x30);
2229
2230 rf = rt3090rfread(ctlr, 9);
2231 rt3090rfwrite(ctlr, 9, rf | 0x0e);
2232
2233 /* enable RX CTB */
2234 rf = rt3090rfread(ctlr, 21);
2235 rt3090rfwrite(ctlr, 21, rf | Rt3070RxCtb);
2236
2237 /* fix Tx to Rx IQ glitch by raising RF voltage */
2238 rf = rt3090rfread(ctlr, 27);
2239 rf &= ~0x77;
2240 if(ctlr->mac_rev < 0x0211)
2241 rf |= 0x03;
2242 rt3090rfwrite(ctlr, 27, rf);
2243 }
2244 if(ctlr->patch_dac && ctlr->mac_rev < 0x0211){
2245 tmp = csr32r(ctlr, Rt3070LdoCfg0);
2246 tmp = (tmp & ~0x1f000000) | 0x0d000000;
2247 csr32w(ctlr, Rt3070LdoCfg0, tmp);
2248 }
2249 }
2250
2251 static void
rt3090rfsetup(Ctlr * ctlr)2252 rt3090rfsetup(Ctlr *ctlr)
2253 {
2254 u8int bbp;
2255 int i;
2256
2257 if(ctlr->mac_rev >= 0x0211){
2258 /* enable DC filter */
2259 bbpwrite(ctlr, 103, 0xc0);
2260
2261 /* improve power consumption */
2262 bbp = bbpread(ctlr, 31);
2263 bbpwrite(ctlr, 31, bbp & ~0x03);
2264 }
2265
2266 csr32w(ctlr, TxSwCfg1, 0);
2267 if(ctlr->mac_rev < 0x0211){
2268 csr32w(ctlr, TxSwCfg2,
2269 ctlr->patch_dac ? 0x2c : 0x0f);
2270 }else
2271 csr32w(ctlr, TxSwCfg2, 0);
2272
2273 /* initialize RF registers from ROM */
2274 for(i = 0; i < 10; i++){
2275 if(ctlr->rf[i].reg == 0 || ctlr->rf[i].reg == 0xff)
2276 continue;
2277 rt3090rfwrite(ctlr, ctlr->rf[i].reg, ctlr->rf[i].val);
2278 }
2279 }
2280
2281 static void
updateprot(Ctlr * ctlr)2282 updateprot(Ctlr *ctlr)
2283 {
2284 u32int tmp;
2285
2286 tmp = RtsthEn | ProtNavShort | TxopAllowAll;
2287 /* setup protection frame rate (MCS code) */
2288 tmp |= /*(ic->ic_curmode == IEEE80211_MODE_11A) ?
2289 rt2860_rates[RT2860_RIDX_OFDM6].mcs :*/
2290 rt2860_rates[RidxCck11].mcs;
2291
2292 /* CCK frames don't require protection */
2293 csr32w(ctlr, CckProtCfg, tmp);
2294 /* XXX
2295 if(ic->ic_flags & IEEE80211_F_USEPROT){
2296 if(ic->ic_protmode == IEEE80211_PROT_RTSCTS)
2297 tmp |= ProtCtrlRtsCts;
2298 else if(ic->ic_protmode == IEEE80211_PROT_CTSONLY)
2299 tmp |= ProtCtrlCts;
2300 }
2301 csr32w(ctlr, OfdmProtCfg, tmp); */
2302 }
2303
2304 static char*
rt2860start(Ether * edev)2305 rt2860start(Ether *edev)
2306 {
2307 u32int tmp;
2308 u8int bbp1, bbp3;
2309 int i, qid, ridx, ntries;
2310 char *err;
2311 Ctlr *ctlr;
2312
2313 ctlr = edev->ctlr;
2314 csr32w(ctlr, PwrPinCfg, IoRaPe);
2315
2316 /* disable DMA */
2317 tmp = csr32r(ctlr, WpdmaGloCfg);
2318 tmp &= 0xff0;
2319 csr32w(ctlr, WpdmaGloCfg, tmp);
2320
2321 /* PBF hardware reset */
2322 csr32w(ctlr, SysCtrl, 0xe1f);
2323 coherence();
2324 csr32w(ctlr, SysCtrl, 0xe00);
2325
2326 if((err = boot(ctlr)) != nil){
2327 /*XXX: rt2860stop(ifp, 1);*/
2328 return err;
2329 }
2330 /* set MAC address */
2331 csr32w(ctlr, MacAddrDw0,
2332 edev->ea[0] | edev->ea[1] << 8 | edev->ea[2] << 16 | edev->ea[3] << 24);
2333 csr32w(ctlr, MacAddrDw1,
2334 edev->ea[4] | edev->ea[5] << 8 | 0xff << 16);
2335
2336 /* init Tx power for all Tx rates (from EEPROM) */
2337 for(ridx = 0; ridx < 5; ridx++){
2338 if(ctlr->txpow20mhz[ridx] == 0xffffffff)
2339 continue;
2340 csr32w(ctlr, TxPwrCfg(ridx), ctlr->txpow20mhz[ridx]);
2341 }
2342
2343 for(ntries = 0; ntries < 100; ntries++){
2344 tmp = csr32r(ctlr, WpdmaGloCfg);
2345 if((tmp & (TxDmaBusy | RxDmaBusy)) == 0)
2346 break;
2347 microdelay(1000);
2348 }
2349 if(ntries == 100){
2350 err = "timeout waiting for DMA engine";
2351 /*rt2860_stop(ifp, 1);*/
2352 return err;
2353 }
2354 tmp &= 0xff0;
2355 csr32w(ctlr, WpdmaGloCfg, tmp);
2356
2357 /* reset Rx ring and all 6 Tx rings */
2358 csr32w(ctlr, WpdmaRstIdx, 0x1003f);
2359
2360 /* PBF hardware reset */
2361 csr32w(ctlr, SysCtrl, 0xe1f);
2362 coherence();
2363 csr32w(ctlr, SysCtrl, 0xe00);
2364
2365 csr32w(ctlr, PwrPinCfg, IoRaPe | IoRfPe);
2366
2367 csr32w(ctlr, MacSysCtrl, BbpHrst | MacSrst);
2368 coherence();
2369 csr32w(ctlr, MacSysCtrl, 0);
2370
2371 for(i = 0; i < nelem(rt2860_def_mac); i++)
2372 csr32w(ctlr, rt2860_def_mac[i].reg, rt2860_def_mac[i].val);
2373 if(ctlr->mac_ver >= 0x3071){
2374 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */
2375 csr32w(ctlr, TxSwCfg0,
2376 4 << DlyPapeEnShift);
2377 }
2378
2379 if(!(csr32r(ctlr, PciCfg) & PciCfgPci)){
2380 ctlr->flags |= ConnPciE;
2381 /* PCIe has different clock cycle count than PCI */
2382 tmp = csr32r(ctlr, UsCycCnt);
2383 tmp = (tmp & ~0xff) | 0x7d;
2384 csr32w(ctlr, UsCycCnt, tmp);
2385 }
2386
2387 /* wait while MAC is busy */
2388 for(ntries = 0; ntries < 100; ntries++){
2389 if(!(csr32r(ctlr, MacStatusReg) &
2390 (RxStatusBusy | TxStatusBusy)))
2391 break;
2392 microdelay(1000);
2393 }
2394 if(ntries == 100){
2395 err = "timeout waiting for MAC";
2396 /*rt2860_stop(ifp, 1);*/
2397 return err;
2398 }
2399
2400 /* clear Host to MCU mailbox */
2401 csr32w(ctlr, H2mBbpagent, 0);
2402 csr32w(ctlr, H2mMailbox, 0);
2403
2404 mcucmd(ctlr, McuCmdRfreset, 0, 0);
2405 microdelay(1000);
2406
2407 if((err = bbpinit(ctlr)) != nil){
2408 /*rt2860_stop(ifp, 1);*/
2409 return err;
2410 }
2411 /* clear RX WCID search table */
2412 setregion(ctlr, WcidEntry(0), 0, 512);
2413 /* clear pairwise key table */
2414 setregion(ctlr, Pkey(0), 0, 2048);
2415 /* clear IV/EIV table */
2416 setregion(ctlr, Iveiv(0), 0, 512);
2417 /* clear WCID attribute table */
2418 setregion(ctlr, WcidAttr(0), 0, 256);
2419 /* clear shared key table */
2420 setregion(ctlr, Skey(0, 0), 0, 8 * 32);
2421 /* clear shared key mode */
2422 setregion(ctlr, SkeyMode07, 0, 4);
2423
2424 /* init Tx rings (4 EDCAs + HCCA + Mgt) */
2425 for(qid = 0; qid < 6; qid++){
2426 csr32w(ctlr, TxBasePtr(qid), PCIWADDR(ctlr->tx[qid].d));
2427 csr32w(ctlr, TxMaxCnt(qid), Ntx);
2428 csr32w(ctlr, TxCtxIdx(qid), 0);
2429 }
2430
2431 /* init Rx ring */
2432 csr32w(ctlr, RxBasePtr, PCIWADDR(ctlr->rx.p));
2433 csr32w(ctlr, RxMaxCnt, Nrx);
2434 csr32w(ctlr, RxCalcIdx, Nrx - 1);
2435
2436 /* setup maximum buffer sizes */
2437 csr32w(ctlr, MaxLenCfg, 1 << 12 |
2438 (Rbufsize - Rxwisize - 2));
2439
2440 for(ntries = 0; ntries < 100; ntries++){
2441 tmp = csr32r(ctlr, WpdmaGloCfg);
2442 if((tmp & (TxDmaBusy | RxDmaBusy)) == 0)
2443 break;
2444 microdelay(1000);
2445 }
2446 if(ntries == 100){
2447 err = "timeout waiting for DMA engine";
2448 /*rt2860_stop(ifp, 1);*/
2449 return err;
2450 }
2451 tmp &= 0xff0;
2452 csr32w(ctlr, WpdmaGloCfg, tmp);
2453
2454 /* disable interrupts mitigation */
2455 csr32w(ctlr, DelayIntCfg, 0);
2456
2457 /* write vendor-specific BBP values (from EEPROM) */
2458 for(i = 0; i < 8; i++){
2459 if(ctlr->bbp[i].reg == 0 || ctlr->bbp[i].reg == 0xff)
2460 continue;
2461 bbpwrite(ctlr, ctlr->bbp[i].reg, ctlr->bbp[i].val);
2462 }
2463
2464 /* select Main antenna for 1T1R devices */
2465 if(ctlr->rf_rev == Rf2020 ||
2466 ctlr->rf_rev == Rf3020 ||
2467 ctlr->rf_rev == Rf3320)
2468 rt3090setrxantenna(ctlr, 0);
2469
2470 /* send LEDs operating mode to microcontroller */
2471 mcucmd(ctlr, McuCmdLed1, ctlr->led[0], 0);
2472 mcucmd(ctlr, McuCmdLed2, ctlr->led[1], 0);
2473 mcucmd(ctlr, McuCmdLed3, ctlr->led[2], 0);
2474
2475 if(ctlr->mac_ver >= 0x3071)
2476 rt3090rfinit(ctlr);
2477
2478 mcucmd(ctlr, McuCmdSleep, 0x02ff, 1);
2479 mcucmd(ctlr, McuCmdWakeup, 0, 1);
2480
2481 if(ctlr->mac_ver >= 0x3071)
2482 rt3090rfwakeup(ctlr);
2483
2484 /* disable non-existing Rx chains */
2485 bbp3 = bbpread(ctlr, 3);
2486 bbp3 &= ~(1 << 3 | 1 << 4);
2487 if(ctlr->nrxchains == 2)
2488 bbp3 |= 1 << 3;
2489 else if(ctlr->nrxchains == 3)
2490 bbp3 |= 1 << 4;
2491 bbpwrite(ctlr, 3, bbp3);
2492
2493 /* disable non-existing Tx chains */
2494 bbp1 = bbpread(ctlr, 1);
2495 if(ctlr->ntxchains == 1)
2496 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4));
2497 else if(ctlr->mac_ver == 0x3593 && ctlr->ntxchains == 2)
2498 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3;
2499 else if(ctlr->mac_ver == 0x3593 && ctlr->ntxchains == 3)
2500 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4;
2501 bbpwrite(ctlr, 1, bbp1);
2502
2503 if(ctlr->mac_ver >= 0x3071)
2504 rt3090rfsetup(ctlr);
2505
2506 /* select default channel */
2507 if(ctlr->mac_ver >= 0x3071)
2508 rt3090setchan(ctlr, 3);
2509 else
2510 setchan(ctlr, 3);
2511
2512 /* reset RF from MCU */
2513 mcucmd(ctlr, McuCmdRfreset, 0, 0);
2514
2515 /* set RTS threshold */
2516 tmp = csr32r(ctlr, TxRtsCfg);
2517 tmp &= ~0xffff00;
2518 tmp |= 1 /* ic->ic_rtsthreshold */ << 8;
2519 csr32w(ctlr, TxRtsCfg, tmp);
2520
2521 /* setup initial protection mode */
2522 updateprot(ctlr);
2523
2524 /* turn radio LED on */
2525 setleds(ctlr, LedRadio);
2526
2527 /* enable Tx/Rx DMA engine */
2528 if((err = txrxon(ctlr)) != 0){
2529 /*rt2860_stop(ifp, 1);*/
2530 return err;
2531 }
2532
2533 /* clear pending interrupts */
2534 csr32w(ctlr, IntStatus, 0xffffffff);
2535 /* enable interrupts */
2536 csr32w(ctlr, IntMask, 0x3fffc);
2537
2538 if(ctlr->flags & AdvancedPs)
2539 mcucmd(ctlr, McuCmdPslevel, ctlr->pslevel, 0);
2540 return nil;
2541 }
2542
2543 /*
2544 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word.
2545 * Used to adjust per-rate Tx power registers.
2546 */
2547 static u32int
b4inc(u32int b32,s8int delta)2548 b4inc(u32int b32, s8int delta)
2549 {
2550 s8int i, b4;
2551
2552 for(i = 0; i < 8; i++){
2553 b4 = b32 & 0xf;
2554 b4 += delta;
2555 if(b4 < 0)
2556 b4 = 0;
2557 else if(b4 > 0xf)
2558 b4 = 0xf;
2559 b32 = b32 >> 4 | b4 << 28;
2560 }
2561 return b32;
2562 }
2563
2564 static void
transmit(Wifi * wifi,Wnode * wn,Block * b)2565 transmit(Wifi *wifi, Wnode *wn, Block *b)
2566 {
2567 Ether *edev;
2568 Ctlr *ctlr;
2569 Wifipkt *w;
2570 u8int mcs, qid;
2571 int ridx, /*ctl_ridx,*/ hdrlen;
2572 uchar *p;
2573 int nodeid;
2574 Block *outb;
2575 TXQ *tx;
2576 Pool *pool;
2577
2578 edev = wifi->ether;
2579 ctlr = edev->ctlr;
2580
2581 qlock(ctlr);
2582 if(ctlr->attached == 0 || ctlr->broken){
2583 qunlock(ctlr);
2584 freeb(b);
2585 return;
2586 }
2587 if((wn->channel != ctlr->channel)
2588 || (!ctlr->prom && (wn->aid != ctlr->aid || memcmp(wn->bssid, ctlr->bssid, Eaddrlen) != 0)))
2589 rxon(edev, wn);
2590
2591 if(b == nil){
2592 /* association note has no data to transmit */
2593 qunlock(ctlr);
2594 return;
2595 }
2596
2597 pool = &ctlr->pool;
2598 qid = 0; /* for now */
2599 ridx = 0;
2600 tx = &ctlr->tx[qid];
2601
2602 nodeid = ctlr->bcastnodeid;
2603 w = (Wifipkt*)b->rp;
2604 hdrlen = wifihdrlen(w);
2605
2606 p = pool->p + pool->i * TxwiDmaSz;
2607 if((w->a1[0] & 1) == 0){
2608 *(p+4) = TxAck; /* xflags */
2609
2610 if(BLEN(b) > 512-4)
2611 *(p+1) = TxTxopBackoff; /* txop */
2612
2613 if((w->fc[0] & 0x0c) == 0x08 && ctlr->bssnodeid != -1){
2614 nodeid = ctlr->bssnodeid;
2615 ridx = 2; /* BUG: hardcode 11Mbit */
2616 }
2617 }
2618
2619 /*ctl_ridx = rt2860_rates[ridx].ctl_ridx;*/
2620 mcs = rt2860_rates[ridx].mcs;
2621
2622 /* setup TX Wireless Information */
2623 *p = 0; /* flags */
2624 *(p+2) = PhyCck | mcs; /* phy */
2625 /* let HW generate seq numbers */
2626 *(p+4) |= TxNseq; /* xflags */
2627 put16(p + 6, BLEN(b) | (((mcs+1) & 0xf) << TxPidShift) ); /* length */
2628
2629 /* put16((uchar*)&w->dur[0], rt2860_rates[ctl_ridx].lp_ack_dur); */
2630
2631 *(p+5) = nodeid; /* wcid */
2632
2633 /* copy packet header */
2634 memmove(p + Txwisize, b->rp, hdrlen);
2635
2636 /* setup tx descriptor */
2637 /* first segment is TXWI + 802.11 header */
2638 p = (uchar*)tx->d + Tdscsize * tx->i;
2639 put32(p, PCIWADDR(pool->p + pool->i * TxwiDmaSz)); /* sdp0 */
2640 put16(p + 6, Txwisize + hdrlen); /* sdl0 */
2641 *(p + 15) = TxQselEdca; /* flags */
2642
2643 /* allocate output buffer */
2644 b->rp += hdrlen;
2645 tx->b[tx->i] = outb = iallocb(BLEN(b) + 256);
2646 if(outb == nil){
2647 print("outb = nil\n");
2648 return;
2649 }
2650 outb->rp = (uchar*)ROUND((uintptr)outb->base, 256);
2651 memset(outb->rp, 0, BLEN(b));
2652 memmove(outb->rp, b->rp, BLEN(b));
2653 outb->wp = outb->rp + BLEN(b);
2654 freeb(b);
2655
2656 /* setup payload segments */
2657 put32(p + 8, PCIWADDR(outb->rp)); /* sdp1 */
2658 put16(p + 4, BLEN(outb) | TxLs1); /* sdl1 */
2659
2660 p = pool->p + pool->i * TxwiDmaSz;
2661 w = (Wifipkt*)(p + Txwisize);
2662 if(ctlr->wifi->debug){
2663 print("transmit: %E->%E,%E nodeid=%x txq[%d]=%d size=%ld\n", w->a2, w->a1, w->a3, nodeid, qid, ctlr->tx[qid].i, BLEN(outb));
2664 }
2665
2666 tx->i = (tx->i + 1) % Ntx;
2667 pool->i = (pool->i + 1) % Ntxpool;
2668
2669 coherence();
2670
2671 /* kick Tx */
2672 csr32w(ctlr, TxCtxIdx(qid), ctlr->tx[qid].i);
2673
2674 qunlock(ctlr);
2675 return;
2676 }
2677
2678 static void
rt2860attach(Ether * edev)2679 rt2860attach(Ether *edev)
2680 {
2681 FWImage *fw;
2682 Ctlr *ctlr;
2683 char *err;
2684
2685 ctlr = edev->ctlr;
2686 qlock(ctlr);
2687 if(waserror()){
2688 print("#l%d: %s\n", edev->ctlrno, up->errstr);
2689 /*if(ctlr->power)
2690 poweroff(ctlr);*/
2691 qunlock(ctlr);
2692 nexterror();
2693 }
2694 if(ctlr->attached == 0){
2695 if(ctlr->wifi == nil)
2696 ctlr->wifi = wifiattach(edev, transmit);
2697
2698 if(ctlr->fw == nil){
2699 fw = readfirmware();
2700 ctlr->fw = fw;
2701 }
2702 if((err = rt2860start(edev)) != nil){
2703 error(err);
2704 }
2705
2706 ctlr->bcastnodeid = -1;
2707 ctlr->bssnodeid = -1;
2708 ctlr->channel = 1;
2709 ctlr->aid = 0;
2710
2711 setoptions(edev);
2712
2713 ctlr->attached = 1;
2714 }
2715 qunlock(ctlr);
2716 poperror();
2717 }
2718
2719 static void
receive(Ctlr * ctlr)2720 receive(Ctlr *ctlr)
2721 {
2722 u32int hw;
2723 RXQ *rx;
2724 Block *b;
2725 uchar *d;
2726
2727 rx = &ctlr->rx;
2728 if(rx->b == nil){
2729 print("rx->b == nil!");
2730 return;
2731 }
2732 hw = csr32r(ctlr, FsDrxIdx) & 0xfff;
2733 while(rx->i != hw){
2734 u16int sdl0, len;
2735 u32int flags;
2736 uchar *p;
2737 Wifipkt *w;
2738 int hdrlen;
2739
2740 p = (uchar*)rx->p + Rdscsize * rx->i;
2741 sdl0 = get16(p + 4 /* sdp0 */ + 2 /* sdl1 */);
2742 if(!(sdl0 & RxDdone)){
2743 print("rxd ddone bit not set\n");
2744 break; /* should not happen */
2745 }
2746 flags = get32(p + 12);
2747 if(flags & (RxCrcerr | RxIcverr)){
2748 /* print("crc | icv err\n"); */
2749 goto skip;
2750 }
2751
2752 b = rx->b[rx->i];
2753 if(b == nil){
2754 print("no buf\n");
2755 goto skip;
2756 }
2757 d = b->rp;
2758 if(ctlr->wifi == nil)
2759 goto skip;
2760 if(rbplant(ctlr, rx->i) < 0){
2761 print("can't plant");
2762 goto skip;
2763 }
2764 ctlr->wcid = *b->rp;
2765 len = get16(b->rp + 2 /* wcid, keyidx */) & 0xfff;
2766 b->rp = d + Rxwisize;
2767 b->wp = b->rp + len;
2768 w = (Wifipkt*)b->rp;
2769 hdrlen = wifihdrlen(w);
2770 /* HW may insert 2 padding bytes after 802.11 header */
2771 if(flags & RxL2pad){
2772 memmove(b->rp + 2, b->rp, hdrlen);
2773 b->rp += 2;
2774 }
2775 w = (Wifipkt*)b->rp;
2776 if(ctlr->wifi->debug)
2777 print("receive: %E->%E,%E wcid 0x%x \n", w->a2, w->a1, w->a3, ctlr->wcid);
2778 wifiiq(ctlr->wifi, b);
2779 skip:
2780 put16(p + 4 /* sdp0 */ + 2 /* sdl1 */, sdl0 & ~RxDdone);
2781 rx->i = (rx->i + 1) % Nrx;
2782 }
2783 coherence();
2784 /* tell HW what we have processed */
2785 csr32w(ctlr, RxCalcIdx, (rx->i - 1) % Nrx);
2786 }
2787
2788 static void
stats(Ctlr * ctlr)2789 stats(Ctlr *ctlr)
2790 {
2791 u32int stat;
2792 u8int wcid;
2793
2794 while((stat = csr32r(ctlr, TxStatFifo)) & TxqVld){
2795 wcid = (stat >> TxqWcidShift) & 0xff;
2796 /* if no ACK was requested, no feedback is available */
2797 if(!(stat & TxqAckreq) || wcid == 0xff){
2798 continue;
2799 }
2800 }
2801 }
2802
2803 static void
rt2860tx(Ctlr * ctlr,u8int q)2804 rt2860tx(Ctlr *ctlr, u8int q)
2805 {
2806 u32int hw;
2807 TXQ *tx;
2808
2809 stats(ctlr);
2810 tx = &ctlr->tx[q];
2811 hw = csr32r(ctlr, TxDtxIdx(q));
2812 while(tx->n != hw){
2813 uchar *p = (uchar*)tx->d + Rdscsize * tx->n;
2814 u16int sdl0;
2815
2816 if(tx->b[tx->n]){
2817 freeb(tx->b[tx->n]);
2818 tx->b[tx->n] = nil;
2819 }
2820 sdl0 = get16(p + 4 /* sdp0 */ + 2 /* sdl1 */);
2821 if(!(sdl0 & TxDdone)){
2822 print("txd ddone bit not set\n");
2823 break; /* should not happen */
2824 }
2825 memset((uchar*)ctlr->pool.p + TxwiDmaSz * tx->n, 0, TxwiDmaSz);
2826 memset((uchar*)tx->d + Tdscsize * tx->n, 0, Tdscsize);
2827 // put16(p + 4 /* sdp0 */ + 2 /* sdl1 */, sdl0 & ~TxDdone);
2828 tx->n = (tx->n + 1) % Ntx;
2829 }
2830 coherence();
2831 }
2832
2833 static void
rt2860interrupt(Ureg *,void * arg)2834 rt2860interrupt(Ureg*, void *arg)
2835 {
2836 u32int r;
2837 Ether *edev;
2838 Ctlr *ctlr;
2839 int debug;
2840
2841 edev = arg;
2842 ctlr = edev->ctlr;
2843 ilock(ctlr);
2844
2845 debug = ctlr->wifi->debug;
2846
2847 r = csr32r(ctlr, IntStatus);
2848 if(r == 0xffffffff){
2849 iunlock(ctlr);
2850 return;
2851 }
2852 if(r == 0){
2853 iunlock(ctlr);
2854 return;
2855 }
2856
2857 /* acknowledge interrupts */
2858 csr32w(ctlr, IntStatus, r);
2859
2860 if(r & TxRxCoherent){
2861 u32int tmp;
2862 /* DMA finds data coherent event when checking the DDONE bit */
2863 if(debug)
2864 print("txrx coherent intr\n");
2865
2866 /* restart DMA engine */
2867 tmp = csr32r(ctlr, WpdmaGloCfg);
2868 tmp &= ~(TxWbDdone | RxDmaEn | TxDmaEn);
2869 csr32w(ctlr, WpdmaGloCfg, tmp);
2870
2871 txrxon(ctlr);
2872 }
2873 if(r & MacInt2)
2874 stats(ctlr);
2875
2876 if(r & TxDoneInt5)
2877 rt2860tx(ctlr, 5);
2878
2879 if(r & RxDoneInt)
2880 receive(ctlr);
2881
2882 if(r & TxDoneInt4)
2883 rt2860tx(ctlr, 4);
2884
2885 if(r & TxDoneInt3)
2886 rt2860tx(ctlr, 3);
2887
2888 if(r & TxDoneInt2)
2889 rt2860tx(ctlr, 2);
2890
2891 if(r & TxDoneInt1)
2892 rt2860tx(ctlr, 1);
2893
2894 if(r & TxDoneInt0)
2895 rt2860tx(ctlr, 0);
2896
2897 iunlock(ctlr);
2898 }
2899
2900 static void
eepromctl(Ctlr * ctlr,u32int val)2901 eepromctl(Ctlr *ctlr, u32int val)
2902 {
2903 csr32w(ctlr, PciEectrl, val);
2904 coherence();
2905 microdelay(EepromDelay);
2906 }
2907
2908 /*
2909 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46,
2910 * 93C66 or 93C86).
2911 */
2912 static u16int
eeread2(Ctlr * ctlr,u16int addr)2913 eeread2(Ctlr *ctlr, u16int addr)
2914 {
2915 u32int tmp;
2916 u16int val;
2917 int n;
2918
2919 /* clock C once before the first command */
2920 eepromctl(ctlr, 0);
2921
2922 eepromctl(ctlr, EectrlS);
2923 eepromctl(ctlr, EectrlS | EectrlC);
2924 eepromctl(ctlr, EectrlS);
2925
2926 /* write start bit (1) */
2927 eepromctl(ctlr, EectrlS | EectrlD);
2928 eepromctl(ctlr, EectrlS | EectrlD | EectrlC);
2929
2930 /* write READ opcode (10) */
2931 eepromctl(ctlr, EectrlS | EectrlD);
2932 eepromctl(ctlr, EectrlS | EectrlD | EectrlC);
2933 eepromctl(ctlr, EectrlS);
2934 eepromctl(ctlr, EectrlS | EectrlC);
2935
2936 /* write address (A5-A0 or A7-A0) */
2937 n = ((csr32r(ctlr, PciEectrl) & 0x30) == 0) ? 5 : 7;
2938 for(; n >= 0; n--){
2939 eepromctl(ctlr, EectrlS |
2940 (((addr >> n) & 1) << EectrlShiftD));
2941 eepromctl(ctlr, EectrlS |
2942 (((addr >> n) & 1) << EectrlShiftD) | EectrlC);
2943 }
2944
2945 eepromctl(ctlr, EectrlS);
2946
2947 /* read data Q15-Q0 */
2948 val = 0;
2949 for(n = 15; n >= 0; n--){
2950 eepromctl(ctlr, EectrlS | EectrlC);
2951 tmp = csr32r(ctlr, PciEectrl);
2952 val |= ((tmp & EectrlQ) >> EectrlShiftQ) << n;
2953 eepromctl(ctlr, EectrlS);
2954 }
2955
2956 eepromctl(ctlr, 0);
2957
2958 /* clear Chip Select and clock C */
2959 eepromctl(ctlr, EectrlS);
2960 eepromctl(ctlr, 0);
2961 eepromctl(ctlr, EectrlC);
2962
2963 return val;
2964 }
2965
2966 /* Read 16-bit from eFUSE ROM (>=RT3071 only.) */
2967 static u16int
efuseread2(Ctlr * ctlr,u16int addr)2968 efuseread2(Ctlr *ctlr, u16int addr)
2969 {
2970 u32int tmp;
2971 u16int reg;
2972 int ntries;
2973
2974 addr *= 2;
2975 /*-
2976 * Read one 16-byte block into registers EFUSE_DATA[0-3]:
2977 * DATA0: F E D C
2978 * DATA1: B A 9 8
2979 * DATA2: 7 6 5 4
2980 * DATA3: 3 2 1 0
2981 */
2982 tmp = csr32r(ctlr, Rt3070EfuseCtrl);
2983 tmp &= ~(Rt3070EfsromModeMask | Rt3070EfsromAinMask);
2984 tmp |= (addr & ~0xf) << Rt3070EfsromAinShift | Rt3070EfsromKick;
2985 csr32w(ctlr, Rt3070EfuseCtrl, tmp);
2986 for(ntries = 0; ntries < 500; ntries++){
2987 tmp = csr32r(ctlr, Rt3070EfuseCtrl);
2988 if(!(tmp & Rt3070EfsromKick))
2989 break;
2990 microdelay(2);
2991 }
2992 if(ntries == 500)
2993 return 0xffff;
2994
2995 if((tmp & Rt3070EfuseAoutMask) == Rt3070EfuseAoutMask)
2996 return 0xffff; /* address not found */
2997
2998 /* determine to which 32-bit register our 16-bit word belongs */
2999 reg = Rt3070EfuseData3 - (addr & 0xc);
3000 tmp = csr32r(ctlr, reg);
3001
3002 return (addr & 2) ? tmp >> 16 : tmp & 0xffff;
3003 }
3004
3005 static char*
eepromread(Ether * edev)3006 eepromread(Ether *edev)
3007 {
3008 s8int delta_2ghz, delta_5ghz;
3009 u32int tmp;
3010 u16int val;
3011 int ridx, ant, i;
3012 u16int (*rom_read)(Ctlr*, u16int);
3013 Ctlr *ctlr;
3014
3015 enum { DefLna = 10 };
3016
3017 ctlr = edev->ctlr;
3018 /* check whether the ROM is eFUSE ROM or EEPROM */
3019 rom_read = eeread2;
3020 if(ctlr->mac_ver >= 0x3071){
3021 tmp = csr32r(ctlr, Rt3070EfuseCtrl);
3022 if(tmp & Rt3070SelEfuse)
3023 rom_read = efuseread2;
3024 }
3025
3026 /* read MAC address */
3027 val = rom_read(ctlr, EepromMac01);
3028 edev->ea[0] = val & 0xff;
3029 edev->ea[1] = val >> 8;
3030 val = rom_read(ctlr, EepromMac23);
3031 edev->ea[2] = val & 0xff;
3032 edev->ea[3] = val >> 8;
3033 val = rom_read(ctlr, EepromMac45);
3034 edev->ea[4] = val & 0xff;
3035 edev->ea[5] = val >> 8;
3036
3037 /* read vendor BBP settings */
3038 for(i = 0; i < 8; i++){
3039 val = rom_read(ctlr, EepromBbpBase + i);
3040 ctlr->bbp[i].val = val & 0xff;
3041 ctlr->bbp[i].reg = val >> 8;
3042 }
3043
3044 if(ctlr->mac_ver >= 0x3071){
3045 /* read vendor RF settings */
3046 for(i = 0; i < 10; i++){
3047 val = rom_read(ctlr, Rt3071EepromRfBase + i);
3048 ctlr->rf[i].val = val & 0xff;
3049 ctlr->rf[i].reg = val >> 8;
3050 }
3051 }
3052
3053 /* read RF frequency offset from EEPROM */
3054 val = rom_read(ctlr, EepromFreqLeds);
3055 ctlr->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0;
3056 if((val >> 8) != 0xff){
3057 /* read LEDs operating mode */
3058 ctlr->leds = val >> 8;
3059 ctlr->led[0] = rom_read(ctlr, EepromLed1);
3060 ctlr->led[1] = rom_read(ctlr, EepromLed2);
3061 ctlr->led[2] = rom_read(ctlr, EepromLed3);
3062 }else{
3063 /* broken EEPROM, use default settings */
3064 ctlr->leds = 0x01;
3065 ctlr->led[0] = 0x5555;
3066 ctlr->led[1] = 0x2221;
3067 ctlr->led[2] = 0xa9f8;
3068 }
3069 /* read RF information */
3070 val = rom_read(ctlr, EepromAntenna);
3071 if(val == 0xffff){
3072 if(ctlr->mac_ver == 0x3593){
3073 /* default to RF3053 3T3R */
3074 ctlr->rf_rev = Rf3053;
3075 ctlr->ntxchains = 3;
3076 ctlr->nrxchains = 3;
3077 }else if(ctlr->mac_ver >= 0x3071){
3078 /* default to RF3020 1T1R */
3079 ctlr->rf_rev = Rf3020;
3080 ctlr->ntxchains = 1;
3081 ctlr->nrxchains = 1;
3082 }else{
3083 /* default to RF2820 1T2R */
3084 ctlr->rf_rev = Rf2820;
3085 ctlr->ntxchains = 1;
3086 ctlr->nrxchains = 2;
3087 }
3088 }else{
3089 ctlr->rf_rev = (val >> 8) & 0xf;
3090 ctlr->ntxchains = (val >> 4) & 0xf;
3091 ctlr->nrxchains = val & 0xf;
3092 }
3093
3094 /* check if RF supports automatic Tx access gain control */
3095 val = rom_read(ctlr, EepromConfig);
3096 /* check if driver should patch the DAC issue */
3097 if((val >> 8) != 0xff)
3098 ctlr->patch_dac = (val >> 15) & 1;
3099 if((val & 0xff) != 0xff){
3100 ctlr->ext_5ghz_lna = (val >> 3) & 1;
3101 ctlr->ext_2ghz_lna = (val >> 2) & 1;
3102 /* check if RF supports automatic Tx access gain control */
3103 ctlr->calib_2ghz = ctlr->calib_5ghz = 0; /* XXX (val >> 1) & 1 */;
3104 /* check if we have a hardware radio switch */
3105 ctlr->rfswitch = val & 1;
3106 }
3107 if(ctlr->flags & AdvancedPs){
3108 /* read PCIe power save level */
3109 val = rom_read(ctlr, EepromPciePslevel);
3110 if((val & 0xff) != 0xff){
3111 ctlr->pslevel = val & 0x3;
3112 val = rom_read(ctlr, EepromRev);
3113 if((val & 0xff80) != 0x9280)
3114 ctlr->pslevel = MIN(ctlr->pslevel, 1);
3115 }
3116 }
3117
3118 /* read power settings for 2GHz channels */
3119 for(i = 0; i < 14; i += 2){
3120 val = rom_read(ctlr,
3121 EepromPwr2ghzBase1 + i / 2);
3122 ctlr->txpow1[i + 0] = (s8int)(val & 0xff);
3123 ctlr->txpow1[i + 1] = (s8int)(val >> 8);
3124
3125 val = rom_read(ctlr,
3126 EepromPwr2ghzBase2 + i / 2);
3127 ctlr->txpow2[i + 0] = (s8int)(val & 0xff);
3128 ctlr->txpow2[i + 1] = (s8int)(val >> 8);
3129 }
3130 /* fix broken Tx power entries */
3131
3132 for(i = 0; i < 14; i++){
3133 if(ctlr->txpow1[i] < 0 || ctlr->txpow1[i] > 31)
3134 ctlr->txpow1[i] = 5;
3135 if(ctlr->txpow2[i] < 0 || ctlr->txpow2[i] > 31)
3136 ctlr->txpow2[i] = 5;
3137 }
3138 /* read power settings for 5GHz channels */
3139 for(i = 0; i < 40; i += 2){
3140 val = rom_read(ctlr,
3141 EepromPwr5ghzBase1 + i / 2);
3142 ctlr->txpow1[i + 14] = (s8int)(val & 0xff);
3143 ctlr->txpow1[i + 15] = (s8int)(val >> 8);
3144
3145 val = rom_read(ctlr,
3146 EepromPwr5ghzBase2 + i / 2);
3147 ctlr->txpow2[i + 14] = (s8int)(val & 0xff);
3148 ctlr->txpow2[i + 15] = (s8int)(val >> 8);
3149 }
3150
3151 /* fix broken Tx power entries */
3152 for(i = 0; i < 40; i++){
3153 if(ctlr->txpow1[14 + i] < -7 || ctlr->txpow1[14 + i] > 15)
3154 ctlr->txpow1[14 + i] = 5;
3155 if(ctlr->txpow2[14 + i] < -7 || ctlr->txpow2[14 + i] > 15)
3156 ctlr->txpow2[14 + i] = 5;
3157 }
3158
3159 /* read Tx power compensation for each Tx rate */
3160 val = rom_read(ctlr, EepromDeltapwr);
3161 delta_2ghz = delta_5ghz = 0;
3162 if((val & 0xff) != 0xff && (val & 0x80)){
3163 delta_2ghz = val & 0xf;
3164 if(!(val & 0x40)) /* negative number */
3165 delta_2ghz = -delta_2ghz;
3166 }
3167 val >>= 8;
3168 if((val & 0xff) != 0xff && (val & 0x80)){
3169 delta_5ghz = val & 0xf;
3170 if(!(val & 0x40)) /* negative number */
3171 delta_5ghz = -delta_5ghz;
3172 }
3173
3174 for(ridx = 0; ridx < 5; ridx++){
3175 u32int reg;
3176
3177 val = rom_read(ctlr, EepromRpwr + ridx * 2);
3178 reg = val;
3179 val = rom_read(ctlr, EepromRpwr + ridx * 2 + 1);
3180 reg |= (u32int)val << 16;
3181
3182 ctlr->txpow20mhz[ridx] = reg;
3183 ctlr->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz);
3184 ctlr->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz);
3185 }
3186
3187 /* read factory-calibrated samples for temperature compensation */
3188 val = rom_read(ctlr, EepromTssi12ghz);
3189 ctlr->tssi_2ghz[0] = val & 0xff; /* [-4] */
3190 ctlr->tssi_2ghz[1] = val >> 8; /* [-3] */
3191 val = rom_read(ctlr, EepromTssi22ghz);
3192 ctlr->tssi_2ghz[2] = val & 0xff; /* [-2] */
3193 ctlr->tssi_2ghz[3] = val >> 8; /* [-1] */
3194 val = rom_read(ctlr, EepromTssi32ghz);
3195 ctlr->tssi_2ghz[4] = val & 0xff; /* [+0] */
3196 ctlr->tssi_2ghz[5] = val >> 8; /* [+1] */
3197 val = rom_read(ctlr, EepromTssi42ghz);
3198 ctlr->tssi_2ghz[6] = val & 0xff; /* [+2] */
3199 ctlr->tssi_2ghz[7] = val >> 8; /* [+3] */
3200 val = rom_read(ctlr, EepromTssi52ghz);
3201 ctlr->tssi_2ghz[8] = val & 0xff; /* [+4] */
3202 ctlr->step_2ghz = val >> 8;
3203 /* check that ref value is correct, otherwise disable calibration */
3204 if(ctlr->tssi_2ghz[4] == 0xff)
3205 ctlr->calib_2ghz = 0;
3206
3207 val = rom_read(ctlr, EepromTssi15ghz);
3208 ctlr->tssi_5ghz[0] = val & 0xff; /* [-4] */
3209 ctlr->tssi_5ghz[1] = val >> 8; /* [-3] */
3210 val = rom_read(ctlr, EepromTssi25ghz);
3211 ctlr->tssi_5ghz[2] = val & 0xff; /* [-2] */
3212 ctlr->tssi_5ghz[3] = val >> 8; /* [-1] */
3213 val = rom_read(ctlr, EepromTssi35ghz);
3214 ctlr->tssi_5ghz[4] = val & 0xff; /* [+0] */
3215 ctlr->tssi_5ghz[5] = val >> 8; /* [+1] */
3216 val = rom_read(ctlr, EepromTssi45ghz);
3217 ctlr->tssi_5ghz[6] = val & 0xff; /* [+2] */
3218 ctlr->tssi_5ghz[7] = val >> 8; /* [+3] */
3219 val = rom_read(ctlr, EepromTssi55ghz);
3220 ctlr->tssi_5ghz[8] = val & 0xff; /* [+4] */
3221 ctlr->step_5ghz = val >> 8;
3222 /* check that ref value is correct, otherwise disable calibration */
3223 if(ctlr->tssi_5ghz[4] == 0xff)
3224 ctlr->calib_5ghz = 0;
3225
3226 /* read RSSI offsets and LNA gains from EEPROM */
3227 val = rom_read(ctlr, EepromRssi12ghz);
3228 ctlr->rssi_2ghz[0] = val & 0xff; /* Ant A */
3229 ctlr->rssi_2ghz[1] = val >> 8; /* Ant B */
3230 val = rom_read(ctlr, EepromRssi22ghz);
3231 if(ctlr->mac_ver >= 0x3071){
3232 /*
3233 * On RT3090 chips (limited to 2 Rx chains), this ROM
3234 * field contains the Tx mixer gain for the 2GHz band.
3235 */
3236 if((val & 0xff) != 0xff)
3237 ctlr->txmixgain_2ghz = val & 0x7;
3238 }else
3239 ctlr->rssi_2ghz[2] = val & 0xff; /* Ant C */
3240 ctlr->lna[2] = val >> 8; /* channel group 2 */
3241
3242 val = rom_read(ctlr, EepromRssi15ghz);
3243 ctlr->rssi_5ghz[0] = val & 0xff; /* Ant A */
3244 ctlr->rssi_5ghz[1] = val >> 8; /* Ant B */
3245 val = rom_read(ctlr, EepromRssi25ghz);
3246 ctlr->rssi_5ghz[2] = val & 0xff; /* Ant C */
3247 ctlr->lna[3] = val >> 8; /* channel group 3 */
3248
3249 val = rom_read(ctlr, EepromLna);
3250 if(ctlr->mac_ver >= 0x3071)
3251 ctlr->lna[0] = DefLna;
3252 else /* channel group 0 */
3253 ctlr->lna[0] = val & 0xff;
3254 ctlr->lna[1] = val >> 8; /* channel group 1 */
3255
3256 /* fix broken 5GHz LNA entries */
3257 if(ctlr->lna[2] == 0 || ctlr->lna[2] == 0xff){
3258 ctlr->lna[2] = ctlr->lna[1];
3259 }
3260 if(ctlr->lna[3] == 0 || ctlr->lna[3] == 0xff){
3261 ctlr->lna[3] = ctlr->lna[1];
3262 }
3263
3264 /* fix broken RSSI offset entries */
3265 for(ant = 0; ant < 3; ant++){
3266 if(ctlr->rssi_2ghz[ant] < -10 || ctlr->rssi_2ghz[ant] > 10){
3267 ctlr->rssi_2ghz[ant] = 0;
3268 }
3269 if(ctlr->rssi_5ghz[ant] < -10 || ctlr->rssi_5ghz[ant] > 10){
3270 ctlr->rssi_5ghz[ant] = 0;
3271 }
3272 }
3273
3274 return 0;
3275 }
3276
3277 static const char *
getrfname(u8int rev)3278 getrfname(u8int rev)
3279 {
3280 if((rev == 0) || (rev >= nelem(rfnames)))
3281 return "unknown";
3282 if(rfnames[rev][0] == '\0')
3283 return "unknown";
3284 return rfnames[rev];
3285 }
3286
3287 static int
rbplant(Ctlr * ctlr,int i)3288 rbplant(Ctlr *ctlr, int i)
3289 {
3290 Block *b;
3291 uchar *p;
3292
3293 b = iallocb(Rbufsize + 256);
3294 if(b == nil)
3295 return -1;
3296 b->rp = b->wp = (uchar*)ROUND((uintptr)b->base, 256);
3297 memset(b->rp, 0, Rbufsize);
3298 ctlr->rx.b[i] = b;
3299 p = (uchar*)&ctlr->rx.p[i * 4]; /* sdp0 */
3300 memset(p, 0, Rdscsize);
3301 put32(p, PCIWADDR(b->rp));
3302 p = (uchar*)&ctlr->rx.p[i * 4 + 1]; /* sdl0 */
3303 p += 2; /* sdl1 */
3304 put16(p, Rbufsize);;
3305
3306 return 0;
3307 }
3308
3309 static char*
allocrx(Ctlr * ctlr,RXQ * rx)3310 allocrx(Ctlr *ctlr, RXQ *rx)
3311 {
3312 int i;
3313
3314 if(rx->b == nil)
3315 rx->b = malloc(sizeof(Block*) * Nrx);
3316 if(rx->p == nil) /* Rx descriptors */
3317 rx->p = mallocalign(Nrx * Rdscsize, 16, 0, 0);
3318 if(rx->b == nil || rx->p == nil)
3319 return "no memory for rx ring";
3320 memset(rx->p, 0, Nrx * Rdscsize);
3321 for(i=0; i<Nrx; i++){
3322 if(rx->b[i] != nil){
3323 freeb(rx->b[i]);
3324 rx->b[i] = nil;
3325 }
3326 if(rbplant(ctlr, i) < 0)
3327 return "no memory for rx descriptors";
3328 }
3329 rx->i = 0;
3330 return nil;
3331 }
3332
3333 static void
freerx(Ctlr *,RXQ * rx)3334 freerx(Ctlr *, RXQ *rx)
3335 {
3336 int i;
3337
3338 for(i = 0; i < Nrx; i++){
3339 if(rx->b[i] != nil){
3340 freeb(rx->b[i]);
3341 rx->b[i] = nil;
3342 }
3343 }
3344 free(rx->b);
3345 free(rx->p);
3346 rx->p = nil;
3347 rx->b = nil;
3348 rx->i = 0;
3349 }
3350
3351 static char*
alloctx(Ctlr *,TXQ * tx)3352 alloctx(Ctlr *, TXQ *tx)
3353 {
3354 if(tx->b == nil)
3355 tx->b = malloc(sizeof(Block*) * Ntx);
3356 if(tx->d == nil) /* Tx descriptors */
3357 tx->d = mallocalign(Ntx * Tdscsize, 16, 0, 0);
3358 if(tx->b == nil || tx->d == nil)
3359 return "no memory for tx ring";
3360 memset(tx->d, 0, Ntx * Tdscsize);
3361 memset(tx->b, 0, Ntx * sizeof(Block*));
3362 tx->i = 0;
3363 return nil;
3364 }
3365
3366 static void
freetx(Ctlr *,TXQ * tx)3367 freetx(Ctlr *, TXQ *tx)
3368 {
3369 free(tx->b);
3370 free(tx->d);
3371 tx->d = nil;
3372 tx->i = 0;
3373 }
3374
3375 static char*
alloctxpool(Ctlr * ctlr)3376 alloctxpool(Ctlr *ctlr)
3377 {
3378 Pool *pool;
3379
3380 pool = &ctlr->pool;
3381 if(pool->p == nil)
3382 pool->p = mallocalign(Ntxpool * TxwiDmaSz, 4096, 0, 0);
3383 if(pool->p == nil)
3384 return "no memory for pool";
3385 memset(pool->p, 0, Ntxpool * TxwiDmaSz);
3386 pool->i = 0;
3387 return 0;
3388 }
3389
3390 static char*
initring(Ctlr * ctlr)3391 initring(Ctlr *ctlr)
3392 {
3393 int qid;
3394 char *err;
3395
3396 /*
3397 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings.
3398 */
3399 for(qid = 0; qid < 6; qid++){
3400 if((err = alloctx(ctlr, &ctlr->tx[qid])) != nil)
3401 goto fail1;
3402 }
3403 if((err = allocrx(ctlr, &ctlr->rx)) != nil)
3404 goto fail1;
3405
3406 if((err = alloctxpool(ctlr)) != nil)
3407 goto fail2;
3408 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */
3409
3410 ctlr->mgtqid = (ctlr->mac_ver == 0x2860 && ctlr->mac_rev == 0x0100) ?
3411 3 : 5;
3412
3413 return nil;
3414 fail2: freerx(ctlr, &ctlr->rx);
3415 return err;
3416 fail1: while(--qid >= 0)
3417 freetx(ctlr, &ctlr->tx[qid]);
3418 return err;
3419 }
3420
3421 static int
rt2860init(Ether * edev)3422 rt2860init(Ether *edev)
3423 {
3424 Ctlr *ctlr;
3425 int ntries;
3426 char *err;
3427 u32int tmp;
3428
3429 SET(tmp);
3430 ctlr = edev->ctlr;
3431 /* wait for NIC to initialize */
3432 for(ntries = 0; ntries < 100; ntries++){
3433 tmp = csr32r(ctlr, AsicVerId);
3434 if(tmp != 0 && tmp != 0xffffffff)
3435 break;
3436 microdelay(10);
3437 }
3438 if(ntries == 100){
3439 print("timeout waiting for NIC to initialize");
3440 return -1;
3441 }
3442 ctlr->mac_ver = tmp >> 16;
3443 ctlr->mac_rev = tmp & 0xffff;
3444
3445 if(ctlr->mac_ver != 0x2860){
3446 switch(ctlr->pdev->did){
3447 default:
3448 break;
3449 case RalinkRT2890:
3450 case RalinkRT2790:
3451 case RalinkRT3090:
3452 case AwtRT2890:
3453 ctlr->flags = AdvancedPs;
3454 break;
3455 }
3456 }
3457 /* retrieve RF rev. no and various other things from EEPROM */
3458 eepromread(edev);
3459
3460 print("MAC/BBP RT%X (rev 0x%04X), RF %s (MIMO %dT%dR)\n",
3461 ctlr->mac_ver, ctlr->mac_rev,
3462 getrfname(ctlr->rf_rev), ctlr->ntxchains, ctlr->nrxchains);
3463 if((err = initring(ctlr)) != nil){
3464 print("error: %s", err);
3465 return -1;
3466 }
3467
3468 return 0;
3469 }
3470
3471 static Ctlr *rt2860head, *rt2860tail;
3472
3473 static void
rt2860pci(void)3474 rt2860pci(void)
3475 {
3476 Pcidev *pdev;
3477
3478 pdev = nil;
3479 while(pdev = pcimatch(pdev, 0, 0)){
3480 Ctlr *ctlr;
3481 void *mem;
3482
3483 if(pdev->ccrb != 2 || pdev->ccru != 0x80)
3484 continue;
3485 if(pdev->vid != 0x1814) /* Ralink */
3486 continue;
3487
3488 switch(pdev->did){
3489 default:
3490 continue;
3491 case RalinkRT2790:
3492 case RalinkRT3090:
3493 break;
3494 }
3495
3496 pcisetbme(pdev);
3497 pcisetpms(pdev, 0);
3498
3499 ctlr = malloc(sizeof(Ctlr));
3500 if(ctlr == nil){
3501 print("rt2860: unable to alloc Ctlr\n");
3502 continue;
3503 }
3504 ctlr->port = pdev->mem[0].bar & ~0x0F;
3505 mem = vmap(pdev->mem[0].bar & ~0x0F, pdev->mem[0].size);
3506 if(mem == nil){
3507 print("rt2860: can't map %8.8luX\n", pdev->mem[0].bar);
3508 free(ctlr);
3509 continue;
3510 }
3511 ctlr->nic = mem;
3512 ctlr->pdev = pdev;
3513
3514 if(rt2860head != nil)
3515 rt2860tail->link = ctlr;
3516 else
3517 rt2860head = ctlr;
3518 rt2860tail = ctlr;
3519 }
3520 }
3521
3522 static int
rt2860pnp(Ether * edev)3523 rt2860pnp(Ether* edev)
3524 {
3525 Ctlr *ctlr;
3526
3527 if(rt2860head == nil)
3528 rt2860pci();
3529 again:
3530 for(ctlr = rt2860head; ctlr != nil; ctlr = ctlr->link){
3531 if(ctlr->active)
3532 continue;
3533 if(edev->port == 0 || edev->port == ctlr->port){
3534 ctlr->active = 1;
3535 break;
3536 }
3537 }
3538
3539 if(ctlr == nil)
3540 return -1;
3541
3542 edev->ctlr = ctlr;
3543 edev->port = ctlr->port;
3544 edev->irq = ctlr->pdev->intl;
3545 edev->tbdf = ctlr->pdev->tbdf;
3546 edev->arg = edev;
3547 edev->interrupt = rt2860interrupt;
3548 edev->attach = rt2860attach;
3549 edev->ifstat = rt2860ifstat;
3550 edev->ctl = rt2860ctl;
3551 edev->promiscuous = rt2860promiscuous;
3552 edev->multicast = rt2860multicast;
3553 edev->mbps = 10;
3554
3555 if(rt2860init(edev) < 0){
3556 edev->ctlr = nil;
3557 goto again;
3558 }
3559 return 0;
3560 }
3561
3562 void
etherrt2860link(void)3563 etherrt2860link(void)
3564 {
3565 addethercard("rt2860", rt2860pnp);
3566 }
3567