1 /*
2 * Intel Gigabit Ethernet PCI-Express Controllers.
3 * 8256[367], 8257[1-79], 21[078]
4 * Pretty basic, does not use many of the chip smarts.
5 * The interrupt mitigation tuning for each chip variant
6 * is probably different. The reset/initialisation
7 * sequence needs straightened out. Doubt the PHY code
8 * for the 82575eb is right.
9 *
10 * on the assumption that allowing jumbo packets makes the controller
11 * much slower (as is true of the 82579), never allow jumbos.
12 */
13 #include "u.h"
14 #include "../port/lib.h"
15 #include "mem.h"
16 #include "dat.h"
17 #include "fns.h"
18 #include "io.h"
19 #include "../port/error.h"
20 #include "../port/netif.h"
21 #include "etherif.h"
22
23 #define now() TK2MS(MACHP(0)->ticks)
24
25 /*
26 * these are in the order they appear in the manual, not numeric order.
27 * It was too hard to find them in the book. Ref 21489, rev 2.6
28 */
29
30 enum {
31 /* General */
32 Ctrl = 0x0000, /* Device Control */
33 Status = 0x0008, /* Device Status */
34 Eec = 0x0010, /* EEPROM/Flash Control/Data */
35 Fextnvm6 = 0x0010, /* Future Extended NVM 6 */
36 Eerd = 0x0014, /* EEPROM Read */
37 Ctrlext = 0x0018, /* Extended Device Control */
38 Fla = 0x001c, /* Flash Access */
39 Mdic = 0x0020, /* MDI Control */
40 Seresctl = 0x0024, /* Serdes ana */
41 Fcal = 0x0028, /* Flow Control Address Low */
42 Fcah = 0x002C, /* Flow Control Address High */
43 Fct = 0x0030, /* Flow Control Type */
44 Kumctrlsta = 0x0034, /* MAC-PHY Interface */
45 Vet = 0x0038, /* VLAN EtherType */
46 Fcttv = 0x0170, /* Flow Control Transmit Timer Value */
47 Txcw = 0x0178, /* Transmit Configuration Word */
48 Rxcw = 0x0180, /* Receive Configuration Word */
49 Ledctl = 0x0E00, /* LED control */
50 Pba = 0x1000, /* Packet Buffer Allocation */
51 Pbs = 0x1008, /* Packet Buffer Size */
52
53 /* Interrupt */
54 Icr = 0x00C0, /* Interrupt Cause Read */
55 Itr = 0x00c4, /* Interrupt Throttling Rate */
56 Ics = 0x00C8, /* Interrupt Cause Set */
57 Ims = 0x00D0, /* Interrupt Mask Set/Read */
58 Imc = 0x00D8, /* Interrupt mask Clear */
59 Iam = 0x00E0, /* Interrupt acknowledge Auto Mask */
60
61 /* Receive */
62 Rctl = 0x0100, /* Control */
63 Ert = 0x2008, /* Early Receive Threshold (573[EVL], 579 only) */
64 Fcrtl = 0x2160, /* Flow Control RX Threshold Low */
65 Fcrth = 0x2168, /* Flow Control Rx Threshold High */
66 Psrctl = 0x2170, /* Packet Split Receive Control */
67 Rdbal = 0x2800, /* Rdesc Base Address Low Queue 0 */
68 Rdbah = 0x2804, /* Rdesc Base Address High Queue 0 */
69 Rdlen = 0x2808, /* Descriptor Length Queue 0 */
70 Rdh = 0x2810, /* Descriptor Head Queue 0 */
71 Rdt = 0x2818, /* Descriptor Tail Queue 0 */
72 Rdtr = 0x2820, /* Descriptor Timer Ring */
73 Rxdctl = 0x2828, /* Descriptor Control */
74 Radv = 0x282C, /* Interrupt Absolute Delay Timer */
75 Rdbal1 = 0x2900, /* Rdesc Base Address Low Queue 1 */
76 Rdbah1 = 0x2804, /* Rdesc Base Address High Queue 1 */
77 Rdlen1 = 0x2908, /* Descriptor Length Queue 1 */
78 Rdh1 = 0x2910, /* Descriptor Head Queue 1 */
79 Rdt1 = 0x2918, /* Descriptor Tail Queue 1 */
80 Rxdctl1 = 0x2928, /* Descriptor Control Queue 1 */
81 Rsrpd = 0x2c00, /* Small Packet Detect */
82 Raid = 0x2c08, /* ACK interrupt delay */
83 Cpuvec = 0x2c10, /* CPU Vector */
84 Rxcsum = 0x5000, /* Checksum Control */
85 Rfctl = 0x5008, /* Filter Control */
86 Mta = 0x5200, /* Multicast Table Array */
87 Ral = 0x5400, /* Receive Address Low */
88 Rah = 0x5404, /* Receive Address High */
89 Vfta = 0x5600, /* VLAN Filter Table Array */
90 Mrqc = 0x5818, /* Multiple Receive Queues Command */
91 Rssim = 0x5864, /* RSS Interrupt Mask */
92 Rssir = 0x5868, /* RSS Interrupt Request */
93 Reta = 0x5c00, /* Redirection Table */
94 Rssrk = 0x5c80, /* RSS Random Key */
95
96 /* Transmit */
97 Tctl = 0x0400, /* Transmit Control */
98 Tipg = 0x0410, /* Transmit IPG */
99 Tkabgtxd = 0x3004, /* glci afe band gap transmit ref data, or something */
100 Tdbal = 0x3800, /* Tdesc Base Address Low */
101 Tdbah = 0x3804, /* Tdesc Base Address High */
102 Tdlen = 0x3808, /* Descriptor Length */
103 Tdh = 0x3810, /* Descriptor Head */
104 Tdt = 0x3818, /* Descriptor Tail */
105 Tidv = 0x3820, /* Interrupt Delay Value */
106 Txdctl = 0x3828, /* Descriptor Control */
107 Tadv = 0x382C, /* Interrupt Absolute Delay Timer */
108 Tarc0 = 0x3840, /* Arbitration Counter Queue 0 */
109 Tdbal1 = 0x3900, /* Descriptor Base Low Queue 1 */
110 Tdbah1 = 0x3904, /* Descriptor Base High Queue 1 */
111 Tdlen1 = 0x3908, /* Descriptor Length Queue 1 */
112 Tdh1 = 0x3910, /* Descriptor Head Queue 1 */
113 Tdt1 = 0x3918, /* Descriptor Tail Queue 1 */
114 Txdctl1 = 0x3928, /* Descriptor Control 1 */
115 Tarc1 = 0x3940, /* Arbitration Counter Queue 1 */
116
117 /* Statistics */
118 Statistics = 0x4000, /* Start of Statistics Area */
119 Gorcl = 0x88/4, /* Good Octets Received Count */
120 Gotcl = 0x90/4, /* Good Octets Transmitted Count */
121 Torl = 0xC0/4, /* Total Octets Received */
122 Totl = 0xC8/4, /* Total Octets Transmitted */
123 Nstatistics = 0x124/4,
124 };
125
126 enum { /* Ctrl */
127 GIOmd = 1<<2, /* BIO master disable */
128 Lrst = 1<<3, /* link reset */
129 Slu = 1<<6, /* Set Link Up */
130 SspeedMASK = 3<<8, /* Speed Selection */
131 SspeedSHIFT = 8,
132 Sspeed10 = 0x00000000, /* 10Mb/s */
133 Sspeed100 = 0x00000100, /* 100Mb/s */
134 Sspeed1000 = 0x00000200, /* 1000Mb/s */
135 Frcspd = 1<<11, /* Force Speed */
136 Frcdplx = 1<<12, /* Force Duplex */
137 SwdpinsloMASK = 0x003C0000, /* Software Defined Pins - lo nibble */
138 SwdpinsloSHIFT = 18,
139 SwdpioloMASK = 0x03C00000, /* Software Defined Pins - I or O */
140 SwdpioloSHIFT = 22,
141 Devrst = 1<<26, /* Device Reset */
142 Rfce = 1<<27, /* Receive Flow Control Enable */
143 Tfce = 1<<28, /* Transmit Flow Control Enable */
144 Vme = 1<<30, /* VLAN Mode Enable */
145 Phyrst = 1<<31, /* Phy Reset */
146 };
147
148 enum { /* Status */
149 Lu = 1<<1, /* Link Up */
150 Lanid = 3<<2, /* mask for Lan ID. */
151 Txoff = 1<<4, /* Transmission Paused */
152 Tbimode = 1<<5, /* TBI Mode Indication */
153 Phyra = 1<<10, /* PHY Reset Asserted */
154 GIOme = 1<<19, /* GIO Master Enable Status */
155 };
156
157 enum { /* Eerd */
158 EEstart = 1<<0, /* Start Read */
159 EEdone = 1<<1, /* Read done */
160 };
161
162 enum { /* Ctrlext */
163 Asdchk = 1<<12, /* ASD Check */
164 Eerst = 1<<13, /* EEPROM Reset */
165 Spdbyps = 1<<15, /* Speed Select Bypass */
166 };
167
168 enum { /* EEPROM content offsets */
169 Ea = 0x00, /* Ethernet Address */
170 Cf = 0x03, /* Compatibility Field */
171 Icw1 = 0x0A, /* Initialization Control Word 1 */
172 Sid = 0x0B, /* Subsystem ID */
173 Svid = 0x0C, /* Subsystem Vendor ID */
174 Did = 0x0D, /* Device ID */
175 Vid = 0x0E, /* Vendor ID */
176 Icw2 = 0x0F, /* Initialization Control Word 2 */
177 };
178
179 enum { /* Mdic */
180 MDIdMASK = 0x0000FFFF, /* Data */
181 MDIdSHIFT = 0,
182 MDIrMASK = 0x001F0000, /* PHY Register Address */
183 MDIrSHIFT = 16,
184 MDIpMASK = 0x03E00000, /* PHY Address */
185 MDIpSHIFT = 21,
186 MDIwop = 0x04000000, /* Write Operation */
187 MDIrop = 0x08000000, /* Read Operation */
188 MDIready = 0x10000000, /* End of Transaction */
189 MDIie = 0x20000000, /* Interrupt Enable */
190 MDIe = 0x40000000, /* Error */
191 };
192
193 enum { /* phy interface registers */
194 Phyctl = 0, /* phy ctl */
195 Physsr = 17, /* phy secondary status */
196 Phyier = 18, /* 82573 phy interrupt enable */
197 Phyisr = 19, /* 82563 phy interrupt status */
198 Phylhr = 19, /* 8257[12] link health */
199 Phyier218 = 24, /* 218 (phy79?) phy interrupt enable */
200 Phyisr218 = 25, /* 218 (phy79?) phy interrupt status */
201 Phystat = 26, /* 82580 (phy79?) phy status */
202 Phypage = 31, /* page number */
203
204 Rtlink = 1<<10, /* realtime link status */
205 Phyan = 1<<11, /* phy has auto-negotiated */
206
207 /* Phyctl bits */
208 Ran = 1<<9, /* restart auto-negotiation */
209 Ean = 1<<12, /* enable auto-negotiation */
210
211 /* 82573 Phyier interrupt enable bits */
212 Lscie = 1<<10, /* link status changed */
213 Ancie = 1<<11, /* auto-negotiation complete */
214 Spdie = 1<<14, /* speed changed */
215 Panie = 1<<15, /* phy auto-negotiation error */
216
217 /* Phylhr/Phyisr bits */
218 Anf = 1<<6, /* lhr: auto-negotiation fault */
219 Ane = 1<<15, /* isr: auto-negotiation error */
220
221 /* 82580 Phystat bits */
222 Ans = 3<<14, /* 82580 autoneg. status */
223 Link = 1<<6, /* 82580 link */
224
225 /* 218 Phystat bits */
226 Anfs = 3<<13, /* fault status */
227 Ans218 = 1<<12, /* autoneg complete */
228
229 /* 218 Phyier218 interrupt enable bits */
230 Spdie218 = 1<<1, /* speed changed */
231 Lscie218 = 1<<2, /* link status changed */
232 Ancie218 = 1<<8, /* auto-negotiation changed */
233 };
234
235 enum { /* Icr, Ics, Ims, Imc */
236 Txdw = 0x00000001, /* Transmit Descriptor Written Back */
237 Txqe = 0x00000002, /* Transmit Queue Empty */
238 Lsc = 0x00000004, /* Link Status Change */
239 Rxseq = 0x00000008, /* Receive Sequence Error */
240 Rxdmt0 = 0x00000010, /* Rdesc Minimum Threshold Reached */
241 Rxo = 0x00000040, /* Receiver Overrun */
242 Rxt0 = 0x00000080, /* Receiver Timer Interrupt */
243 Mdac = 0x00000200, /* MDIO Access Completed */
244 Rxcfg = 0x00000400, /* Receiving /C/ ordered sets */
245 Gpi0 = 0x00000800, /* General Purpose Interrupts */
246 Gpi1 = 0x00001000,
247 Gpi2 = 0x00002000,
248 Gpi3 = 0x00004000,
249 Ack = 0x00020000, /* Receive ACK frame */
250 };
251
252 enum { /* Txcw */
253 TxcwFd = 0x00000020, /* Full Duplex */
254 TxcwHd = 0x00000040, /* Half Duplex */
255 TxcwPauseMASK = 0x00000180, /* Pause */
256 TxcwPauseSHIFT = 7,
257 TxcwPs = 1<<TxcwPauseSHIFT, /* Pause Supported */
258 TxcwAs = 2<<TxcwPauseSHIFT, /* Asymmetric FC desired */
259 TxcwRfiMASK = 0x00003000, /* Remote Fault Indication */
260 TxcwRfiSHIFT = 12,
261 TxcwNpr = 0x00008000, /* Next Page Request */
262 TxcwConfig = 0x40000000, /* Transmit Config Control */
263 TxcwAne = 0x80000000, /* Auto-Negotiation Enable */
264 };
265
266 enum { /* Rctl */
267 Rrst = 0x00000001, /* Receiver Software Reset */
268 Ren = 0x00000002, /* Receiver Enable */
269 Sbp = 0x00000004, /* Store Bad Packets */
270 Upe = 0x00000008, /* Unicast Promiscuous Enable */
271 Mpe = 0x00000010, /* Multicast Promiscuous Enable */
272 Lpe = 0x00000020, /* Long Packet Reception Enable */
273 LbmMASK = 0x000000C0, /* Loopback Mode */
274 LbmOFF = 0x00000000, /* No Loopback */
275 LbmTBI = 0x00000040, /* TBI Loopback */
276 LbmMII = 0x00000080, /* GMII/MII Loopback */
277 LbmXCVR = 0x000000C0, /* Transceiver Loopback */
278 RdtmsMASK = 0x00000300, /* Rdesc Minimum Threshold Size */
279 RdtmsHALF = 0x00000000, /* Threshold is 1/2 Rdlen */
280 RdtmsQUARTER = 0x00000100, /* Threshold is 1/4 Rdlen */
281 RdtmsEIGHTH = 0x00000200, /* Threshold is 1/8 Rdlen */
282 MoMASK = 0x00003000, /* Multicast Offset */
283 Bam = 0x00008000, /* Broadcast Accept Mode */
284 BsizeMASK = 0x00030000, /* Receive Buffer Size */
285 Bsize16384 = 0x00010000, /* Bsex = 1 */
286 Bsize8192 = 0x00020000, /* Bsex = 1 */
287 Bsize2048 = 0x00000000,
288 Bsize1024 = 0x00010000,
289 Bsize512 = 0x00020000,
290 Bsize256 = 0x00030000,
291 BsizeFlex = 0x08000000, /* Flexible Bsize in 1KB increments */
292 Vfe = 0x00040000, /* VLAN Filter Enable */
293 Cfien = 0x00080000, /* Canonical Form Indicator Enable */
294 Cfi = 0x00100000, /* Canonical Form Indicator value */
295 Dpf = 0x00400000, /* Discard Pause Frames */
296 Pmcf = 0x00800000, /* Pass MAC Control Frames */
297 Bsex = 0x02000000, /* Buffer Size Extension */
298 Secrc = 0x04000000, /* Strip CRC from incoming packet */
299 };
300
301 enum { /* Tctl */
302 Trst = 0x00000001, /* Transmitter Software Reset */
303 Ten = 0x00000002, /* Transmit Enable */
304 Psp = 0x00000008, /* Pad Short Packets */
305 Mulr = 0x10000000, /* Allow multiple concurrent requests */
306 Ctmask = 0x00000FF0, /* Collision Threshold */
307 Ctshift = 4,
308 ColdMASK = 0x003FF000, /* Collision Distance */
309 ColdSHIFT = 12,
310 Swxoff = 0x00400000, /* Sofware XOFF Transmission */
311 Pbe = 0x00800000, /* Packet Burst Enable */
312 Rtlc = 0x01000000, /* Re-transmit on Late Collision */
313 Nrtu = 0x02000000, /* No Re-transmit on Underrrun */
314 };
315
316 enum { /* [RT]xdctl */
317 PthreshMASK = 0x0000003F, /* Prefetch Threshold */
318 PthreshSHIFT = 0,
319 HthreshMASK = 0x00003F00, /* Host Threshold */
320 HthreshSHIFT = 8,
321 WthreshMASK = 0x003F0000, /* Writeback Threshold */
322 WthreshSHIFT = 16,
323 Gran = 0x01000000, /* Granularity (descriptors, not cls) */
324 Qenable = 0x02000000, /* Queue Enable (82575) */
325 };
326
327 enum { /* Rxcsum */
328 PcssMASK = 0x00FF, /* Packet Checksum Start */
329 PcssSHIFT = 0,
330 Ipofl = 0x0100, /* IP Checksum Off-load Enable */
331 Tuofl = 0x0200, /* TCP/UDP Checksum Off-load Enable */
332 };
333
334 enum { /* Receive Delay Timer Ring */
335 DelayMASK = 0xFFFF, /* delay timer in 1.024nS increments */
336 DelaySHIFT = 0,
337 Fpd = 0x80000000, /* Flush partial Descriptor Block */
338 };
339
340 typedef struct Ctlr Ctlr;
341 typedef struct Rd Rd;
342 typedef struct Td Td;
343
344 struct Rd { /* Receive Descriptor */
345 u32int addr[2];
346 u16int length;
347 u16int checksum;
348 u8int status;
349 u8int errors;
350 u16int special;
351 };
352
353 enum { /* Rd status */
354 Rdd = 0x01, /* Descriptor Done */
355 Reop = 0x02, /* End of Packet */
356 Ixsm = 0x04, /* Ignore Checksum Indication */
357 Vp = 0x08, /* Packet is 802.1Q (matched VET) */
358 Tcpcs = 0x20, /* TCP Checksum Calculated on Packet */
359 Ipcs = 0x40, /* IP Checksum Calculated on Packet */
360 Pif = 0x80, /* Passed in-exact filter */
361 };
362
363 enum { /* Rd errors */
364 Ce = 0x01, /* CRC Error or Alignment Error */
365 Se = 0x02, /* Symbol Error */
366 Seq = 0x04, /* Sequence Error */
367 Cxe = 0x10, /* Carrier Extension Error */
368 Tcpe = 0x20, /* TCP/UDP Checksum Error */
369 Ipe = 0x40, /* IP Checksum Error */
370 Rxe = 0x80, /* RX Data Error */
371 };
372
373 struct Td { /* Transmit Descriptor */
374 u32int addr[2]; /* Data */
375 u32int control;
376 u32int status;
377 };
378
379 enum { /* Tdesc control */
380 LenMASK = 0x000FFFFF, /* Data/Packet Length Field */
381 LenSHIFT = 0,
382 DtypeCD = 0x00000000, /* Data Type 'Context Descriptor' */
383 DtypeDD = 0x00100000, /* Data Type 'Data Descriptor' */
384 PtypeTCP = 0x01000000, /* TCP/UDP Packet Type (CD) */
385 Teop = 0x01000000, /* End of Packet (DD) */
386 PtypeIP = 0x02000000, /* IP Packet Type (CD) */
387 Ifcs = 0x02000000, /* Insert FCS (DD) */
388 Tse = 0x04000000, /* TCP Segmentation Enable */
389 Rs = 0x08000000, /* Report Status */
390 Rps = 0x10000000, /* Report Status Sent */
391 Dext = 0x20000000, /* Descriptor Extension */
392 Vle = 0x40000000, /* VLAN Packet Enable */
393 Ide = 0x80000000, /* Interrupt Delay Enable */
394 };
395
396 enum { /* Tdesc status */
397 Tdd = 0x0001, /* Descriptor Done */
398 Ec = 0x0002, /* Excess Collisions */
399 Lc = 0x0004, /* Late Collision */
400 Tu = 0x0008, /* Transmit Underrun */
401 CssMASK = 0xFF00, /* Checksum Start Field */
402 CssSHIFT = 8,
403 };
404
405 typedef struct {
406 u16int *reg;
407 u32int *reg32;
408 u16int base;
409 u16int lim;
410 } Flash;
411
412 enum {
413 /* 16 and 32-bit flash registers for ich flash parts */
414 Bfpr = 0x00/4, /* flash base 0:12; lim 16:28 */
415 Fsts = 0x04/2, /* flash status; Hsfsts */
416 Fctl = 0x06/2, /* flash control; Hsfctl */
417 Faddr = 0x08/4, /* flash address to r/w */
418 Fdata = 0x10/4, /* data @ address */
419
420 /* status register */
421 Fdone = 1<<0, /* flash cycle done */
422 Fcerr = 1<<1, /* cycle error; write 1 to clear */
423 Ael = 1<<2, /* direct access error log; 1 to clear */
424 Scip = 1<<5, /* spi cycle in progress */
425 Fvalid = 1<<14, /* flash descriptor valid */
426
427 /* control register */
428 Fgo = 1<<0, /* start cycle */
429 Flcycle = 1<<1, /* two bits: r=0; w=2 */
430 Fdbc = 1<<8, /* bytes to read; 5 bits */
431 };
432
433 /*
434 * the kumeran interface is mac-to-phy for external gigabit ethernet on
435 * intel's esb2 ich8 (io controller hub), it carries mii bits. can be used
436 * to reset the phy. intel proprietary, see "kumeran specification".
437 */
438 enum {
439 I217inbandctlpage = 770, /* phy page */
440 I217inbandctlreg = 18, /* phy register */
441 I217inbandctllnkststxtmoutmask = 0x3F00,
442 I217inbandctllnkststxtmoutshift = 8,
443
444 Fextnvm6reqpllclk = 0x100,
445 Fextnvm6enak1entrycond = 0x200, /* extend K1 entry latency */
446
447 Nvmk1cfg = 0x1B, /* NVM K1 Config Word */
448 Nvmk1enable = 0x1, /* NVM Enable K1 bit */
449
450 Kumctrlstaoff = 0x1F0000,
451 Kumctrlstaoffshift = 16,
452 Kumctrlstaren = 0x200000, /* read enable */
453 Kumctrlstak1cfg = 0x7,
454 Kumctrlstak1enable = 0x2,
455 };
456
457 enum {
458 /*
459 * these were 512, 1024 & 64, but 52, 253 & 9 are usually ample;
460 * however cpu servers and terminals can need more receive buffers
461 * due to bursts of traffic.
462 *
463 * Tdlen and Rdlen have to be multiples of 128. Rd and Td are both
464 * 16 bytes long, so Nrd and Ntd must be multiples of 8.
465 */
466 Ntd = 32, /* power of two >= 8 */
467 Nrd = 128, /* power of two >= 8 */
468 Nrb = 1024, /* private receive buffers per Ctlr */
469 Slop = 32, /* for vlan headers, crcs, etc. */
470 };
471
472 enum {
473 Iany,
474 i82563,
475 i82566,
476 i82567,
477 i82571,
478 i82572,
479 i82573,
480 i82574,
481 i82575,
482 i82576,
483 i82577,
484 i82579,
485 i210,
486 i217,
487 i218,
488 };
489
490 static char *tname[] = {
491 [Iany] "any",
492 [i82563] "i82563",
493 [i82566] "i82566",
494 [i82567] "i82567",
495 [i82571] "i82571",
496 [i82572] "i82572",
497 [i82573] "i82573",
498 [i82574] "i82574",
499 [i82575] "i82575",
500 [i82576] "i82576",
501 [i82577] "i82577",
502 [i82579] "i82579",
503 [i210] "i210",
504 [i217] "i217",
505 [i218] "i218",
506 };
507
508 struct Ctlr {
509 int port;
510 Pcidev *pcidev;
511 Ctlr *next;
512 Ether *edev;
513 int active;
514 int type;
515 ushort eeprom[0x40];
516
517 QLock alock; /* attach */
518 int attached;
519
520 int *nic;
521 Lock imlock;
522 int im; /* interrupt mask */
523
524 Rendez lrendez;
525 int lim;
526 int phynum;
527 int didk1fix;
528
529 Watermark wmrb;
530 Watermark wmrd;
531 Watermark wmtd;
532
533 QLock slock;
534 uint statistics[Nstatistics];
535 uint lsleep;
536 uint lintr;
537 uint rsleep;
538 uint rintr;
539 uint txdw;
540 uint tintr;
541 uint ixsm;
542 uint ipcs;
543 uint tcpcs;
544 uint speeds[4];
545
546 uchar ra[Eaddrlen]; /* receive address */
547 ulong mta[128]; /* maximal multicast table array */
548
549 Rendez rrendez;
550 int rim;
551 int rdfree; /* rx descriptors awaiting packets */
552 Rd *rdba; /* receive descriptor base address */
553 Block **rb; /* receive buffers */
554 int rdh; /* receive descriptor head */
555 int rdt; /* receive descriptor tail */
556
557 Rendez trendez;
558 QLock tlock;
559 Td *tdba; /* transmit descriptor base address */
560 Block **tb; /* transmit buffers */
561 int tdh; /* transmit descriptor head */
562 int tdt; /* transmit descriptor tail */
563
564 int fcrtl;
565 int fcrth;
566
567 uint pbs; /* packet buffer size */
568 uint pba; /* packet buffer allocation */
569 };
570
571 #define csr32r(c, r) (*((c)->nic+((r)/4)))
572 #define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v))
573
574 static Ctlr* i82563ctlrhead;
575 static Ctlr* i82563ctlrtail;
576
577 static Lock i82563rblock; /* free receive Blocks */
578 static Block* i82563rbpool;
579 static int nrbfull; /* # of rcv Blocks with data awaiting processing */
580
581 static int speedtab[] = {
582 10, 100, 1000, 0
583 };
584
585 static char* statistics[] = {
586 "CRC Error",
587 "Alignment Error",
588 "Symbol Error",
589 "RX Error",
590 "Missed Packets",
591 "Single Collision",
592 "Excessive Collisions",
593 "Multiple Collision",
594 "Late Collisions",
595 nil,
596 "Collision",
597 "Transmit Underrun",
598 "Defer",
599 "Transmit - No CRS",
600 "Sequence Error",
601 "Carrier Extension Error",
602 "Receive Error Length",
603 nil,
604 "XON Received",
605 "XON Transmitted",
606 "XOFF Received",
607 "XOFF Transmitted",
608 "FC Received Unsupported",
609 "Packets Received (64 Bytes)",
610 "Packets Received (65-127 Bytes)",
611 "Packets Received (128-255 Bytes)",
612 "Packets Received (256-511 Bytes)",
613 "Packets Received (512-1023 Bytes)",
614 "Packets Received (1024-mtu Bytes)",
615 "Good Packets Received",
616 "Broadcast Packets Received",
617 "Multicast Packets Received",
618 "Good Packets Transmitted",
619 nil,
620 "Good Octets Received",
621 nil,
622 "Good Octets Transmitted",
623 nil,
624 nil,
625 nil,
626 "Receive No Buffers",
627 "Receive Undersize",
628 "Receive Fragment",
629 "Receive Oversize",
630 "Receive Jabber",
631 "Management Packets Rx",
632 "Management Packets Drop",
633 "Management Packets Tx",
634 "Total Octets Received",
635 nil,
636 "Total Octets Transmitted",
637 nil,
638 "Total Packets Received",
639 "Total Packets Transmitted",
640 "Packets Transmitted (64 Bytes)",
641 "Packets Transmitted (65-127 Bytes)",
642 "Packets Transmitted (128-255 Bytes)",
643 "Packets Transmitted (256-511 Bytes)",
644 "Packets Transmitted (512-1023 Bytes)",
645 "Packets Transmitted (1024-mtu Bytes)",
646 "Multicast Packets Transmitted",
647 "Broadcast Packets Transmitted",
648 "TCP Segmentation Context Transmitted",
649 "TCP Segmentation Context Fail",
650 "Interrupt Assertion",
651 "Interrupt Rx Pkt Timer",
652 "Interrupt Rx Abs Timer",
653 "Interrupt Tx Pkt Timer",
654 "Interrupt Tx Abs Timer",
655 "Interrupt Tx Queue Empty",
656 "Interrupt Tx Desc Low",
657 "Interrupt Rx Min",
658 "Interrupt Rx Overrun",
659 };
660
661 static int i82563reset(Ctlr *);
662
663 static long
i82563ifstat(Ether * edev,void * a,long n,ulong offset)664 i82563ifstat(Ether* edev, void* a, long n, ulong offset)
665 {
666 Ctlr *ctlr;
667 char *s, *p, *e, *stat;
668 int i, r;
669 uvlong tuvl, ruvl;
670
671 ctlr = edev->ctlr;
672 qlock(&ctlr->slock);
673 p = s = malloc(READSTR);
674 if(p == nil) {
675 qunlock(&ctlr->slock);
676 error(Enomem);
677 }
678 e = p + READSTR;
679
680 for(i = 0; i < Nstatistics; i++){
681 r = csr32r(ctlr, Statistics + i*4);
682 if((stat = statistics[i]) == nil)
683 continue;
684 switch(i){
685 case Gorcl:
686 case Gotcl:
687 case Torl:
688 case Totl:
689 ruvl = r;
690 ruvl += (uvlong)csr32r(ctlr, Statistics+(i+1)*4) << 32;
691 tuvl = ruvl;
692 tuvl += ctlr->statistics[i];
693 tuvl += (uvlong)ctlr->statistics[i+1] << 32;
694 if(tuvl == 0)
695 continue;
696 ctlr->statistics[i] = tuvl;
697 ctlr->statistics[i+1] = tuvl >> 32;
698 p = seprint(p, e, "%s: %llud %llud\n", stat, tuvl, ruvl);
699 i++;
700 break;
701
702 default:
703 ctlr->statistics[i] += r;
704 if(ctlr->statistics[i] == 0)
705 continue;
706 p = seprint(p, e, "%s: %ud %ud\n", stat,
707 ctlr->statistics[i], r);
708 break;
709 }
710 }
711
712 p = seprint(p, e, "lintr: %ud %ud\n", ctlr->lintr, ctlr->lsleep);
713 p = seprint(p, e, "rintr: %ud %ud\n", ctlr->rintr, ctlr->rsleep);
714 p = seprint(p, e, "tintr: %ud %ud\n", ctlr->tintr, ctlr->txdw);
715 p = seprint(p, e, "ixcs: %ud %ud %ud\n", ctlr->ixsm, ctlr->ipcs, ctlr->tcpcs);
716 p = seprint(p, e, "ctrl: %.8ux\n", csr32r(ctlr, Ctrl));
717 p = seprint(p, e, "ctrlext: %.8ux\n", csr32r(ctlr, Ctrlext));
718 p = seprint(p, e, "status: %.8ux\n", csr32r(ctlr, Status));
719 p = seprint(p, e, "txcw: %.8ux\n", csr32r(ctlr, Txcw));
720 p = seprint(p, e, "txdctl: %.8ux\n", csr32r(ctlr, Txdctl));
721 p = seprint(p, e, "pbs: %dKB\n", ctlr->pbs);
722 p = seprint(p, e, "pba: %#.8ux\n", ctlr->pba);
723
724 p = seprint(p, e, "speeds: 10:%ud 100:%ud 1000:%ud ?:%ud\n",
725 ctlr->speeds[0], ctlr->speeds[1], ctlr->speeds[2], ctlr->speeds[3]);
726 p = seprint(p, e, "type: %s\n", tname[ctlr->type]);
727 p = seprint(p, e, "nrbfull (rcv blocks outstanding): %d\n", nrbfull);
728
729 // p = seprint(p, e, "eeprom:");
730 // for(i = 0; i < 0x40; i++){
731 // if(i && ((i & 7) == 0))
732 // p = seprint(p, e, "\n ");
733 // p = seprint(p, e, " %4.4ux", ctlr->eeprom[i]);
734 // }
735 // p = seprint(p, e, "\n");
736
737 p = seprintmark(p, e, &ctlr->wmrb);
738 p = seprintmark(p, e, &ctlr->wmrd);
739 p = seprintmark(p, e, &ctlr->wmtd);
740
741 USED(p);
742 n = readstr(offset, a, n, s);
743 free(s);
744 qunlock(&ctlr->slock);
745
746 return n;
747 }
748
749 static long
i82563ctl(Ether *,void *,long)750 i82563ctl(Ether*, void*, long)
751 {
752 error(Enonexist);
753 return 0;
754 }
755
756 static void
i82563promiscuous(void * arg,int on)757 i82563promiscuous(void* arg, int on)
758 {
759 int rctl;
760 Ctlr *ctlr;
761 Ether *edev;
762
763 edev = arg;
764 ctlr = edev->ctlr;
765
766 rctl = csr32r(ctlr, Rctl) & ~MoMASK;
767 if(on)
768 rctl |= Upe|Mpe;
769 else
770 rctl &= ~(Upe|Mpe);
771 csr32w(ctlr, Rctl, rctl);
772 }
773
774 /*
775 * Returns the number of bits of mac address used in multicast hash,
776 * thus the number of longs of ctlr->mta (2^(bits-5)).
777 * This must be right for multicast (thus ipv6) to work reliably.
778 *
779 * The default multicast hash for mta is based on 12 bits of MAC address;
780 * the rightmost bit is a function of Rctl's Multicast Offset: 0=>36,
781 * 1=>35, 2=>34, 3=>32. Exceptions include the 578, 579, 217, 218, 219;
782 * they use only 10 bits, ignoring the rightmost 2 of the 12.
783 */
784 static int
mcastbits(Ctlr * ctlr)785 mcastbits(Ctlr *ctlr)
786 {
787 switch (ctlr->type) {
788 /*
789 * openbsd says all `ich8' versions (ich8, ich9, ich10, pch, pch2 and
790 * pch_lpt) have 32 longs (use 10 bits of mac address for hash).
791 */
792 case i82566:
793 case i82567:
794 // case i82578:
795 case i82579:
796 case i217:
797 case i218:
798 // case i219:
799 return 10; /* 32 longs */
800 case i82563:
801 case i82571:
802 case i82572:
803 case i82573:
804 case i82574:
805 // case i82575:
806 // case i82583:
807 case i210: /* includes i211 */
808 return 12; /* 128 longs */
809 default:
810 print("82563: unsure of multicast bits in mac addresses; "
811 "enabling promiscuous multicast reception\n");
812 csr32w(ctlr, Rctl, csr32r(ctlr, Rctl) | Mpe);
813 return 10; /* be conservative (for mta size) */
814 }
815 }
816
817 static int
mcbitstolongs(int nmcbits)818 mcbitstolongs(int nmcbits)
819 {
820 return 1 << (nmcbits - 5); /* 2^5 = 32 */
821 }
822
823 static void
i82563multicast(void * arg,uchar * addr,int on)824 i82563multicast(void* arg, uchar* addr, int on)
825 {
826 ulong nbits, tblsz, hash, word, bit;
827 Ctlr *ctlr;
828 Ether *edev;
829
830 edev = arg;
831 ctlr = edev->ctlr;
832
833 nbits = mcastbits(ctlr);
834 tblsz = mcbitstolongs(nbits);
835 /* assume multicast offset in Rctl is 0 (we clear it above) */
836 hash = addr[5] << 4 | addr[4] >> 4; /* bits 47:36 of mac */
837 if (nbits == 10)
838 hash >>= 2; /* discard 37:36 of mac */
839 word = (hash / 32) & (tblsz - 1);
840 bit = 1UL << (hash % 32);
841 /*
842 * multiple ether addresses can hash to the same filter bit,
843 * so it's never safe to clear a filter bit.
844 * if we want to clear filter bits, we need to keep track of
845 * all the multicast addresses in use, clear all the filter bits,
846 * then set the ones corresponding to in-use addresses.
847 */
848 if(on)
849 ctlr->mta[word] |= bit;
850 // else
851 // ctlr->mta[word] &= ~bit;
852 csr32w(ctlr, Mta+word*4, ctlr->mta[word]);
853 }
854
855 static Block*
i82563rballoc(void)856 i82563rballoc(void)
857 {
858 Block *bp;
859
860 ilock(&i82563rblock);
861 if((bp = i82563rbpool) != nil){
862 i82563rbpool = bp->next;
863 bp->next = nil;
864 ainc(&bp->ref); /* prevent bp from being freed */
865 }
866 iunlock(&i82563rblock);
867
868 return bp;
869 }
870
871 static void
i82563rbfree(Block * b)872 i82563rbfree(Block* b)
873 {
874 b->rp = b->wp = (uchar*)PGROUND((uintptr)b->base);
875 b->flag &= ~(Bipck | Budpck | Btcpck | Bpktck);
876 ilock(&i82563rblock);
877 b->next = i82563rbpool;
878 i82563rbpool = b;
879 nrbfull--;
880 iunlock(&i82563rblock);
881 }
882
883 static void
i82563im(Ctlr * ctlr,int im)884 i82563im(Ctlr* ctlr, int im)
885 {
886 ilock(&ctlr->imlock);
887 ctlr->im |= im;
888 csr32w(ctlr, Ims, ctlr->im);
889 iunlock(&ctlr->imlock);
890 }
891
892 static void
i82563txinit(Ctlr * ctlr)893 i82563txinit(Ctlr* ctlr)
894 {
895 int i, r, tctl;
896 Block *bp;
897
898 tctl = 0x0F<<Ctshift | Psp;
899 switch (ctlr->type) {
900 case i210:
901 break;
902 default:
903 tctl |= Mulr;
904 /* fall through */
905 case i217:
906 case i218:
907 tctl |= 66<<ColdSHIFT;
908 break;
909 }
910 csr32w(ctlr, Tctl, tctl);
911 csr32w(ctlr, Tipg, 6<<20 | 8<<10 | 8); /* yb sez: 0x702008 */
912 for(i = 0; i < Ntd; i++)
913 if((bp = ctlr->tb[i]) != nil) {
914 ctlr->tb[i] = nil;
915 freeb(bp);
916 }
917 memset(ctlr->tdba, 0, Ntd * sizeof(Td));
918 coherence();
919 csr32w(ctlr, Tdbal, PCIWADDR(ctlr->tdba));
920 csr32w(ctlr, Tdbah, 0); /* 32-bit system */
921 csr32w(ctlr, Tdlen, Ntd * sizeof(Td));
922 ctlr->tdh = PREV(0, Ntd);
923 csr32w(ctlr, Tdh, 0);
924 ctlr->tdt = 0;
925 csr32w(ctlr, Tdt, 0);
926 csr32w(ctlr, Tidv, 0); /* don't coalesce interrupts */
927 csr32w(ctlr, Tadv, 0);
928 r = csr32r(ctlr, Txdctl) & ~(WthreshMASK|PthreshMASK);
929 r |= 4<<WthreshSHIFT | 4<<PthreshSHIFT;
930 if(ctlr->type == i82575 || ctlr->type == i82576 || ctlr->type == i210)
931 r |= Qenable;
932 csr32w(ctlr, Txdctl, r);
933 coherence();
934 csr32w(ctlr, Tctl, csr32r(ctlr, Tctl) | Ten);
935 }
936
937 static int
i82563cleanup(Ctlr * ctlr)938 i82563cleanup(Ctlr *ctlr)
939 {
940 Block *bp;
941 int tdh, n;
942
943 tdh = ctlr->tdh;
944 while(ctlr->tdba[n = NEXT(tdh, Ntd)].status & Tdd){
945 tdh = n;
946 if((bp = ctlr->tb[tdh]) != nil){
947 ctlr->tb[tdh] = nil;
948 freeb(bp);
949 }else
950 iprint("82563 tx underrun!\n");
951 ctlr->tdba[tdh].status = 0;
952 }
953 return ctlr->tdh = tdh;
954 }
955
956 static void
i82563transmit(Ether * edev)957 i82563transmit(Ether* edev)
958 {
959 Td *td;
960 Block *bp;
961 Ctlr *ctlr;
962 int tdh, tdt;
963
964 ctlr = edev->ctlr;
965 qlock(&ctlr->tlock);
966
967 /*
968 * Free any completed packets
969 */
970 tdh = i82563cleanup(ctlr);
971
972 /* if link down on 218, don't try since we need k1fix to run first */
973 if (!edev->link && ctlr->type == i218 && !ctlr->didk1fix) {
974 qunlock(&ctlr->tlock);
975 return;
976 }
977
978 /*
979 * Try to fill the ring back up.
980 */
981 tdt = ctlr->tdt;
982 for(;;){
983 if(NEXT(tdt, Ntd) == tdh){ /* ring full? */
984 ctlr->txdw++;
985 i82563im(ctlr, Txdw);
986 break;
987 }
988 if((bp = qget(edev->oq)) == nil)
989 break;
990 td = &ctlr->tdba[tdt];
991 td->addr[0] = PCIWADDR(bp->rp);
992 td->control = Ide|Rs|Ifcs|Teop|BLEN(bp);
993 ctlr->tb[tdt] = bp;
994 /* note size of queue of tds awaiting transmission */
995 notemark(&ctlr->wmtd, (tdt + Ntd - tdh) % Ntd);
996 tdt = NEXT(tdt, Ntd);
997 }
998 if(ctlr->tdt != tdt){
999 ctlr->tdt = tdt;
1000 coherence();
1001 csr32w(ctlr, Tdt, tdt);
1002 }
1003 /* else may not be any new ones, but could be some still in flight */
1004 qunlock(&ctlr->tlock);
1005 }
1006
1007 static void
i82563replenish(Ctlr * ctlr)1008 i82563replenish(Ctlr* ctlr)
1009 {
1010 Rd *rd;
1011 int rdt;
1012 Block *bp;
1013
1014 rdt = ctlr->rdt;
1015 while(NEXT(rdt, Nrd) != ctlr->rdh){
1016 rd = &ctlr->rdba[rdt];
1017 if(ctlr->rb[rdt] != nil){
1018 print("#l%d: 82563: rx overrun\n", ctlr->edev->ctlrno);
1019 break;
1020 }
1021 bp = i82563rballoc();
1022 if(bp == nil)
1023 /*
1024 * this almost never gets better. likely there's a bug
1025 * elsewhere in the kernel that is failing to free a
1026 * receive Block.
1027 */
1028 panic("#l%d: 82563: all %d rx buffers in use, nrbfull %d",
1029 ctlr->edev->ctlrno, Nrb, nrbfull);
1030 ctlr->rb[rdt] = bp;
1031 rd->addr[0] = PCIWADDR(bp->rp);
1032 // rd->addr[1] = 0;
1033 rd->status = 0;
1034 ctlr->rdfree++;
1035 rdt = NEXT(rdt, Nrd);
1036 }
1037 ctlr->rdt = rdt;
1038 coherence();
1039 csr32w(ctlr, Rdt, rdt);
1040 }
1041
1042 static void
i82563rxinit(Ctlr * ctlr)1043 i82563rxinit(Ctlr* ctlr)
1044 {
1045 Block *bp;
1046 int i, r, rctl, type;
1047
1048 rctl = Dpf|Bsize2048|Bam|RdtmsHALF;
1049 type = ctlr->type;
1050 if(type == i82575 || type == i82576 || type == i210){
1051 /*
1052 * Setting Qenable in Rxdctl does not
1053 * appear to stick unless Ren is on.
1054 */
1055 csr32w(ctlr, Rctl, Ren|rctl);
1056 csr32w(ctlr, Rxdctl, csr32r(ctlr, Rxdctl) | Qenable);
1057 }
1058 csr32w(ctlr, Rctl, rctl);
1059
1060 switch (type) {
1061 case i82573:
1062 case i82577:
1063 // case i82577: /* not yet implemented */
1064 case i82579:
1065 case i210:
1066 case i217:
1067 case i218:
1068 csr32w(ctlr, Ert, 1024/8); /* early rx threshold */
1069 break;
1070 }
1071
1072 csr32w(ctlr, Rdbal, PCIWADDR(ctlr->rdba));
1073 csr32w(ctlr, Rdbah, 0); /* 32-bit system */
1074 csr32w(ctlr, Rdlen, Nrd * sizeof(Rd));
1075 ctlr->rdh = ctlr->rdt = 0;
1076 csr32w(ctlr, Rdh, 0);
1077 csr32w(ctlr, Rdt, 0);
1078
1079 /* to hell with interrupt moderation, we want low latency */
1080 csr32w(ctlr, Rdtr, 0);
1081 csr32w(ctlr, Radv, 0);
1082
1083 for(i = 0; i < Nrd; i++)
1084 if((bp = ctlr->rb[i]) != nil){
1085 ctlr->rb[i] = nil;
1086 freeb(bp);
1087 }
1088 i82563replenish(ctlr);
1089
1090 if(type == i82575 || type == i82576 || type == i210){
1091 /*
1092 * See comment above for Qenable.
1093 * Could shuffle the code?
1094 */
1095 r = csr32r(ctlr, Rxdctl) & ~(WthreshMASK|PthreshMASK);
1096 csr32w(ctlr, Rxdctl, r | 2<<WthreshSHIFT | 2<<PthreshSHIFT);
1097 }
1098
1099 /*
1100 * Don't enable checksum offload. In practice, it interferes with
1101 * tftp booting on at least the 82575.
1102 */
1103 csr32w(ctlr, Rxcsum, 0);
1104 }
1105
1106 static int
i82563rim(void * ctlr)1107 i82563rim(void* ctlr)
1108 {
1109 return ((Ctlr*)ctlr)->rim != 0;
1110 }
1111
1112 /*
1113 * With no errors and the Ixsm bit set,
1114 * the descriptor status Tpcs and Ipcs bits give
1115 * an indication of whether the checksums were
1116 * calculated and valid.
1117 *
1118 * Must be called with rd->errors == 0.
1119 */
1120 static void
ckcksums(Ctlr * ctlr,Rd * rd,Block * bp)1121 ckcksums(Ctlr *ctlr, Rd *rd, Block *bp)
1122 {
1123 if (0) {
1124 if(rd->status & Ixsm)
1125 return;
1126 ctlr->ixsm++;
1127 if(rd->status & Ipcs){
1128 /*
1129 * IP checksum calculated (and valid as errors == 0).
1130 */
1131 ctlr->ipcs++;
1132 bp->flag |= Bipck;
1133 }
1134 if(rd->status & Tcpcs){
1135 /*
1136 * TCP/UDP checksum calculated (and valid as errors == 0).
1137 */
1138 ctlr->tcpcs++;
1139 bp->flag |= Btcpck|Budpck;
1140 }
1141 bp->checksum = rd->checksum;
1142 bp->flag |= Bpktck;
1143 }
1144 }
1145
1146 static void
i82563rproc(void * arg)1147 i82563rproc(void* arg)
1148 {
1149 Rd *rd;
1150 Block *bp;
1151 Ctlr *ctlr;
1152 int rdh, rim, passed;
1153 Ether *edev;
1154
1155 edev = arg;
1156 ctlr = edev->ctlr;
1157 i82563rxinit(ctlr);
1158 coherence();
1159 csr32w(ctlr, Rctl, csr32r(ctlr, Rctl) | Ren);
1160
1161 if(ctlr->type == i210)
1162 csr32w(ctlr, Rxdctl, csr32r(ctlr, Rxdctl) | Qenable);
1163
1164 for(;;){
1165 i82563replenish(ctlr);
1166 i82563im(ctlr, Rxt0|Rxo|Rxdmt0|Rxseq|Ack);
1167 ctlr->rsleep++;
1168 sleep(&ctlr->rrendez, i82563rim, ctlr);
1169
1170 rdh = ctlr->rdh;
1171 passed = 0;
1172 for(;;){
1173 rim = ctlr->rim;
1174 ctlr->rim = 0;
1175 rd = &ctlr->rdba[rdh];
1176 if(!(rd->status & Rdd))
1177 break;
1178
1179 /*
1180 * Accept eop packets with no errors.
1181 */
1182 bp = ctlr->rb[rdh];
1183 if((rd->status & Reop) && rd->errors == 0){
1184 bp->wp += rd->length;
1185 bp->lim = bp->wp; /* lie like a dog. */
1186 if(0)
1187 ckcksums(ctlr, rd, bp);
1188 ilock(&i82563rblock);
1189 nrbfull++;
1190 iunlock(&i82563rblock);
1191 notemark(&ctlr->wmrb, nrbfull);
1192 etheriq(edev, bp, 1); /* pass pkt upstream */
1193 passed++;
1194 } else {
1195 if (rd->status & Reop && rd->errors)
1196 print("%s: input packet error %#ux\n",
1197 tname[ctlr->type], rd->errors);
1198 freeb(bp);
1199 }
1200 ctlr->rb[rdh] = nil;
1201
1202 /* rd needs to be replenished to accept another pkt */
1203 rd->status = 0;
1204 ctlr->rdfree--;
1205 ctlr->rdh = rdh = NEXT(rdh, Nrd);
1206 /*
1207 * if number of rds ready for packets is too low,
1208 * set up the unready ones.
1209 */
1210 if(ctlr->rdfree <= Nrd - 32 || (rim & Rxdmt0))
1211 i82563replenish(ctlr);
1212 }
1213 /* note how many rds had full buffers */
1214 notemark(&ctlr->wmrd, passed);
1215 }
1216 }
1217
1218 static int
i82563lim(void * ctlr)1219 i82563lim(void* ctlr)
1220 {
1221 return ((Ctlr*)ctlr)->lim != 0;
1222 }
1223
1224 static int
phynum(Ctlr * ctlr)1225 phynum(Ctlr *ctlr)
1226 {
1227 if (ctlr->phynum < 0)
1228 switch (ctlr->type) {
1229 case i82577:
1230 // case i82578: /* not yet implemented */
1231 case i82579:
1232 case i217:
1233 case i218:
1234 ctlr->phynum = 2; /* pcie phy */
1235 break;
1236 default:
1237 ctlr->phynum = 1; /* gbe phy */
1238 break;
1239 }
1240 return ctlr->phynum;
1241 }
1242
1243 static uint
phyread(Ctlr * ctlr,int reg)1244 phyread(Ctlr *ctlr, int reg)
1245 {
1246 uint phy, i;
1247
1248 if (reg >= 32)
1249 iprint("phyread: reg %d >= 32\n", reg);
1250 csr32w(ctlr, Mdic, MDIrop | phynum(ctlr)<<MDIpSHIFT | reg<<MDIrSHIFT);
1251 phy = 0;
1252 for(i = 0; i < 64; i++){
1253 phy = csr32r(ctlr, Mdic);
1254 if(phy & (MDIe|MDIready))
1255 break;
1256 microdelay(1);
1257 }
1258 if((phy & (MDIe|MDIready)) != MDIready)
1259 return ~0;
1260 return phy & 0xffff;
1261 }
1262
1263 static uint
phywrite(Ctlr * ctlr,int reg,ushort val)1264 phywrite(Ctlr *ctlr, int reg, ushort val)
1265 {
1266 uint phy, i;
1267
1268 if (reg >= 32)
1269 iprint("phyread: reg %d >= 32\n", reg);
1270 csr32w(ctlr, Mdic, MDIwop | phynum(ctlr)<<MDIpSHIFT | reg<<MDIrSHIFT |
1271 val);
1272 phy = 0;
1273 for(i = 0; i < 64; i++){
1274 phy = csr32r(ctlr, Mdic);
1275 if(phy & (MDIe|MDIready))
1276 break;
1277 microdelay(1);
1278 }
1279 if((phy & (MDIe|MDIready)) != MDIready)
1280 return ~0;
1281 return 0;
1282 }
1283
1284 static void
kmrnwrite(Ctlr * ctlr,ulong reg_addr,ushort data)1285 kmrnwrite(Ctlr *ctlr, ulong reg_addr, ushort data)
1286 {
1287 csr32w(ctlr, Kumctrlsta, ((reg_addr << Kumctrlstaoffshift) &
1288 Kumctrlstaoff) | data);
1289 microdelay(2);
1290 }
1291
1292 static ulong
kmrnread(Ctlr * ctlr,ulong reg_addr)1293 kmrnread(Ctlr *ctlr, ulong reg_addr)
1294 {
1295 csr32w(ctlr, Kumctrlsta, ((reg_addr << Kumctrlstaoffshift) &
1296 Kumctrlstaoff) | Kumctrlstaren); /* write register address */
1297 microdelay(2);
1298 return csr32r(ctlr, Kumctrlsta); /* read data */
1299 }
1300
1301 /*
1302 * this is essentially black magic. we blindly follow the incantations
1303 * prescribed by the god Intel:
1304 *
1305 * On ESB2, the MAC-to-PHY (Kumeran) interface must be configured after
1306 * link is up before any traffic is sent.
1307 *
1308 * workaround DMA unit hang on I218
1309 *
1310 * At 1Gbps link speed, one of the MAC's internal clocks can be stopped
1311 * for up to 4us when entering K1 (a power mode of the MAC-PHY
1312 * interconnect). If the MAC is waiting for completion indications for 2
1313 * DMA write requests into Host memory (e.g. descriptor writeback or Rx
1314 * packet writing) and the indications occur while the clock is stopped,
1315 * both indications will be missed by the MAC, causing the MAC to wait
1316 * for the completion indications and be unable to generate further DMA
1317 * write requests. This results in an apparent hardware hang.
1318 *
1319 * Work-around the bug by disabling the de-assertion of the clock request
1320 * when 1Gbps link is acquired (K1 must be disabled while doing this).
1321 * Also, set appropriate Tx re-transmission timeouts for 10 and 100-half
1322 * link speeds to avoid Tx hangs.
1323 */
1324 static void
k1fix(Ctlr * ctlr)1325 k1fix(Ctlr *ctlr)
1326 {
1327 int txtmout; /* units of 10µs */
1328 ulong fextnvm6, status;
1329 ushort reg;
1330 Ether *edev;
1331
1332 edev = ctlr->edev;
1333 fextnvm6 = csr32r(ctlr, Fextnvm6);
1334 status = csr32r(ctlr, Status);
1335 /* status speed bits are different on 21[78] than earlier ctlrs */
1336 if (edev->link && status & (Sspeed1000>>2)) {
1337 reg = kmrnread(ctlr, Kumctrlstak1cfg);
1338 kmrnwrite(ctlr, Kumctrlstak1cfg, reg & ~Kumctrlstak1enable);
1339 microdelay(10);
1340 csr32w(ctlr, Fextnvm6, fextnvm6 | Fextnvm6reqpllclk);
1341 kmrnwrite(ctlr, Kumctrlstak1cfg, reg);
1342 ctlr->didk1fix = 1;
1343 return;
1344 }
1345 /* else uncommon cases */
1346
1347 fextnvm6 &= ~Fextnvm6reqpllclk;
1348 /*
1349 * 217 manual claims not to have Frcdplx bit in status;
1350 * 218 manual just omits the non-phy registers.
1351 */
1352 if (!edev->link ||
1353 (status & (Sspeed100>>2|Frcdplx)) == (Sspeed100>>2|Frcdplx)) {
1354 csr32w(ctlr, Fextnvm6, fextnvm6);
1355 ctlr->didk1fix = 1;
1356 return;
1357 }
1358
1359 /* access other page via phy addr 1 reg 31, then access reg 16-30 */
1360 phywrite(ctlr, Phypage, I217inbandctlpage<<5);
1361 reg = phyread(ctlr, I217inbandctlreg) & ~I217inbandctllnkststxtmoutmask;
1362 if (status & (Sspeed100>>2)) { /* 100Mb/s half-duplex? */
1363 txtmout = 5;
1364 fextnvm6 &= ~Fextnvm6enak1entrycond;
1365 } else { /* 10Mb/s */
1366 txtmout = 50;
1367 fextnvm6 |= Fextnvm6enak1entrycond;
1368 }
1369 phywrite(ctlr, I217inbandctlreg, reg |
1370 txtmout << I217inbandctllnkststxtmoutshift);
1371 csr32w(ctlr, Fextnvm6, fextnvm6);
1372 phywrite(ctlr, Phypage, 0<<5); /* reset page to usual 0 */
1373 ctlr->didk1fix = 1;
1374 }
1375
1376 /*
1377 * watch for changes of link state
1378 */
1379 static void
i82563lproc(void * v)1380 i82563lproc(void *v)
1381 {
1382 uint phy, sp, a, phy79, prevlink;
1383 Ctlr *ctlr;
1384 Ether *edev;
1385
1386 edev = v;
1387 ctlr = edev->ctlr;
1388 phy79 = 0;
1389 switch (ctlr->type) {
1390 case i82579:
1391 // case i82580:
1392 case i217:
1393 case i218:
1394 // case i219:
1395 // case i350:
1396 // case i354:
1397 phy79 = 1;
1398 break;
1399 }
1400 if(ctlr->type == i82573 && (phy = phyread(ctlr, Phyier)) != ~0)
1401 phywrite(ctlr, Phyier, phy | Lscie | Ancie | Spdie | Panie);
1402 else if(phy79 && (phy = phyread(ctlr, Phyier218)) != ~0)
1403 phywrite(ctlr, Phyier218, phy | Lscie218 | Ancie218 | Spdie218);
1404 prevlink = 0;
1405 for(;;){
1406 a = 0;
1407 phy = phyread(ctlr, phy79? Phystat: Physsr);
1408 if(phy == ~0)
1409 goto next;
1410 if (phy79) {
1411 sp = (phy>>8) & 3;
1412 // a = phy & (ctlr->type == i218? Anfs: Ans);
1413 a = phy & Anfs;
1414 } else {
1415 sp = (phy>>14) & 3;
1416 switch(ctlr->type){
1417 case i82563:
1418 case i210:
1419 a = phyread(ctlr, Phyisr) & Ane; /* a-n error */
1420 break;
1421 case i82571:
1422 case i82572:
1423 case i82575:
1424 case i82576:
1425 a = phyread(ctlr, Phylhr) & Anf; /* a-n fault */
1426 sp = (sp-1) & 3;
1427 break;
1428 }
1429 }
1430 if(a)
1431 phywrite(ctlr, Phyctl, phyread(ctlr, Phyctl) |
1432 Ran | Ean); /* enable & restart autoneg */
1433 edev->link = (phy & (phy79? Link: Rtlink)) != 0;
1434 if(edev->link){
1435 ctlr->speeds[sp]++;
1436 if (speedtab[sp])
1437 edev->mbps = speedtab[sp];
1438 if (prevlink == 0 && ctlr->type == i218)
1439 k1fix(ctlr); /* link newly up: kludge away */
1440 } else
1441 ctlr->didk1fix = 0; /* force fix at next link up */
1442 prevlink = edev->link;
1443 next:
1444 ctlr->lim = 0;
1445 i82563im(ctlr, Lsc);
1446 ctlr->lsleep++;
1447 sleep(&ctlr->lrendez, i82563lim, ctlr);
1448 }
1449 }
1450
1451 static void
i82563tproc(void * v)1452 i82563tproc(void *v)
1453 {
1454 Ether *edev;
1455 Ctlr *ctlr;
1456
1457 edev = v;
1458 ctlr = edev->ctlr;
1459 for(;;){
1460 sleep(&ctlr->trendez, return0, 0);
1461 i82563transmit(edev);
1462 }
1463 }
1464
1465 /*
1466 * controller is buggered; shock it back to life.
1467 */
1468 static void
restart(Ctlr * ctlr)1469 restart(Ctlr *ctlr)
1470 {
1471 if (0) {
1472 static Lock rstlock;
1473
1474 qlock(&ctlr->tlock);
1475 ilock(&rstlock);
1476 iprint("#l%d: resetting...", ctlr->edev->ctlrno);
1477 i82563reset(ctlr);
1478 /* [rt]xinit reset the ring indices */
1479 i82563txinit(ctlr);
1480 i82563rxinit(ctlr);
1481 coherence();
1482 csr32w(ctlr, Rctl, csr32r(ctlr, Rctl) | Ren);
1483 iunlock(&rstlock);
1484 qunlock(&ctlr->tlock);
1485 iprint("reset\n");
1486 }
1487 }
1488
1489 static void
freerbs(Ctlr *)1490 freerbs(Ctlr *)
1491 {
1492 int i;
1493 Block *bp;
1494
1495 for(i = Nrb; i > 0; i--){
1496 bp = i82563rballoc();
1497 bp->free = nil;
1498 freeb(bp);
1499 }
1500 }
1501
1502 static void
freemem(Ctlr * ctlr)1503 freemem(Ctlr *ctlr)
1504 {
1505 freerbs(ctlr);
1506 free(ctlr->tb);
1507 ctlr->tb = nil;
1508 free(ctlr->rb);
1509 ctlr->rb = nil;
1510 free(ctlr->tdba);
1511 ctlr->tdba = nil;
1512 free(ctlr->rdba);
1513 ctlr->rdba = nil;
1514 }
1515
1516 static void
i82563attach(Ether * edev)1517 i82563attach(Ether* edev)
1518 {
1519 int i;
1520 Block *bp;
1521 Ctlr *ctlr;
1522 char name[KNAMELEN];
1523
1524 ctlr = edev->ctlr;
1525 qlock(&ctlr->alock);
1526
1527 if(ctlr->attached){
1528 qunlock(&ctlr->alock);
1529 return;
1530 }
1531
1532 if(waserror()){
1533 freemem(ctlr);
1534 qunlock(&ctlr->alock);
1535 nexterror();
1536 }
1537
1538 ctlr->rdba = mallocalign(Nrd * sizeof(Rd), 128, 0, 0);
1539 ctlr->tdba = mallocalign(Ntd * sizeof(Td), 128, 0, 0);
1540 if(ctlr->rdba == nil || ctlr->tdba == nil ||
1541 (ctlr->rb = malloc(Nrd*sizeof(Block*))) == nil ||
1542 (ctlr->tb = malloc(Ntd*sizeof(Block*))) == nil)
1543 error(Enomem);
1544
1545 for(i = 0; i < Nrb; i++){
1546 if((bp = allocb(ETHERMAXTU + Slop + BY2PG)) == nil)
1547 error(Enomem);
1548 bp->free = i82563rbfree;
1549 freeb(bp);
1550 }
1551 nrbfull = 0;
1552
1553 ctlr->edev = edev; /* point back to Ether* */
1554 ctlr->attached = 1;
1555 initmark(&ctlr->wmrb, Nrb, "rcv bufs unprocessed");
1556 initmark(&ctlr->wmrd, Nrd-1, "rcv descrs processed at once");
1557 initmark(&ctlr->wmtd, Ntd-1, "xmit descr queue len");
1558
1559 snprint(name, sizeof name, "#l%dl", edev->ctlrno);
1560 kproc(name, i82563lproc, edev);
1561
1562 snprint(name, sizeof name, "#l%dr", edev->ctlrno);
1563 kproc(name, i82563rproc, edev);
1564
1565 snprint(name, sizeof name, "#l%dt", edev->ctlrno);
1566 kproc(name, i82563tproc, edev);
1567
1568 i82563txinit(ctlr);
1569
1570 qunlock(&ctlr->alock);
1571 poperror();
1572 }
1573
1574 static void
i82563interrupt(Ureg *,void * arg)1575 i82563interrupt(Ureg*, void* arg)
1576 {
1577 Ctlr *ctlr;
1578 Ether *edev;
1579 int icr, im, i;
1580
1581 edev = arg;
1582 ctlr = edev->ctlr;
1583 ilock(&ctlr->imlock);
1584 csr32w(ctlr, Imc, ~0);
1585 im = ctlr->im;
1586 i = Nrd; /* don't livelock */
1587 for(icr = csr32r(ctlr, Icr); icr & ctlr->im && i-- > 0;
1588 icr = csr32r(ctlr, Icr)){
1589 if(icr & Lsc){
1590 im &= ~Lsc;
1591 ctlr->lim = icr & Lsc;
1592 wakeup(&ctlr->lrendez);
1593 ctlr->lintr++;
1594 }
1595 if(icr & (Rxt0|Rxo|Rxdmt0|Rxseq|Ack)){
1596 ctlr->rim = icr & (Rxt0|Rxo|Rxdmt0|Rxseq|Ack);
1597 im &= ~(Rxt0|Rxo|Rxdmt0|Rxseq|Ack);
1598 wakeup(&ctlr->rrendez);
1599 ctlr->rintr++;
1600 }
1601 if(icr & Txdw){
1602 im &= ~Txdw;
1603 ctlr->tintr++;
1604 wakeup(&ctlr->trendez);
1605 }
1606 }
1607 ctlr->im = im;
1608 csr32w(ctlr, Ims, im);
1609 iunlock(&ctlr->imlock);
1610 }
1611
1612 /* assume misrouted interrupts and check all controllers */
1613 static void
i82575interrupt(Ureg *,void *)1614 i82575interrupt(Ureg*, void *)
1615 {
1616 Ctlr *ctlr;
1617
1618 for (ctlr = i82563ctlrhead; ctlr != nil && ctlr->edev != nil;
1619 ctlr = ctlr->next)
1620 i82563interrupt(nil, ctlr->edev);
1621 }
1622
1623 static int
i82563detach0(Ctlr * ctlr)1624 i82563detach0(Ctlr* ctlr)
1625 {
1626 int r, timeo;
1627
1628 /*
1629 * Perform a device reset to get the chip back to the
1630 * power-on state, followed by an EEPROM reset to read
1631 * the defaults for some internal registers.
1632 */
1633 csr32w(ctlr, Imc, ~0);
1634 csr32w(ctlr, Rctl, 0);
1635 csr32w(ctlr, Tctl, 0);
1636
1637 delay(10);
1638
1639 /*
1640 * Balance Rx/Tx packet buffer.
1641 * No need to set PBA register unless using jumbo, defaults to 32KB
1642 * for receive. If it is changed, then have to do a MAC reset,
1643 * and need to do that at the the right time as it will wipe stuff.
1644 */
1645 ctlr->pba = csr32r(ctlr, Pba);
1646
1647 /* set packet buffer size if present. no effect until soft reset. */
1648 switch (ctlr->type) {
1649 case i82566:
1650 case i82567:
1651 case i217:
1652 ctlr->pbs = 16; /* in KB */
1653 csr32w(ctlr, Pbs, ctlr->pbs);
1654 break;
1655 case i218:
1656 // after pxe or 9fat boot, pba is always 0xe0012 on i218 => 32K
1657 ctlr->pbs = (ctlr->pba >> 16) + (ushort)ctlr->pba;
1658 csr32w(ctlr, Pbs, ctlr->pbs);
1659 break;
1660 }
1661
1662 r = csr32r(ctlr, Ctrl);
1663 if(ctlr->type == i82566 || ctlr->type == i82567 || ctlr->type == i82579)
1664 r |= Phyrst;
1665 csr32w(ctlr, Ctrl, Devrst | r);
1666 delay(1);
1667 for(timeo = 0; timeo < 1000; timeo++){
1668 if(!(csr32r(ctlr, Ctrl) & Devrst))
1669 break;
1670 delay(1);
1671 }
1672 if(csr32r(ctlr, Ctrl) & Devrst)
1673 return -1;
1674
1675 r = csr32r(ctlr, Ctrlext);
1676 csr32w(ctlr, Ctrlext, r|Eerst);
1677 delay(1);
1678 for(timeo = 0; timeo < 1000; timeo++){
1679 if(!(csr32r(ctlr, Ctrlext) & Eerst))
1680 break;
1681 delay(1);
1682 }
1683 if(csr32r(ctlr, Ctrlext) & Eerst)
1684 return -1;
1685
1686 csr32w(ctlr, Imc, ~0);
1687 delay(1);
1688 for(timeo = 0; timeo < 1000; timeo++){
1689 if(!csr32r(ctlr, Icr))
1690 break;
1691 delay(1);
1692 }
1693 if(csr32r(ctlr, Icr))
1694 return -1;
1695
1696 csr32w(ctlr, Ctrl, Slu | csr32r(ctlr, Ctrl));
1697 return 0;
1698 }
1699
1700 static int
i82563detach(Ctlr * ctlr)1701 i82563detach(Ctlr* ctlr)
1702 {
1703 int r;
1704 static Lock detlck;
1705
1706 ilock(&detlck);
1707 r = i82563detach0(ctlr);
1708 iunlock(&detlck);
1709 return r;
1710 }
1711
1712 static void
i82563shutdown(Ether * ether)1713 i82563shutdown(Ether* ether)
1714 {
1715 i82563detach(ether->ctlr);
1716 }
1717
1718 static ushort
eeread(Ctlr * ctlr,int adr)1719 eeread(Ctlr *ctlr, int adr)
1720 {
1721 ulong n;
1722
1723 csr32w(ctlr, Eerd, EEstart | adr << 2);
1724 for (n = 1000000; (csr32r(ctlr, Eerd) & EEdone) == 0 && n-- > 0; )
1725 ;
1726 if (n == 0)
1727 panic("i82563: eeread stuck");
1728 return csr32r(ctlr, Eerd) >> 16;
1729 }
1730
1731 /* load eeprom into ctlr */
1732 static int
eeload(Ctlr * ctlr)1733 eeload(Ctlr *ctlr)
1734 {
1735 ushort sum;
1736 int data, adr;
1737
1738 sum = 0;
1739 for (adr = 0; adr < 0x40; adr++) {
1740 data = eeread(ctlr, adr);
1741 ctlr->eeprom[adr] = data;
1742 sum += data;
1743 }
1744 return sum;
1745 }
1746
1747 static int
fcycle(Ctlr *,Flash * f)1748 fcycle(Ctlr *, Flash *f)
1749 {
1750 ushort s, i;
1751
1752 s = f->reg[Fsts];
1753 if((s&Fvalid) == 0)
1754 return -1;
1755 f->reg[Fsts] |= Fcerr | Ael;
1756 for(i = 0; i < 10; i++){
1757 if((s&Scip) == 0) /* spi cycle done? */
1758 return 0;
1759 delay(1);
1760 s = f->reg[Fsts];
1761 }
1762 return -1;
1763 }
1764
1765 static int
fread(Ctlr * ctlr,Flash * f,int ladr)1766 fread(Ctlr *ctlr, Flash *f, int ladr)
1767 {
1768 ushort s;
1769 ulong n;
1770
1771 delay(1);
1772 if(fcycle(ctlr, f) == -1)
1773 return -1;
1774 f->reg[Fsts] |= Fdone;
1775 f->reg32[Faddr] = ladr;
1776
1777 /* setup flash control register */
1778 s = f->reg[Fctl] & ~(0x1f << 8);
1779 s |= (2-1) << 8; /* 2 bytes */
1780 s &= ~(2*Flcycle); /* read */
1781 f->reg[Fctl] = s | Fgo;
1782
1783 for (n = 1000000; (f->reg[Fsts] & Fdone) == 0 && n-- > 0; )
1784 ;
1785 if (n == 0)
1786 panic("i82563: fread stuck");
1787 if(f->reg[Fsts] & (Fcerr|Ael))
1788 return -1;
1789 return f->reg32[Fdata] & 0xffff;
1790 }
1791
1792 /* load flash into ctlr */
1793 static int
fload(Ctlr * ctlr)1794 fload(Ctlr *ctlr)
1795 {
1796 ulong data, io, r, adr;
1797 ushort sum;
1798 Flash f;
1799
1800 io = ctlr->pcidev->mem[1].bar & ~0x0f;
1801 f.reg = vmap(io, ctlr->pcidev->mem[1].size);
1802 if(f.reg == nil)
1803 return -1;
1804 f.reg32 = (void*)f.reg;
1805 f.base = f.reg32[Bfpr] & FMASK(0, 13);
1806 f.lim = (f.reg32[Bfpr]>>16) & FMASK(0, 13);
1807 if(csr32r(ctlr, Eec) & (1<<22))
1808 f.base += (f.lim + 1 - f.base) >> 1;
1809 r = f.base << 12;
1810
1811 sum = 0;
1812 for (adr = 0; adr < 0x40; adr++) {
1813 data = fread(ctlr, &f, r + adr*2);
1814 if(data == -1)
1815 break;
1816 ctlr->eeprom[adr] = data;
1817 sum += data;
1818 }
1819 vunmap(f.reg, ctlr->pcidev->mem[1].size);
1820 return sum;
1821 }
1822
1823 static int
i82563reset(Ctlr * ctlr)1824 i82563reset(Ctlr *ctlr)
1825 {
1826 int i, r, type;
1827
1828 if(i82563detach(ctlr)) {
1829 iprint("82563 reset: detach failed\n");
1830 return -1;
1831 }
1832 type = ctlr->type;
1833 if (ctlr->ra[Eaddrlen - 1] != 0)
1834 goto macset;
1835 switch (type) {
1836 case i82566:
1837 case i82567:
1838 case i82577:
1839 // case i82578: /* not yet implemented */
1840 case i82579:
1841 case i217:
1842 case i218:
1843 r = fload(ctlr);
1844 break;
1845 default:
1846 r = eeload(ctlr);
1847 break;
1848 }
1849 if (r != 0 && r != 0xBABA){
1850 print("%s: bad EEPROM checksum - %#.4ux\n",
1851 tname[type], r);
1852 return -1;
1853 }
1854
1855 /* set mac addr */
1856 for(i = 0; i < Eaddrlen/2; i++){
1857 ctlr->ra[2*i] = ctlr->eeprom[Ea+i];
1858 ctlr->ra[2*i+1] = ctlr->eeprom[Ea+i] >> 8;
1859 }
1860 /* ea ctlr[1] = ea ctlr[0]+1 */
1861 ctlr->ra[5] += (csr32r(ctlr, Status) & Lanid) >> 2;
1862 /*
1863 * zero other mac addresses.
1864 * AV bits should be zeroed by master reset & there may only be 11
1865 * other registers on e.g., the i217.
1866 */
1867 for(i = 1; i < 12; i++){ /* `12' used to be `16' here */
1868 csr32w(ctlr, Ral+i*8, 0);
1869 csr32w(ctlr, Rah+i*8, 0);
1870 }
1871 memset(ctlr->mta, 0, sizeof(ctlr->mta));
1872 macset:
1873 csr32w(ctlr, Ral, ctlr->ra[3]<<24 | ctlr->ra[2]<<16 | ctlr->ra[1]<<8 |
1874 ctlr->ra[0]); /* low mac addr */
1875 /* address valid | high mac addr */
1876 csr32w(ctlr, Rah, 0x80000000 | ctlr->ra[5]<<8 | ctlr->ra[4]);
1877
1878 /* populate multicast table */
1879 for(i = 0; i < mcbitstolongs(mcastbits(ctlr)); i++)
1880 csr32w(ctlr, Mta + i*4, ctlr->mta[i]);
1881
1882 /*
1883 * Does autonegotiation affect this manual setting?
1884 * The correct values here should depend on the PBA value
1885 * and maximum frame length, no?
1886 */
1887 /* fixed flow control ethernet address 0x0180c2000001 */
1888 csr32w(ctlr, Fcal, 0x00C28001);
1889 csr32w(ctlr, Fcah, 0x0100);
1890 if (type != i82579 && type != i210 && type != i217 && type != i218)
1891 /* flow control type, dictated by Intel */
1892 csr32w(ctlr, Fct, 0x8808);
1893 csr32w(ctlr, Fcttv, 0x0100); /* for XOFF frame */
1894 // ctlr->fcrtl = 0x00002000; /* rcv low water mark: 8KB */
1895 /* rcv high water mark: 16KB, < rcv buffer in PBA & RXA */
1896 // ctlr->fcrth = 0x00004000;
1897 ctlr->fcrtl = ctlr->fcrth = 0;
1898 csr32w(ctlr, Fcrtl, ctlr->fcrtl);
1899 csr32w(ctlr, Fcrth, ctlr->fcrth);
1900 return 0;
1901 }
1902
1903 static void
i82563pci(void)1904 i82563pci(void)
1905 {
1906 int type;
1907 ulong io;
1908 void *mem;
1909 Pcidev *p;
1910 Ctlr *ctlr;
1911
1912 p = nil;
1913 while(p = pcimatch(p, 0x8086, 0)){
1914 switch(p->did){
1915 default:
1916 continue;
1917 case 0x1096:
1918 case 0x10ba:
1919 type = i82563;
1920 break;
1921 case 0x1049: /* mm */
1922 case 0x104a: /* dm */
1923 case 0x104b: /* dc */
1924 case 0x104d: /* mc */
1925 case 0x10bd: /* dm */
1926 case 0x294c: /* dc-2 */
1927 type = i82566;
1928 break;
1929 case 0x10cd: /* lf */
1930 case 0x10ce: /* v-2 */
1931 case 0x10de: /* lm-3 */
1932 case 0x10f5: /* lm-2 */
1933 type = i82567;
1934 break;
1935 case 0x10a4:
1936 case 0x105e:
1937 type = i82571;
1938 break;
1939 case 0x107d: /* eb copper */
1940 case 0x107e: /* ei fiber */
1941 case 0x107f: /* ei */
1942 case 0x10b9: /* sic, 82572gi */
1943 type = i82572;
1944 break;
1945 case 0x108b: /* v */
1946 case 0x108c: /* e (iamt) */
1947 case 0x109a: /* l */
1948 type = i82573;
1949 break;
1950 case 0x10d3: /* l */
1951 type = i82574;
1952 break;
1953 case 0x10a7: /* 82575eb: one of a pair of controllers */
1954 type = i82575;
1955 break;
1956 case 0x10c9: /* 82576 copper */
1957 case 0x10e6: /* 82576 fiber */
1958 case 0x10e7: /* 82576 serdes */
1959 type = i82576;
1960 break;
1961 case 0x10ea: /* 82577lm */
1962 type = i82577;
1963 break;
1964 case 0x1502: /* 82579lm */
1965 case 0x1503: /* 82579v */
1966 type = i82579;
1967 break;
1968 case 0x1533: /* i210-t1 */
1969 case 0x1534: /* i210 */
1970 case 0x1536: /* i210-fiber */
1971 case 0x1537: /* i210-backplane */
1972 case 0x1538:
1973 case 0x1539: /* i211 */
1974 case 0x157b: /* i210 */
1975 case 0x157c: /* i210 */
1976 type = i210;
1977 break;
1978 case 0x153a: /* i217-lm */
1979 case 0x153b: /* i217-v */
1980 type = i217;
1981 break;
1982 case 0x15a3: /* i218 */
1983 type = i218;
1984 break;
1985 }
1986
1987 io = p->mem[0].bar & ~0x0F;
1988 mem = vmap(io, p->mem[0].size);
1989 if(mem == nil){
1990 print("%s: can't map %.8lux\n", tname[type], io);
1991 continue;
1992 }
1993 ctlr = malloc(sizeof(Ctlr));
1994 if(ctlr == nil) {
1995 vunmap(mem, p->mem[0].size);
1996 error(Enomem);
1997 }
1998 ctlr->port = io;
1999 ctlr->pcidev = p;
2000 ctlr->type = type;
2001 ctlr->nic = mem;
2002 ctlr->phynum = -1; /* not yet known */
2003
2004 if(i82563reset(ctlr)){
2005 vunmap(mem, p->mem[0].size);
2006 free(ctlr);
2007 continue;
2008 }
2009 pcisetbme(p);
2010
2011 if(i82563ctlrhead != nil)
2012 i82563ctlrtail->next = ctlr;
2013 else
2014 i82563ctlrhead = ctlr;
2015 i82563ctlrtail = ctlr;
2016 }
2017 }
2018
2019 static int
pnp(Ether * edev,int type)2020 pnp(Ether* edev, int type)
2021 {
2022 Ctlr *ctlr;
2023 static int done;
2024
2025 if(!done) {
2026 i82563pci();
2027 done = 1;
2028 }
2029
2030 /*
2031 * Any adapter matches if no edev->port is supplied,
2032 * otherwise the ports must match.
2033 */
2034 for(ctlr = i82563ctlrhead; ctlr != nil; ctlr = ctlr->next){
2035 if(ctlr->active)
2036 continue;
2037 if(type != Iany && ctlr->type != type)
2038 continue;
2039 if(edev->port == 0 || edev->port == ctlr->port){
2040 ctlr->active = 1;
2041 break;
2042 }
2043 }
2044 if(ctlr == nil)
2045 return -1;
2046
2047 edev->ctlr = ctlr;
2048 ctlr->edev = edev; /* point back to Ether* */
2049 edev->port = ctlr->port;
2050 edev->irq = ctlr->pcidev->intl;
2051 edev->tbdf = ctlr->pcidev->tbdf;
2052 edev->mbps = 1000;
2053 edev->maxmtu = ETHERMAXTU;
2054 memmove(edev->ea, ctlr->ra, Eaddrlen);
2055
2056 /*
2057 * Linkage to the generic ethernet driver.
2058 */
2059 edev->attach = i82563attach;
2060 edev->transmit = i82563transmit;
2061 edev->interrupt = (ctlr->type == i82575?
2062 i82575interrupt: i82563interrupt);
2063 edev->ifstat = i82563ifstat;
2064 edev->ctl = i82563ctl;
2065
2066 edev->arg = edev;
2067 edev->promiscuous = i82563promiscuous;
2068 edev->shutdown = i82563shutdown;
2069 edev->multicast = i82563multicast;
2070
2071 return 0;
2072 }
2073
2074 static int
anypnp(Ether * e)2075 anypnp(Ether *e)
2076 {
2077 return pnp(e, Iany);
2078 }
2079
2080 static int
i82563pnp(Ether * e)2081 i82563pnp(Ether *e)
2082 {
2083 return pnp(e, i82563);
2084 }
2085
2086 static int
i82566pnp(Ether * e)2087 i82566pnp(Ether *e)
2088 {
2089 return pnp(e, i82566);
2090 }
2091
2092 static int
i82571pnp(Ether * e)2093 i82571pnp(Ether *e)
2094 {
2095 return pnp(e, i82571);
2096 }
2097
2098 static int
i82572pnp(Ether * e)2099 i82572pnp(Ether *e)
2100 {
2101 return pnp(e, i82572);
2102 }
2103
2104 static int
i82573pnp(Ether * e)2105 i82573pnp(Ether *e)
2106 {
2107 return pnp(e, i82573);
2108 }
2109
2110 static int
i82575pnp(Ether * e)2111 i82575pnp(Ether *e)
2112 {
2113 return pnp(e, i82575);
2114 }
2115
2116 static int
i82579pnp(Ether * e)2117 i82579pnp(Ether *e)
2118 {
2119 return pnp(e, i82579);
2120 }
2121
2122 static int
i210pnp(Ether * e)2123 i210pnp(Ether *e)
2124 {
2125 return pnp(e, i210);
2126 }
2127
2128 static int
i217pnp(Ether * e)2129 i217pnp(Ether *e)
2130 {
2131 return pnp(e, i217);
2132 }
2133
2134 static int
i218pnp(Ether * e)2135 i218pnp(Ether *e)
2136 {
2137 return pnp(e, i218);
2138 }
2139
2140 void
ether82563link(void)2141 ether82563link(void)
2142 {
2143 /* recognise lots of model numbers for debugging assistance */
2144 addethercard("i82563", i82563pnp);
2145 addethercard("i82566", i82566pnp);
2146 addethercard("i82571", i82571pnp);
2147 addethercard("i82572", i82572pnp);
2148 addethercard("i82573", i82573pnp);
2149 addethercard("i82575", i82575pnp);
2150 addethercard("i82579", i82579pnp);
2151 addethercard("i210", i210pnp);
2152 addethercard("i217", i217pnp);
2153 addethercard("i218", i218pnp);
2154 addethercard("igbepcie", anypnp);
2155 }
2156