1 /*
2 * Digital Semiconductor DECchip 2114x PCI Fast Ethernet LAN Controller.
3 * To do:
4 * thresholds;
5 * ring sizing;
6 * handle more error conditions;
7 * tidy setup packet mess;
8 * push initialisation back to attach;
9 * full SROM decoding.
10 */
11 #include "u.h"
12 #include "../port/lib.h"
13 #include "mem.h"
14 #include "dat.h"
15 #include "fns.h"
16 #include "io.h"
17 #include "../port/error.h"
18 #include "../port/netif.h"
19
20 #include "etherif.h"
21
22 #define DEBUG (0)
23 #define debug if(DEBUG)print
24
25 enum {
26 Nrde = 64,
27 Ntde = 64,
28 };
29
30 #define Rbsz ROUNDUP(sizeof(Etherpkt)+4, 4)
31
32 enum { /* CRS0 - Bus Mode */
33 Swr = 0x00000001, /* Software Reset */
34 Bar = 0x00000002, /* Bus Arbitration */
35 Dsl = 0x0000007C, /* Descriptor Skip Length (field) */
36 Ble = 0x00000080, /* Big/Little Endian */
37 Pbl = 0x00003F00, /* Programmable Burst Length (field) */
38 Cal = 0x0000C000, /* Cache Alignment (field) */
39 Cal8 = 0x00004000, /* 8 longword boundary alignment */
40 Cal16 = 0x00008000, /* 16 longword boundary alignment */
41 Cal32 = 0x0000C000, /* 32 longword boundary alignment */
42 Tap = 0x000E0000, /* Transmit Automatic Polling (field) */
43 Dbo = 0x00100000, /* Descriptor Byte Ordering Mode */
44 Rml = 0x00200000, /* Read Multiple */
45 };
46
47 enum { /* CSR[57] - Status and Interrupt Enable */
48 Ti = 0x00000001, /* Transmit Interrupt */
49 Tps = 0x00000002, /* Transmit Process Stopped */
50 Tu = 0x00000004, /* Transmit buffer Unavailable */
51 Tjt = 0x00000008, /* Transmit Jabber Timeout */
52 Unf = 0x00000020, /* transmit UNderFlow */
53 Ri = 0x00000040, /* Receive Interrupt */
54 Ru = 0x00000080, /* Receive buffer Unavailable */
55 Rps = 0x00000100, /* Receive Process Stopped */
56 Rwt = 0x00000200, /* Receive Watchdog Timeout */
57 Eti = 0x00000400, /* Early Transmit Interrupt */
58 Gte = 0x00000800, /* General purpose Timer Expired */
59 Fbe = 0x00002000, /* Fatal Bit Error */
60 Ais = 0x00008000, /* Abnormal Interrupt Summary */
61 Nis = 0x00010000, /* Normal Interrupt Summary */
62 Rs = 0x000E0000, /* Receive process State (field) */
63 Ts = 0x00700000, /* Transmit process State (field) */
64 Eb = 0x03800000, /* Error bits */
65 };
66
67 enum { /* CSR6 - Operating Mode */
68 Hp = 0x00000001, /* Hash/Perfect receive filtering mode */
69 Sr = 0x00000002, /* Start/stop Receive */
70 Ho = 0x00000004, /* Hash-Only filtering mode */
71 Pb = 0x00000008, /* Pass Bad frames */
72 If = 0x00000010, /* Inverse Filtering */
73 Sb = 0x00000020, /* Start/stop Backoff counter */
74 Pr = 0x00000040, /* Promiscuous Mode */
75 Pm = 0x00000080, /* Pass all Multicast */
76 Fd = 0x00000200, /* Full Duplex mode */
77 Om = 0x00000C00, /* Operating Mode (field) */
78 Fc = 0x00001000, /* Force Collision */
79 St = 0x00002000, /* Start/stop Transmission Command */
80 Tr = 0x0000C000, /* ThReshold control bits (field) */
81 Tr128 = 0x00000000,
82 Tr256 = 0x00004000,
83 Tr512 = 0x00008000,
84 Tr1024 = 0x0000C000,
85 Ca = 0x00020000, /* CApture effect enable */
86 Ps = 0x00040000, /* Port Select */
87 Hbd = 0x00080000, /* HeartBeat Disable */
88 Imm = 0x00100000, /* IMMediate mode */
89 Sf = 0x00200000, /* Store and Forward */
90 Ttm = 0x00400000, /* Transmit Threshold Mode */
91 Pcs = 0x00800000, /* PCS function */
92 Scr = 0x01000000, /* SCRambler mode */
93 Mbo = 0x02000000, /* Must Be One */
94 Ra = 0x40000000, /* Receive All */
95 Sc = 0x80000000, /* Special Capture effect enable */
96
97 TrMODE = Tr512, /* default transmission threshold */
98 };
99
100 enum { /* CSR9 - ROM and MII Management */
101 Scs = 0x00000001, /* serial ROM chip select */
102 Sclk = 0x00000002, /* serial ROM clock */
103 Sdi = 0x00000004, /* serial ROM data in */
104 Sdo = 0x00000008, /* serial ROM data out */
105 Ss = 0x00000800, /* serial ROM select */
106 Wr = 0x00002000, /* write */
107 Rd = 0x00004000, /* read */
108
109 Mdc = 0x00010000, /* MII management clock */
110 Mdo = 0x00020000, /* MII management write data */
111 Mii = 0x00040000, /* MII management operation mode (W) */
112 Mdi = 0x00080000, /* MII management data in */
113 };
114
115 enum { /* CSR12 - General-Purpose Port */
116 Gpc = 0x00000100, /* General Purpose Control */
117 };
118
119 typedef struct Des {
120 int status;
121 int control;
122 ulong addr;
123 Block* bp;
124 } Des;
125
126 enum { /* status */
127 Of = 0x00000001, /* Rx: OverFlow */
128 Ce = 0x00000002, /* Rx: CRC Error */
129 Db = 0x00000004, /* Rx: Dribbling Bit */
130 Re = 0x00000008, /* Rx: Report on MII Error */
131 Rw = 0x00000010, /* Rx: Receive Watchdog */
132 Ft = 0x00000020, /* Rx: Frame Type */
133 Cs = 0x00000040, /* Rx: Collision Seen */
134 Tl = 0x00000080, /* Rx: Frame too Long */
135 Ls = 0x00000100, /* Rx: Last deScriptor */
136 Fs = 0x00000200, /* Rx: First deScriptor */
137 Mf = 0x00000400, /* Rx: Multicast Frame */
138 Rf = 0x00000800, /* Rx: Runt Frame */
139 Dt = 0x00003000, /* Rx: Data Type (field) */
140 De = 0x00004000, /* Rx: Descriptor Error */
141 Fl = 0x3FFF0000, /* Rx: Frame Length (field) */
142 Ff = 0x40000000, /* Rx: Filtering Fail */
143
144 Def = 0x00000001, /* Tx: DEFerred */
145 Uf = 0x00000002, /* Tx: UnderFlow error */
146 Lf = 0x00000004, /* Tx: Link Fail report */
147 Cc = 0x00000078, /* Tx: Collision Count (field) */
148 Hf = 0x00000080, /* Tx: Heartbeat Fail */
149 Ec = 0x00000100, /* Tx: Excessive Collisions */
150 Lc = 0x00000200, /* Tx: Late Collision */
151 Nc = 0x00000400, /* Tx: No Carrier */
152 Lo = 0x00000800, /* Tx: LOss of carrier */
153 To = 0x00004000, /* Tx: Transmission jabber timeOut */
154
155 Es = 0x00008000, /* [RT]x: Error Summary */
156 Own = 0x80000000, /* [RT]x: OWN bit */
157 };
158
159 enum { /* control */
160 Bs1 = 0x000007FF, /* [RT]x: Buffer 1 Size */
161 Bs2 = 0x003FF800, /* [RT]x: Buffer 2 Size */
162
163 Ch = 0x01000000, /* [RT]x: second address CHained */
164 Er = 0x02000000, /* [RT]x: End of Ring */
165
166 Ft0 = 0x00400000, /* Tx: Filtering Type 0 */
167 Dpd = 0x00800000, /* Tx: Disabled PaDding */
168 Ac = 0x04000000, /* Tx: Add CRC disable */
169 Set = 0x08000000, /* Tx: SETup packet */
170 Ft1 = 0x10000000, /* Tx: Filtering Type 1 */
171 Fseg = 0x20000000, /* Tx: First SEGment */
172 Lseg = 0x40000000, /* Tx: Last SEGment */
173 Ic = 0x80000000, /* Tx: Interrupt on Completion */
174 };
175
176 enum { /* PHY registers */
177 Bmcr = 0, /* Basic Mode Control */
178 Bmsr = 1, /* Basic Mode Status */
179 Phyidr1 = 2, /* PHY Identifier #1 */
180 Phyidr2 = 3, /* PHY Identifier #2 */
181 Anar = 4, /* Auto-Negotiation Advertisment */
182 Anlpar = 5, /* Auto-Negotiation Link Partner Ability */
183 Aner = 6, /* Auto-Negotiation Expansion */
184 };
185
186 enum { /* Variants */
187 Tulip0 = (0x0009<<16)|0x1011,
188 Tulip1 = (0x0014<<16)|0x1011,
189 Tulip3 = (0x0019<<16)|0x1011,
190 Pnic = (0x0002<<16)|0x11AD,
191 Pnic2 = (0xC115<<16)|0x11AD,
192 CentaurP = (0x0985<<16)|0x1317,
193 CentaurPcb = (0x1985<<16)|0x1317,
194 };
195
196 typedef struct Ctlr Ctlr;
197 typedef struct Ctlr {
198 int port;
199 Pcidev* pcidev;
200 Ctlr* next;
201 int active;
202 int id; /* (pcidev->did<<16)|pcidev->vid */
203
204 uchar* srom;
205 int sromsz; /* address size in bits */
206 uchar* sromea; /* MAC address */
207 uchar* leaf;
208 int sct; /* selected connection type */
209 int k; /* info block count */
210 uchar* infoblock[16];
211 int sctk; /* sct block index */
212 int curk; /* current block index */
213 uchar* type5block;
214
215 int phy[32]; /* logical to physical map */
216 int phyreset; /* reset bitmap */
217 int curphyad;
218 int fdx;
219 int ttm;
220
221 uchar fd; /* option */
222 int medium; /* option */
223
224 int csr6; /* CSR6 - operating mode */
225 int mask; /* CSR[57] - interrupt mask */
226 int mbps;
227
228 Lock lock;
229
230 Des* rdr; /* receive descriptor ring */
231 int nrdr; /* size of rdr */
232 int rdrx; /* index into rdr */
233
234 Lock tlock;
235 Des* tdr; /* transmit descriptor ring */
236 int ntdr; /* size of tdr */
237 int tdrh; /* host index into tdr */
238 int tdri; /* interface index into tdr */
239 int ntq; /* descriptors active */
240 int ntqmax;
241 Block* setupbp;
242
243 ulong of; /* receive statistics */
244 ulong ce;
245 ulong cs;
246 ulong tl;
247 ulong rf;
248 ulong de;
249
250 ulong ru;
251 ulong rps;
252 ulong rwt;
253
254 ulong uf; /* transmit statistics */
255 ulong ec;
256 ulong lc;
257 ulong nc;
258 ulong lo;
259 ulong to;
260
261 ulong tps;
262 ulong tu;
263 ulong tjt;
264 ulong unf;
265 } Ctlr;
266
267 static Ctlr* ctlrhead;
268 static Ctlr* ctlrtail;
269
270 #define csr32r(c, r) (inl((c)->port+((r)*8)))
271 #define csr32w(c, r, l) (outl((c)->port+((r)*8), (ulong)(l)))
272
273 static void
promiscuous(void * arg,int on)274 promiscuous(void* arg, int on)
275 {
276 Ctlr *ctlr;
277
278 ctlr = ((Ether*)arg)->ctlr;
279 ilock(&ctlr->lock);
280 if(on)
281 ctlr->csr6 |= Pr;
282 else
283 ctlr->csr6 &= ~Pr;
284 csr32w(ctlr, 6, ctlr->csr6);
285 iunlock(&ctlr->lock);
286 }
287
288 /* multicast already on, don't need to do anything */
289 static void
multicast(void *,uchar *,int)290 multicast(void*, uchar*, int)
291 {
292 }
293
294 static void
attach(Ether * ether)295 attach(Ether* ether)
296 {
297 Ctlr *ctlr;
298
299 ctlr = ether->ctlr;
300 ilock(&ctlr->lock);
301 if(!(ctlr->csr6 & Sr)){
302 ctlr->csr6 |= Sr;
303 csr32w(ctlr, 6, ctlr->csr6);
304 }
305 iunlock(&ctlr->lock);
306 }
307
308 static long
ifstat(Ether * ether,void * a,long n,ulong offset)309 ifstat(Ether* ether, void* a, long n, ulong offset)
310 {
311 Ctlr *ctlr;
312 char *buf, *p;
313 int i, l, len;
314
315 ctlr = ether->ctlr;
316
317 ether->crcs = ctlr->ce;
318 ether->frames = ctlr->rf+ctlr->cs;
319 ether->buffs = ctlr->de+ctlr->tl;
320 ether->overflows = ctlr->of;
321
322 if(n == 0)
323 return 0;
324
325 p = malloc(READSTR);
326 if(p == nil)
327 error(Enomem);
328 l = snprint(p, READSTR, "Overflow: %lud\n", ctlr->of);
329 l += snprint(p+l, READSTR-l, "Ru: %lud\n", ctlr->ru);
330 l += snprint(p+l, READSTR-l, "Rps: %lud\n", ctlr->rps);
331 l += snprint(p+l, READSTR-l, "Rwt: %lud\n", ctlr->rwt);
332 l += snprint(p+l, READSTR-l, "Tps: %lud\n", ctlr->tps);
333 l += snprint(p+l, READSTR-l, "Tu: %lud\n", ctlr->tu);
334 l += snprint(p+l, READSTR-l, "Tjt: %lud\n", ctlr->tjt);
335 l += snprint(p+l, READSTR-l, "Unf: %lud\n", ctlr->unf);
336 l += snprint(p+l, READSTR-l, "CRC Error: %lud\n", ctlr->ce);
337 l += snprint(p+l, READSTR-l, "Collision Seen: %lud\n", ctlr->cs);
338 l += snprint(p+l, READSTR-l, "Frame Too Long: %lud\n", ctlr->tl);
339 l += snprint(p+l, READSTR-l, "Runt Frame: %lud\n", ctlr->rf);
340 l += snprint(p+l, READSTR-l, "Descriptor Error: %lud\n", ctlr->de);
341 l += snprint(p+l, READSTR-l, "Underflow Error: %lud\n", ctlr->uf);
342 l += snprint(p+l, READSTR-l, "Excessive Collisions: %lud\n", ctlr->ec);
343 l += snprint(p+l, READSTR-l, "Late Collision: %lud\n", ctlr->lc);
344 l += snprint(p+l, READSTR-l, "No Carrier: %lud\n", ctlr->nc);
345 l += snprint(p+l, READSTR-l, "Loss of Carrier: %lud\n", ctlr->lo);
346 l += snprint(p+l, READSTR-l, "Transmit Jabber Timeout: %lud\n",
347 ctlr->to);
348 l += snprint(p+l, READSTR-l, "csr6: %luX %uX\n", csr32r(ctlr, 6),
349 ctlr->csr6);
350 snprint(p+l, READSTR-l, "ntqmax: %d\n", ctlr->ntqmax);
351 ctlr->ntqmax = 0;
352 buf = a;
353 len = readstr(offset, buf, n, p);
354 if(offset > l)
355 offset -= l;
356 else
357 offset = 0;
358 buf += len;
359 n -= len;
360
361 l = snprint(p, READSTR, "srom:");
362 for(i = 0; i < (1<<(ctlr->sromsz)*sizeof(ushort)); i++){
363 if(i && ((i & 0x0F) == 0))
364 l += snprint(p+l, READSTR-l, "\n ");
365 l += snprint(p+l, READSTR-l, " %2.2uX", ctlr->srom[i]);
366 }
367
368 snprint(p+l, READSTR-l, "\n");
369 len += readstr(offset, buf, n, p);
370 free(p);
371
372 return len;
373 }
374
375 static void
txstart(Ether * ether)376 txstart(Ether* ether)
377 {
378 Ctlr *ctlr;
379 Block *bp;
380 Des *des;
381 int control;
382
383 ctlr = ether->ctlr;
384 while(ctlr->ntq < (ctlr->ntdr-1)){
385 if(ctlr->setupbp){
386 bp = ctlr->setupbp;
387 ctlr->setupbp = 0;
388 control = Ic|Set|BLEN(bp);
389 }
390 else{
391 bp = qget(ether->oq);
392 if(bp == nil)
393 break;
394 control = Ic|Lseg|Fseg|BLEN(bp);
395 }
396
397 ctlr->tdr[PREV(ctlr->tdrh, ctlr->ntdr)].control &= ~Ic;
398 des = &ctlr->tdr[ctlr->tdrh];
399 des->bp = bp;
400 des->addr = PCIWADDR(bp->rp);
401 des->control |= control;
402 ctlr->ntq++;
403 coherence();
404 des->status = Own;
405 csr32w(ctlr, 1, 0);
406 ctlr->tdrh = NEXT(ctlr->tdrh, ctlr->ntdr);
407 }
408
409 if(ctlr->ntq > ctlr->ntqmax)
410 ctlr->ntqmax = ctlr->ntq;
411 }
412
413 static void
transmit(Ether * ether)414 transmit(Ether* ether)
415 {
416 Ctlr *ctlr;
417
418 ctlr = ether->ctlr;
419 ilock(&ctlr->tlock);
420 txstart(ether);
421 iunlock(&ctlr->tlock);
422 }
423
424 static void
interrupt(Ureg *,void * arg)425 interrupt(Ureg*, void* arg)
426 {
427 Ctlr *ctlr;
428 Ether *ether;
429 int len, status;
430 Des *des;
431 Block *bp;
432
433 ether = arg;
434 ctlr = ether->ctlr;
435
436 while((status = csr32r(ctlr, 5)) & (Nis|Ais)){
437 /*
438 * Acknowledge the interrupts and mask-out
439 * the ones that are implicitly handled.
440 */
441 csr32w(ctlr, 5, status);
442 status &= (ctlr->mask & ~(Nis|Ti));
443
444 if(status & Ais){
445 if(status & Tps)
446 ctlr->tps++;
447 if(status & Tu)
448 ctlr->tu++;
449 if(status & Tjt)
450 ctlr->tjt++;
451 if(status & Ru)
452 ctlr->ru++;
453 if(status & Rps)
454 ctlr->rps++;
455 if(status & Rwt)
456 ctlr->rwt++;
457 status &= ~(Ais|Rwt|Rps|Ru|Tjt|Tu|Tps);
458 }
459
460 /*
461 * Received packets.
462 */
463 if(status & Ri){
464 des = &ctlr->rdr[ctlr->rdrx];
465 while(!(des->status & Own)){
466 if(des->status & Es){
467 if(des->status & Of)
468 ctlr->of++;
469 if(des->status & Ce)
470 ctlr->ce++;
471 if(des->status & Cs)
472 ctlr->cs++;
473 if(des->status & Tl)
474 ctlr->tl++;
475 if(des->status & Rf)
476 ctlr->rf++;
477 if(des->status & De)
478 ctlr->de++;
479 }
480 else if(bp = iallocb(Rbsz)){
481 len = ((des->status & Fl)>>16)-4;
482 des->bp->wp = des->bp->rp+len;
483 etheriq(ether, des->bp, 1);
484 des->bp = bp;
485 des->addr = PCIWADDR(bp->rp);
486 }
487
488 des->control &= Er;
489 des->control |= Rbsz;
490 coherence();
491 des->status = Own;
492
493 ctlr->rdrx = NEXT(ctlr->rdrx, ctlr->nrdr);
494 des = &ctlr->rdr[ctlr->rdrx];
495 }
496 status &= ~Ri;
497 }
498
499 /*
500 * Check the transmit side:
501 * check for Transmit Underflow and Adjust
502 * the threshold upwards;
503 * free any transmitted buffers and try to
504 * top-up the ring.
505 */
506 if(status & Unf){
507 ctlr->unf++;
508 ilock(&ctlr->lock);
509 csr32w(ctlr, 6, ctlr->csr6 & ~St);
510 switch(ctlr->csr6 & Tr){
511 case Tr128:
512 len = Tr256;
513 break;
514 case Tr256:
515 len = Tr512;
516 break;
517 case Tr512:
518 len = Tr1024;
519 break;
520 default:
521 case Tr1024:
522 len = Sf;
523 break;
524 }
525 ctlr->csr6 = (ctlr->csr6 & ~Tr)|len;
526 csr32w(ctlr, 6, ctlr->csr6);
527 iunlock(&ctlr->lock);
528 csr32w(ctlr, 5, Tps);
529 status &= ~(Unf|Tps);
530 }
531
532 ilock(&ctlr->tlock);
533 while(ctlr->ntq){
534 des = &ctlr->tdr[ctlr->tdri];
535 if(des->status & Own)
536 break;
537
538 if(des->status & Es){
539 if(des->status & Uf)
540 ctlr->uf++;
541 if(des->status & Ec)
542 ctlr->ec++;
543 if(des->status & Lc)
544 ctlr->lc++;
545 if(des->status & Nc)
546 ctlr->nc++;
547 if(des->status & Lo)
548 ctlr->lo++;
549 if(des->status & To)
550 ctlr->to++;
551 ether->oerrs++;
552 }
553
554 freeb(des->bp);
555 des->control &= Er;
556
557 ctlr->ntq--;
558 ctlr->tdri = NEXT(ctlr->tdri, ctlr->ntdr);
559 }
560 txstart(ether);
561 iunlock(&ctlr->tlock);
562
563 /*
564 * Anything left not catered for?
565 */
566 if(status)
567 panic("#l%d: status %8.8uX\n", ether->ctlrno, status);
568 }
569 }
570
571 static void
ctlrinit(Ether * ether)572 ctlrinit(Ether* ether)
573 {
574 Ctlr *ctlr;
575 Des *des;
576 Block *bp;
577 int i;
578 uchar bi[Eaddrlen*2];
579
580 ctlr = ether->ctlr;
581
582 /*
583 * Allocate and initialise the receive ring;
584 * allocate and initialise the transmit ring;
585 * unmask interrupts and start the transmit side;
586 * create and post a setup packet to initialise
587 * the physical ethernet address.
588 */
589 ctlr->rdr = xspanalloc(ctlr->nrdr*sizeof(Des), 8*sizeof(ulong), 0);
590 for(des = ctlr->rdr; des < &ctlr->rdr[ctlr->nrdr]; des++){
591 des->bp = iallocb(Rbsz);
592 if(des->bp == nil)
593 panic("can't allocate ethernet receive ring\n");
594 des->status = Own;
595 des->control = Rbsz;
596 des->addr = PCIWADDR(des->bp->rp);
597 }
598 ctlr->rdr[ctlr->nrdr-1].control |= Er;
599 ctlr->rdrx = 0;
600 csr32w(ctlr, 3, PCIWADDR(ctlr->rdr));
601
602 ctlr->tdr = xspanalloc(ctlr->ntdr*sizeof(Des), 8*sizeof(ulong), 0);
603 ctlr->tdr[ctlr->ntdr-1].control |= Er;
604 ctlr->tdrh = 0;
605 ctlr->tdri = 0;
606 csr32w(ctlr, 4, PCIWADDR(ctlr->tdr));
607
608 /*
609 * Clear any bits in the Status Register (CSR5) as
610 * the PNIC has a different reset value from a true 2114x.
611 */
612 ctlr->mask = Nis|Ais|Fbe|Rwt|Rps|Ru|Ri|Unf|Tjt|Tps|Ti;
613 csr32w(ctlr, 5, ctlr->mask);
614 csr32w(ctlr, 7, ctlr->mask);
615 ctlr->csr6 |= St|Pm;
616 csr32w(ctlr, 6, ctlr->csr6);
617
618 for(i = 0; i < Eaddrlen/2; i++){
619 bi[i*4] = ether->ea[i*2];
620 bi[i*4+1] = ether->ea[i*2+1];
621 bi[i*4+2] = ether->ea[i*2+1];
622 bi[i*4+3] = ether->ea[i*2];
623 }
624 bp = iallocb(Eaddrlen*2*16);
625 if(bp == nil)
626 panic("can't allocate ethernet setup buffer\n");
627 memset(bp->rp, 0xFF, sizeof(bi));
628 for(i = sizeof(bi); i < sizeof(bi)*16; i += sizeof(bi))
629 memmove(bp->rp+i, bi, sizeof(bi));
630 bp->wp += sizeof(bi)*16;
631
632 ctlr->setupbp = bp;
633 ether->oq = qopen(64*1024, Qmsg, 0, 0);
634 transmit(ether);
635 }
636
637 static void
csr9w(Ctlr * ctlr,int data)638 csr9w(Ctlr* ctlr, int data)
639 {
640 csr32w(ctlr, 9, data);
641 microdelay(1);
642 }
643
644 static int
miimdi(Ctlr * ctlr,int n)645 miimdi(Ctlr* ctlr, int n)
646 {
647 int data, i;
648
649 /*
650 * Read n bits from the MII Management Register.
651 */
652 data = 0;
653 for(i = n-1; i >= 0; i--){
654 if(csr32r(ctlr, 9) & Mdi)
655 data |= (1<<i);
656 csr9w(ctlr, Mii|Mdc);
657 csr9w(ctlr, Mii);
658 }
659 csr9w(ctlr, 0);
660
661 return data;
662 }
663
664 static void
miimdo(Ctlr * ctlr,int bits,int n)665 miimdo(Ctlr* ctlr, int bits, int n)
666 {
667 int i, mdo;
668
669 /*
670 * Write n bits to the MII Management Register.
671 */
672 for(i = n-1; i >= 0; i--){
673 if(bits & (1<<i))
674 mdo = Mdo;
675 else
676 mdo = 0;
677 csr9w(ctlr, mdo);
678 csr9w(ctlr, mdo|Mdc);
679 csr9w(ctlr, mdo);
680 }
681 }
682
683 static int
miir(Ctlr * ctlr,int phyad,int regad)684 miir(Ctlr* ctlr, int phyad, int regad)
685 {
686 int data, i;
687
688 if(ctlr->id == Pnic){
689 i = 1000;
690 csr32w(ctlr, 20, 0x60020000|(phyad<<23)|(regad<<18));
691 do{
692 microdelay(1);
693 data = csr32r(ctlr, 20);
694 }while((data & 0x80000000) && --i);
695
696 if(i == 0)
697 return -1;
698 return data & 0xFFFF;
699 }
700
701 /*
702 * Preamble;
703 * ST+OP+PHYAD+REGAD;
704 * TA + 16 data bits.
705 */
706 miimdo(ctlr, 0xFFFFFFFF, 32);
707 miimdo(ctlr, 0x1800|(phyad<<5)|regad, 14);
708 data = miimdi(ctlr, 18);
709
710 if(data & 0x10000)
711 return -1;
712
713 return data & 0xFFFF;
714 }
715
716 static void
miiw(Ctlr * ctlr,int phyad,int regad,int data)717 miiw(Ctlr* ctlr, int phyad, int regad, int data)
718 {
719 /*
720 * Preamble;
721 * ST+OP+PHYAD+REGAD+TA + 16 data bits;
722 * Z.
723 */
724 miimdo(ctlr, 0xFFFFFFFF, 32);
725 data &= 0xFFFF;
726 data |= (0x05<<(5+5+2+16))|(phyad<<(5+2+16))|(regad<<(2+16))|(0x02<<16);
727 miimdo(ctlr, data, 32);
728 csr9w(ctlr, Mdc);
729 csr9w(ctlr, 0);
730 }
731
732 static int
sromr(Ctlr * ctlr,int r)733 sromr(Ctlr* ctlr, int r)
734 {
735 int i, op, data, size;
736
737 if(ctlr->id == Pnic){
738 i = 1000;
739 csr32w(ctlr, 19, 0x600|r);
740 do{
741 microdelay(1);
742 data = csr32r(ctlr, 19);
743 }while((data & 0x80000000) && --i);
744
745 if(ctlr->sromsz == 0)
746 ctlr->sromsz = 6;
747
748 return csr32r(ctlr, 9) & 0xFFFF;
749 }
750
751 /*
752 * This sequence for reading a 16-bit register 'r'
753 * in the EEPROM is taken (pretty much) straight from Section
754 * 7.4 of the 21140 Hardware Reference Manual.
755 */
756 reread:
757 csr9w(ctlr, Rd|Ss);
758 csr9w(ctlr, Rd|Ss|Scs);
759 csr9w(ctlr, Rd|Ss|Sclk|Scs);
760 csr9w(ctlr, Rd|Ss);
761
762 op = 0x06;
763 for(i = 3-1; i >= 0; i--){
764 data = Rd|Ss|(((op>>i) & 0x01)<<2)|Scs;
765 csr9w(ctlr, data);
766 csr9w(ctlr, data|Sclk);
767 csr9w(ctlr, data);
768 }
769
770 /*
771 * First time through must work out the EEPROM size.
772 * This doesn't seem to work on the 21041 as implemented
773 * in Virtual PC for the Mac, so wire any 21041 to 6,
774 * it's the only 21041 this code will ever likely see.
775 */
776 if((size = ctlr->sromsz) == 0){
777 if(ctlr->id == Tulip1)
778 ctlr->sromsz = size = 6;
779 else
780 size = 8;
781 }
782
783 for(size = size-1; size >= 0; size--){
784 data = Rd|Ss|(((r>>size) & 0x01)<<2)|Scs;
785 csr9w(ctlr, data);
786 csr9w(ctlr, data|Sclk);
787 csr9w(ctlr, data);
788 microdelay(1);
789 if(ctlr->sromsz == 0 && !(csr32r(ctlr, 9) & Sdo))
790 break;
791 }
792
793 data = 0;
794 for(i = 16-1; i >= 0; i--){
795 csr9w(ctlr, Rd|Ss|Sclk|Scs);
796 if(csr32r(ctlr, 9) & Sdo)
797 data |= (1<<i);
798 csr9w(ctlr, Rd|Ss|Scs);
799 }
800
801 csr9w(ctlr, 0);
802
803 if(ctlr->sromsz == 0){
804 ctlr->sromsz = 8-size;
805 goto reread;
806 }
807
808 return data & 0xFFFF;
809 }
810
811 static void
shutdown(Ether * ether)812 shutdown(Ether* ether)
813 {
814 Ctlr *ctlr = ether->ctlr;
815
816 print("ether2114x shutting down\n");
817 csr32w(ctlr, 0, Swr);
818 }
819
820 static void
softreset(Ctlr * ctlr)821 softreset(Ctlr* ctlr)
822 {
823 /*
824 * Soft-reset the controller and initialise bus mode.
825 * Delay should be >= 50 PCI cycles (2×S @ 25MHz).
826 */
827 csr32w(ctlr, 0, Swr);
828 microdelay(10);
829 csr32w(ctlr, 0, Rml|Cal16);
830 delay(1);
831 }
832
833 static int
type5block(Ctlr * ctlr,uchar * block)834 type5block(Ctlr* ctlr, uchar* block)
835 {
836 int csr15, i, len;
837
838 /*
839 * Reset or GPR sequence. Reset should be once only,
840 * before the GPR sequence.
841 * Note 'block' is not a pointer to the block head but
842 * a pointer to the data in the block starting at the
843 * reset length value so type5block can be used for the
844 * sequences contained in type 1 and type 3 blocks.
845 * The SROM docs state the 21140 type 5 block is the
846 * same as that for the 21143, but the two controllers
847 * use different registers and sequence-element lengths
848 * so the 21140 code here is a guess for a real type 5
849 * sequence.
850 */
851 len = *block++;
852 if(ctlr->id != Tulip3){
853 for(i = 0; i < len; i++){
854 csr32w(ctlr, 12, *block);
855 block++;
856 }
857 return len;
858 }
859
860 for(i = 0; i < len; i++){
861 csr15 = *block++<<16;
862 csr15 |= *block++<<24;
863 csr32w(ctlr, 15, csr15);
864 debug("%8.8uX ", csr15);
865 }
866 return 2*len;
867 }
868
869 static int
typephylink(Ctlr * ctlr,uchar *)870 typephylink(Ctlr* ctlr, uchar*)
871 {
872 int an, bmcr, bmsr, csr6, x;
873
874 /*
875 * Fail if
876 * auto-negotiataion enabled but not complete;
877 * no valid link established.
878 */
879 bmcr = miir(ctlr, ctlr->curphyad, Bmcr);
880 miir(ctlr, ctlr->curphyad, Bmsr);
881 bmsr = miir(ctlr, ctlr->curphyad, Bmsr);
882 debug("bmcr 0x%2.2uX bmsr 0x%2.2uX\n", bmcr, bmsr);
883 if(((bmcr & 0x1000) && !(bmsr & 0x0020)) || !(bmsr & 0x0004))
884 return 0;
885
886 if(bmcr & 0x1000){
887 an = miir(ctlr, ctlr->curphyad, Anar);
888 an &= miir(ctlr, ctlr->curphyad, Anlpar) & 0x3E0;
889 debug("an 0x%2.uX 0x%2.2uX 0x%2.2uX\n",
890 miir(ctlr, ctlr->curphyad, Anar),
891 miir(ctlr, ctlr->curphyad, Anlpar),
892 an);
893
894 if(an & 0x0100)
895 x = 0x4000;
896 else if(an & 0x0080)
897 x = 0x2000;
898 else if(an & 0x0040)
899 x = 0x1000;
900 else if(an & 0x0020)
901 x = 0x0800;
902 else
903 x = 0;
904 }
905 else if((bmcr & 0x2100) == 0x2100)
906 x = 0x4000;
907 else if(bmcr & 0x2000){
908 /*
909 * If FD capable, force it if necessary.
910 */
911 if((bmsr & 0x4000) && ctlr->fd){
912 miiw(ctlr, ctlr->curphyad, Bmcr, 0x2100);
913 x = 0x4000;
914 }
915 else
916 x = 0x2000;
917 }
918 else if(bmcr & 0x0100)
919 x = 0x1000;
920 else
921 x = 0x0800;
922
923 csr6 = Sc|Mbo|Hbd|Ps|Ca|TrMODE|Sb;
924 if(ctlr->fdx & x)
925 csr6 |= Fd;
926 if(ctlr->ttm & x)
927 csr6 |= Ttm;
928 debug("csr6 0x%8.8uX 0x%8.8uX 0x%8.8luX\n",
929 csr6, ctlr->csr6, csr32r(ctlr, 6));
930 if(csr6 != ctlr->csr6){
931 ctlr->csr6 = csr6;
932 csr32w(ctlr, 6, csr6);
933 }
934
935 return 1;
936 }
937
938 static int
typephymode(Ctlr * ctlr,uchar * block,int wait)939 typephymode(Ctlr* ctlr, uchar* block, int wait)
940 {
941 uchar *p;
942 int len, mc, nway, phyx, timeo;
943
944 if(DEBUG){
945 int i;
946
947 len = (block[0] & ~0x80)+1;
948 for(i = 0; i < len; i++)
949 debug("%2.2uX ", block[i]);
950 debug("\n");
951 }
952
953 if(block[1] == 1)
954 len = 1;
955 else if(block[1] == 3)
956 len = 2;
957 else
958 return -1;
959
960 /*
961 * Snarf the media capabilities, nway advertisment,
962 * FDX and TTM bitmaps.
963 */
964 p = &block[5+len*block[3]+len*block[4+len*block[3]]];
965 mc = *p++;
966 mc |= *p++<<8;
967 nway = *p++;
968 nway |= *p++<<8;
969 ctlr->fdx = *p++;
970 ctlr->fdx |= *p++<<8;
971 ctlr->ttm = *p++;
972 ctlr->ttm |= *p<<8;
973 debug("mc %4.4uX nway %4.4uX fdx %4.4uX ttm %4.4uX\n",
974 mc, nway, ctlr->fdx, ctlr->ttm);
975 USED(mc);
976
977 phyx = block[2];
978 ctlr->curphyad = ctlr->phy[phyx];
979
980 ctlr->csr6 = 0; /* Sc|Mbo|Hbd|Ps|Ca|TrMODE|Sb; */
981 // csr32w(ctlr, 6, ctlr->csr6);
982 if(typephylink(ctlr, block))
983 return 0;
984
985 if(!(ctlr->phyreset & (1<<phyx))){
986 debug("reset seq: len %d: ", block[3]);
987 if(ctlr->type5block)
988 type5block(ctlr, &ctlr->type5block[2]);
989 else
990 type5block(ctlr, &block[4+len*block[3]]);
991 debug("\n");
992 ctlr->phyreset |= (1<<phyx);
993 }
994
995 /*
996 * GPR sequence.
997 */
998 debug("gpr seq: len %d: ", block[3]);
999 type5block(ctlr, &block[3]);
1000 debug("\n");
1001
1002 ctlr->csr6 = 0; /* Sc|Mbo|Hbd|Ps|Ca|TrMODE|Sb; */
1003 // csr32w(ctlr, 6, ctlr->csr6);
1004 if(typephylink(ctlr, block))
1005 return 0;
1006
1007 /*
1008 * Turn off auto-negotiation, set the auto-negotiation
1009 * advertisment register then start the auto-negotiation
1010 * process again.
1011 */
1012 miiw(ctlr, ctlr->curphyad, Bmcr, 0);
1013 miiw(ctlr, ctlr->curphyad, Anar, nway|1);
1014 miiw(ctlr, ctlr->curphyad, Bmcr, 0x1000);
1015
1016 if(!wait)
1017 return 0;
1018
1019 for(timeo = 0; timeo < 45; timeo++){
1020 if(typephylink(ctlr, block))
1021 return 0;
1022 delay(100);
1023 }
1024
1025 return -1;
1026 }
1027
1028 static int
typesymmode(Ctlr * ctlr,uchar * block,int wait)1029 typesymmode(Ctlr *ctlr, uchar *block, int wait)
1030 {
1031 uint gpmode, gpdata, command;
1032
1033 USED(wait);
1034 gpmode = block[3] | ((uint) block[4] << 8);
1035 gpdata = block[5] | ((uint) block[6] << 8);
1036 command = (block[7] | ((uint) block[8] << 8)) & 0x71;
1037 if (command & 0x8000) {
1038 print("ether2114x.c: FIXME: handle type 4 mode blocks where cmd.active_invalid != 0\n");
1039 return -1;
1040 }
1041 csr32w(ctlr, 15, gpmode);
1042 csr32w(ctlr, 15, gpdata);
1043 ctlr->csr6 = (command & 0x71) << 18;
1044 csr32w(ctlr, 6, ctlr->csr6);
1045 return 0;
1046 }
1047
1048 static int
type2mode(Ctlr * ctlr,uchar * block,int)1049 type2mode(Ctlr* ctlr, uchar* block, int)
1050 {
1051 uchar *p;
1052 int csr6, csr13, csr14, csr15, gpc, gpd;
1053
1054 csr6 = Sc|Mbo|Ca|TrMODE|Sb;
1055 debug("type2mode: medium 0x%2.2uX\n", block[2]);
1056
1057 /*
1058 * Don't attempt full-duplex
1059 * unless explicitly requested.
1060 */
1061 if((block[2] & 0x3F) == 0x04){ /* 10BASE-TFD */
1062 if(!ctlr->fd)
1063 return -1;
1064 csr6 |= Fd;
1065 }
1066
1067 /*
1068 * Operating mode programming values from the datasheet
1069 * unless media specific data is explicitly given.
1070 */
1071 p = &block[3];
1072 if(block[2] & 0x40){
1073 csr13 = (block[4]<<8)|block[3];
1074 csr14 = (block[6]<<8)|block[5];
1075 csr15 = (block[8]<<8)|block[7];
1076 p += 6;
1077 }
1078 else switch(block[2] & 0x3F){
1079 default:
1080 return -1;
1081 case 0x00: /* 10BASE-T */
1082 csr13 = 0x00000001;
1083 csr14 = 0x00007F3F;
1084 csr15 = 0x00000008;
1085 break;
1086 case 0x01: /* 10BASE-2 */
1087 csr13 = 0x00000009;
1088 csr14 = 0x00000705;
1089 csr15 = 0x00000006;
1090 break;
1091 case 0x02: /* 10BASE-5 (AUI) */
1092 csr13 = 0x00000009;
1093 csr14 = 0x00000705;
1094 csr15 = 0x0000000E;
1095 break;
1096 case 0x04: /* 10BASE-TFD */
1097 csr13 = 0x00000001;
1098 csr14 = 0x00007F3D;
1099 csr15 = 0x00000008;
1100 break;
1101 }
1102 gpc = *p++<<16;
1103 gpc |= *p++<<24;
1104 gpd = *p++<<16;
1105 gpd |= *p<<24;
1106
1107 csr32w(ctlr, 13, 0);
1108 csr32w(ctlr, 14, csr14);
1109 csr32w(ctlr, 15, gpc|csr15);
1110 delay(10);
1111 csr32w(ctlr, 15, gpd|csr15);
1112 csr32w(ctlr, 13, csr13);
1113
1114 ctlr->csr6 = csr6;
1115 csr32w(ctlr, 6, ctlr->csr6);
1116
1117 debug("type2mode: csr13 %8.8uX csr14 %8.8uX csr15 %8.8uX\n",
1118 csr13, csr14, csr15);
1119 debug("type2mode: gpc %8.8uX gpd %8.8uX csr6 %8.8uX\n",
1120 gpc, gpd, csr6);
1121
1122 return 0;
1123 }
1124
1125 static int
type0link(Ctlr * ctlr,uchar * block)1126 type0link(Ctlr* ctlr, uchar* block)
1127 {
1128 int m, polarity, sense;
1129
1130 m = (block[3]<<8)|block[2];
1131 sense = 1<<((m & 0x000E)>>1);
1132 if(m & 0x0080)
1133 polarity = sense;
1134 else
1135 polarity = 0;
1136
1137 return (csr32r(ctlr, 12) & sense)^polarity;
1138 }
1139
1140 static int
type0mode(Ctlr * ctlr,uchar * block,int wait)1141 type0mode(Ctlr* ctlr, uchar* block, int wait)
1142 {
1143 int csr6, m, timeo;
1144
1145 csr6 = Sc|Mbo|Hbd|Ca|TrMODE|Sb;
1146 debug("type0: medium 0x%uX, fd %d: 0x%2.2uX 0x%2.2uX 0x%2.2uX 0x%2.2uX\n",
1147 ctlr->medium, ctlr->fd, block[0], block[1], block[2], block[3]);
1148 switch(block[0]){
1149 default:
1150 break;
1151
1152 case 0x04: /* 10BASE-TFD */
1153 case 0x05: /* 100BASE-TXFD */
1154 case 0x08: /* 100BASE-FXFD */
1155 /*
1156 * Don't attempt full-duplex
1157 * unless explicitly requested.
1158 */
1159 if(!ctlr->fd)
1160 return -1;
1161 csr6 |= Fd;
1162 break;
1163 }
1164
1165 m = (block[3]<<8)|block[2];
1166 if(m & 0x0001)
1167 csr6 |= Ps;
1168 if(m & 0x0010)
1169 csr6 |= Ttm;
1170 if(m & 0x0020)
1171 csr6 |= Pcs;
1172 if(m & 0x0040)
1173 csr6 |= Scr;
1174
1175 csr32w(ctlr, 12, block[1]);
1176 microdelay(10);
1177 csr32w(ctlr, 6, csr6);
1178 ctlr->csr6 = csr6;
1179
1180 if(!wait)
1181 return 0;
1182
1183 for(timeo = 0; timeo < 30; timeo++){
1184 if(type0link(ctlr, block))
1185 return 0;
1186 delay(100);
1187 }
1188
1189 return -1;
1190 }
1191
1192 static int
media21041(Ether * ether,int wait)1193 media21041(Ether* ether, int wait)
1194 {
1195 Ctlr* ctlr;
1196 uchar *block;
1197 int csr6, csr13, csr14, csr15, medium, timeo;
1198
1199 ctlr = ether->ctlr;
1200 block = ctlr->infoblock[ctlr->curk];
1201 debug("media21041: block[0] %2.2uX, medium %4.4uX sct %4.4uX\n",
1202 block[0], ctlr->medium, ctlr->sct);
1203
1204 medium = block[0] & 0x3F;
1205 if(ctlr->medium >= 0 && medium != ctlr->medium)
1206 return 0;
1207 if(ctlr->sct != 0x0800 && (ctlr->sct & 0x3F) != medium)
1208 return 0;
1209
1210 csr6 = Sc|Mbo|Ca|TrMODE|Sb;
1211 if(block[0] & 0x40){
1212 csr13 = (block[2]<<8)|block[1];
1213 csr14 = (block[4]<<8)|block[3];
1214 csr15 = (block[6]<<8)|block[5];
1215 }
1216 else switch(medium){
1217 default:
1218 return -1;
1219 case 0x00: /* 10BASE-T */
1220 csr13 = 0xEF01;
1221 csr14 = 0xFF3F;
1222 csr15 = 0x0008;
1223 break;
1224 case 0x01: /* 10BASE-2 */
1225 csr13 = 0xEF09;
1226 csr14 = 0xF73D;
1227 csr15 = 0x0006;
1228 break;
1229 case 0x02: /* 10BASE-5 */
1230 csr13 = 0xEF09;
1231 csr14 = 0xF73D;
1232 csr15 = 0x000E;
1233 break;
1234 case 0x04: /* 10BASE-TFD */
1235 csr13 = 0xEF01;
1236 csr14 = 0xFF3D;
1237 csr15 = 0x0008;
1238 break;
1239 }
1240
1241 csr32w(ctlr, 13, 0);
1242 csr32w(ctlr, 14, csr14);
1243 csr32w(ctlr, 15, csr15);
1244 csr32w(ctlr, 13, csr13);
1245 delay(10);
1246
1247 if(medium == 0x04)
1248 csr6 |= Fd;
1249 ctlr->csr6 = csr6;
1250 csr32w(ctlr, 6, ctlr->csr6);
1251
1252 debug("media21041: csr6 %8.8uX csr13 %4.4uX csr14 %4.4uX csr15 %4.4uX\n",
1253 csr6, csr13, csr14, csr15);
1254
1255 if(!wait)
1256 return 0;
1257
1258 for(timeo = 0; timeo < 30; timeo++){
1259 if(!(csr32r(ctlr, 12) & 0x0002)){
1260 debug("media21041: ok: csr12 %4.4luX timeo %d\n",
1261 csr32r(ctlr, 12), timeo);
1262 return 10;
1263 }
1264 delay(100);
1265 }
1266 debug("media21041: !ok: csr12 %4.4luX\n", csr32r(ctlr, 12));
1267
1268 return -1;
1269 }
1270
1271 static int
mediaxx(Ether * ether,int wait)1272 mediaxx(Ether* ether, int wait)
1273 {
1274 Ctlr* ctlr;
1275 uchar *block;
1276
1277 ctlr = ether->ctlr;
1278 block = ctlr->infoblock[ctlr->curk];
1279 if(block[0] & 0x80){
1280 switch(block[1]){
1281 default:
1282 return -1;
1283 case 0:
1284 if(ctlr->medium >= 0 && block[2] != ctlr->medium)
1285 return 0;
1286 /* need this test? */ if(ctlr->sct != 0x0800 && (ctlr->sct & 0x3F) != block[2])
1287 return 0;
1288 if(type0mode(ctlr, block+2, wait))
1289 return 0;
1290 break;
1291 case 1:
1292 if(typephymode(ctlr, block, wait))
1293 return 0;
1294 break;
1295 case 2:
1296 debug("type2: medium %d block[2] %d\n",
1297 ctlr->medium, block[2]);
1298 if(ctlr->medium >= 0 && ((block[2] & 0x3F) != ctlr->medium))
1299 return 0;
1300 if(type2mode(ctlr, block, wait))
1301 return 0;
1302 break;
1303 case 3:
1304 if(typephymode(ctlr, block, wait))
1305 return 0;
1306 break;
1307 case 4:
1308 debug("type4: medium %d block[2] %d\n",
1309 ctlr->medium, block[2]);
1310 if(ctlr->medium >= 0 && ((block[2] & 0x3F) != ctlr->medium))
1311 return 0;
1312 if(typesymmode(ctlr, block, wait))
1313 return 0;
1314 break;
1315 }
1316 }
1317 else{
1318 if(ctlr->medium >= 0 && block[0] != ctlr->medium)
1319 return 0;
1320 /* need this test? */if(ctlr->sct != 0x0800 && (ctlr->sct & 0x3F) != block[0])
1321 return 0;
1322 if(type0mode(ctlr, block, wait))
1323 return 0;
1324 }
1325
1326 if(ctlr->csr6){
1327 if(!(ctlr->csr6 & Ps) || (ctlr->csr6 & Ttm))
1328 return 10;
1329 return 100;
1330 }
1331
1332 return 0;
1333 }
1334
1335 static int
media(Ether * ether,int wait)1336 media(Ether* ether, int wait)
1337 {
1338 Ctlr* ctlr;
1339 int k, mbps;
1340
1341 ctlr = ether->ctlr;
1342 for(k = 0; k < ctlr->k; k++){
1343 switch(ctlr->id){
1344 default:
1345 mbps = mediaxx(ether, wait);
1346 break;
1347 case Tulip1: /* 21041 */
1348 mbps = media21041(ether, wait);
1349 break;
1350 }
1351 if(mbps > 0)
1352 return mbps;
1353 if(ctlr->curk == 0)
1354 ctlr->curk = ctlr->k-1;
1355 else
1356 ctlr->curk--;
1357 }
1358
1359 return 0;
1360 }
1361
1362 static char* mediatable[9] = {
1363 "10BASE-T", /* TP */
1364 "10BASE-2", /* BNC */
1365 "10BASE-5", /* AUI */
1366 "100BASE-TX",
1367 "10BASE-TFD",
1368 "100BASE-TXFD",
1369 "100BASE-T4",
1370 "100BASE-FX",
1371 "100BASE-FXFD",
1372 };
1373
1374 static uchar en1207[] = { /* Accton EN1207-COMBO */
1375 0x00, 0x00, 0xE8, /* [0] vendor ethernet code */
1376 0x00, /* [3] spare */
1377
1378 0x00, 0x08, /* [4] connection (LSB+MSB = 0x0800) */
1379 0x1F, /* [6] general purpose control */
1380 2, /* [7] block count */
1381
1382 0x00, /* [8] media code (10BASE-TX) */
1383 0x0B, /* [9] general purpose port data */
1384 0x9E, 0x00, /* [10] command (LSB+MSB = 0x009E) */
1385
1386 0x03, /* [8] media code (100BASE-TX) */
1387 0x1B, /* [9] general purpose port data */
1388 0x6D, 0x00, /* [10] command (LSB+MSB = 0x006D) */
1389
1390 /* There is 10BASE-2 as well, but... */
1391 };
1392
1393 static uchar ana6910fx[] = { /* Adaptec (Cogent) ANA-6910FX */
1394 0x00, 0x00, 0x92, /* [0] vendor ethernet code */
1395 0x00, /* [3] spare */
1396
1397 0x00, 0x08, /* [4] connection (LSB+MSB = 0x0800) */
1398 0x3F, /* [6] general purpose control */
1399 1, /* [7] block count */
1400
1401 0x07, /* [8] media code (100BASE-FX) */
1402 0x03, /* [9] general purpose port data */
1403 0x2D, 0x00 /* [10] command (LSB+MSB = 0x000D) */
1404 };
1405
1406 static uchar smc9332[] = { /* SMC 9332 */
1407 0x00, 0x00, 0xC0, /* [0] vendor ethernet code */
1408 0x00, /* [3] spare */
1409
1410 0x00, 0x08, /* [4] connection (LSB+MSB = 0x0800) */
1411 0x1F, /* [6] general purpose control */
1412 2, /* [7] block count */
1413
1414 0x00, /* [8] media code (10BASE-TX) */
1415 0x00, /* [9] general purpose port data */
1416 0x9E, 0x00, /* [10] command (LSB+MSB = 0x009E) */
1417
1418 0x03, /* [8] media code (100BASE-TX) */
1419 0x09, /* [9] general purpose port data */
1420 0x6D, 0x00, /* [10] command (LSB+MSB = 0x006D) */
1421 };
1422
1423 static uchar* leaf21140[] = {
1424 en1207, /* Accton EN1207-COMBO */
1425 ana6910fx, /* Adaptec (Cogent) ANA-6910FX */
1426 smc9332, /* SMC 9332 */
1427 nil,
1428 };
1429
1430 /*
1431 * Copied to ctlr->srom at offset 20.
1432 */
1433 static uchar leafpnic[] = {
1434 0x00, 0x00, 0x00, 0x00, /* MAC address */
1435 0x00, 0x00,
1436 0x00, /* controller 0 device number */
1437 0x1E, 0x00, /* controller 0 info leaf offset */
1438 0x00, /* reserved */
1439 0x00, 0x08, /* selected connection type */
1440 0x00, /* general purpose control */
1441 0x01, /* block count */
1442
1443 0x8C, /* format indicator and count */
1444 0x01, /* block type */
1445 0x00, /* PHY number */
1446 0x00, /* GPR sequence length */
1447 0x00, /* reset sequence length */
1448 0x00, 0x78, /* media capabilities */
1449 0xE0, 0x01, /* Nway advertisment */
1450 0x00, 0x50, /* FDX bitmap */
1451 0x00, 0x18, /* TTM bitmap */
1452 };
1453
1454 static int
srom(Ctlr * ctlr)1455 srom(Ctlr* ctlr)
1456 {
1457 int i, k, oui, phy, x;
1458 uchar *p;
1459
1460 /*
1461 * This is a partial decoding of the SROM format described in
1462 * 'Digital Semiconductor 21X4 Serial ROM Format, Version 4.05,
1463 * 2-Mar-98'. Only the 2114[03] are handled, support for other
1464 * controllers can be added as needed.
1465 * Do a dummy read first to get the size and allocate ctlr->srom.
1466 */
1467 sromr(ctlr, 0);
1468 if(ctlr->srom == nil)
1469 ctlr->srom = malloc((1<<ctlr->sromsz)*sizeof(ushort));
1470 if(ctlr->srom == nil)
1471 error(Enomem);
1472 for(i = 0; i < (1<<ctlr->sromsz); i++){
1473 x = sromr(ctlr, i);
1474 ctlr->srom[2*i] = x;
1475 ctlr->srom[2*i+1] = x>>8;
1476 }
1477
1478 if(DEBUG){
1479 print("srom:");
1480 for(i = 0; i < ((1<<ctlr->sromsz)*sizeof(ushort)); i++){
1481 if(i && ((i & 0x0F) == 0))
1482 print("\n ");
1483 print(" %2.2uX", ctlr->srom[i]);
1484 }
1485 print("\n");
1486 }
1487
1488 /*
1489 * There are at least 2 SROM layouts:
1490 * e.g. Digital EtherWORKS station address at offset 20;
1491 * this complies with the 21140A SROM
1492 * application note from Digital;
1493 * e.g. SMC9332 station address at offset 0 followed by
1494 * 2 additional bytes, repeated at offset
1495 * 6; the 8 bytes are also repeated in
1496 * reverse order at offset 8.
1497 * To check which it is, read the SROM and check for the repeating
1498 * patterns of the non-compliant cards; if that fails use the one at
1499 * offset 20.
1500 */
1501 ctlr->sromea = ctlr->srom;
1502 for(i = 0; i < 8; i++){
1503 x = ctlr->srom[i];
1504 if(x != ctlr->srom[15-i] || x != ctlr->srom[16+i]){
1505 ctlr->sromea = &ctlr->srom[20];
1506 break;
1507 }
1508 }
1509
1510 /*
1511 * Fake up the SROM for the PNIC and AMDtek.
1512 * They look like a 21140 with a PHY.
1513 * The MAC address is byte-swapped in the orginal
1514 * PNIC SROM data.
1515 */
1516 if(ctlr->id == Pnic){
1517 memmove(&ctlr->srom[20], leafpnic, sizeof(leafpnic));
1518 for(i = 0; i < Eaddrlen; i += 2){
1519 ctlr->srom[20+i] = ctlr->srom[i+1];
1520 ctlr->srom[20+i+1] = ctlr->srom[i];
1521 }
1522 }
1523 if(ctlr->id == CentaurP || ctlr->id == CentaurPcb){
1524 memmove(&ctlr->srom[20], leafpnic, sizeof(leafpnic));
1525 for(i = 0; i < Eaddrlen; i += 2){
1526 ctlr->srom[20+i] = ctlr->srom[8+i];
1527 ctlr->srom[20+i+1] = ctlr->srom[8+i+1];
1528 }
1529 }
1530
1531 /*
1532 * Next, try to find the info leaf in the SROM for media detection.
1533 * If it's a non-conforming card try to match the vendor ethernet code
1534 * and point p at a fake info leaf with compact 21140 entries.
1535 */
1536 if(ctlr->sromea == ctlr->srom){
1537 p = nil;
1538 for(i = 0; leaf21140[i] != nil; i++){
1539 if(memcmp(leaf21140[i], ctlr->sromea, 3) == 0){
1540 p = &leaf21140[i][4];
1541 break;
1542 }
1543 }
1544 if(p == nil)
1545 return -1;
1546 }
1547 else
1548 p = &ctlr->srom[(ctlr->srom[28]<<8)|ctlr->srom[27]];
1549
1550 /*
1551 * Set up the info needed for later media detection.
1552 * For the 21140, set the general-purpose mask in CSR12.
1553 * The info block entries are stored in order of increasing
1554 * precedence, so detection will work backwards through the
1555 * stored indexes into ctlr->srom.
1556 * If an entry is found which matches the selected connection
1557 * type, save the index. Otherwise, start at the last entry.
1558 * If any MII entries are found (type 1 and 3 blocks), scan
1559 * for PHYs.
1560 */
1561 ctlr->leaf = p;
1562 ctlr->sct = *p++;
1563 ctlr->sct |= *p++<<8;
1564 if(ctlr->id != Tulip3 && ctlr->id != Tulip1){
1565 csr32w(ctlr, 12, Gpc|*p++);
1566 delay(200);
1567 }
1568 ctlr->k = *p++;
1569 if(ctlr->k >= nelem(ctlr->infoblock))
1570 ctlr->k = nelem(ctlr->infoblock)-1;
1571 ctlr->sctk = ctlr->k-1;
1572 phy = 0;
1573 for(k = 0; k < ctlr->k; k++){
1574 ctlr->infoblock[k] = p;
1575 if(ctlr->id == Tulip1){
1576 debug("type21041: 0x%2.2uX\n", p[0]);
1577 if(ctlr->sct != 0x0800 && *p == (ctlr->sct & 0xFF))
1578 ctlr->sctk = k;
1579 if(*p & 0x40)
1580 p += 7;
1581 else
1582 p += 1;
1583 }
1584 /*
1585 * The RAMIX PMC665 has a badly-coded SROM,
1586 * hence the test for 21143 and type 3.
1587 */
1588 else if((*p & 0x80) || (ctlr->id == Tulip3 && *(p+1) == 3)){
1589 *p |= 0x80;
1590 if(*(p+1) == 1 || *(p+1) == 3)
1591 phy = 1;
1592 if(*(p+1) == 5)
1593 ctlr->type5block = p;
1594 p += (*p & ~0x80)+1;
1595 }
1596 else{
1597 debug("type0: 0x%2.2uX 0x%2.2uX 0x%2.2uX 0x%2.2uX\n",
1598 p[0], p[1], p[2], p[3]);
1599 if(ctlr->sct != 0x0800 && *p == (ctlr->sct & 0xFF))
1600 ctlr->sctk = k;
1601 p += 4;
1602 }
1603 }
1604 ctlr->curk = ctlr->sctk;
1605 debug("sct 0x%uX medium 0x%uX k %d curk %d phy %d\n",
1606 ctlr->sct, ctlr->medium, ctlr->k, ctlr->curk, phy);
1607
1608 if(phy){
1609 x = 0;
1610 for(k = 0; k < nelem(ctlr->phy); k++){
1611 if((ctlr->id == CentaurP || ctlr->id == CentaurPcb) && k != 1)
1612 continue;
1613 if((oui = miir(ctlr, k, 2)) == -1 || oui == 0)
1614 continue;
1615 debug("phy reg 2 %4.4uX\n", oui);
1616 if(DEBUG){
1617 oui = (oui & 0x3FF)<<6;
1618 oui |= miir(ctlr, k, 3)>>10;
1619 miir(ctlr, k, 1);
1620 debug("phy%d: index %d oui %uX reg1 %uX\n",
1621 x, k, oui, miir(ctlr, k, 1));
1622 USED(oui);
1623 }
1624 ctlr->phy[x] = k;
1625 }
1626 }
1627
1628 ctlr->fd = 0;
1629 ctlr->medium = -1;
1630
1631 return 0;
1632 }
1633
1634 static void
dec2114xpci(void)1635 dec2114xpci(void)
1636 {
1637 Ctlr *ctlr;
1638 Pcidev *p;
1639 int x;
1640
1641 p = nil;
1642 while(p = pcimatch(p, 0, 0)){
1643 if(p->ccrb != 0x02 || p->ccru != 0)
1644 continue;
1645 switch((p->did<<16)|p->vid){
1646 default:
1647 continue;
1648
1649 case Tulip3: /* 21143 */
1650 /*
1651 * Exit sleep mode.
1652 */
1653 x = pcicfgr32(p, 0x40);
1654 x &= ~0xC0000000;
1655 pcicfgw32(p, 0x40, x);
1656 /*FALLTHROUGH*/
1657
1658 case Tulip0: /* 21140 */
1659 case Tulip1: /* 21041 */
1660 case Pnic: /* PNIC */
1661 case Pnic2: /* PNIC-II */
1662 case CentaurP: /* ADMtek */
1663 case CentaurPcb: /* ADMtek CardBus */
1664 break;
1665 }
1666
1667 /*
1668 * bar[0] is the I/O port register address and
1669 * bar[1] is the memory-mapped register address.
1670 */
1671 ctlr = malloc(sizeof(Ctlr));
1672 if(ctlr == nil)
1673 error(Enomem);
1674 ctlr->port = p->mem[0].bar & ~0x01;
1675 ctlr->pcidev = p;
1676 ctlr->id = (p->did<<16)|p->vid;
1677
1678 if(ioalloc(ctlr->port, p->mem[0].size, 0, "dec2114x") < 0){
1679 print("dec2114x: port 0x%uX in use\n", ctlr->port);
1680 free(ctlr);
1681 continue;
1682 }
1683
1684 /*
1685 * Some cards (e.g. ANA-6910FX) seem to need the Ps bit
1686 * set or they don't always work right after a hardware
1687 * reset.
1688 */
1689 csr32w(ctlr, 6, Mbo|Ps);
1690 softreset(ctlr);
1691
1692 if(srom(ctlr)){
1693 iofree(ctlr->port);
1694 free(ctlr);
1695 continue;
1696 }
1697
1698 switch(ctlr->id){
1699 default:
1700 break;
1701 case Pnic: /* PNIC */
1702 /*
1703 * Turn off the jabber timer.
1704 */
1705 csr32w(ctlr, 15, 0x00000001);
1706 break;
1707 case CentaurP:
1708 case CentaurPcb:
1709 /*
1710 * Nice - the register offsets change from *8 to *4
1711 * for CSR16 and up...
1712 * CSR25/26 give the MAC address read from the SROM.
1713 * Don't really need to use this other than as a check,
1714 * the SROM will be read in anyway so the value there
1715 * can be used directly.
1716 */
1717 debug("csr25 %8.8luX csr26 %8.8luX\n",
1718 inl(ctlr->port+0xA4), inl(ctlr->port+0xA8));
1719 debug("phyidr1 %4.4luX phyidr2 %4.4luX\n",
1720 inl(ctlr->port+0xBC), inl(ctlr->port+0xC0));
1721 break;
1722 }
1723
1724 if(ctlrhead != nil)
1725 ctlrtail->next = ctlr;
1726 else
1727 ctlrhead = ctlr;
1728 ctlrtail = ctlr;
1729 }
1730 }
1731
1732 static int
reset(Ether * ether)1733 reset(Ether* ether)
1734 {
1735 Ctlr *ctlr;
1736 int i, x;
1737 uchar ea[Eaddrlen];
1738 static int scandone;
1739
1740 if(scandone == 0){
1741 dec2114xpci();
1742 scandone = 1;
1743 }
1744
1745 /*
1746 * Any adapter matches if no ether->port is supplied,
1747 * otherwise the ports must match.
1748 */
1749 for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){
1750 if(ctlr->active)
1751 continue;
1752 if(ether->port == 0 || ether->port == ctlr->port){
1753 ctlr->active = 1;
1754 break;
1755 }
1756 }
1757 if(ctlr == nil)
1758 return -1;
1759
1760 ether->ctlr = ctlr;
1761 ether->port = ctlr->port;
1762 ether->irq = ctlr->pcidev->intl;
1763 ether->tbdf = ctlr->pcidev->tbdf;
1764
1765 /*
1766 * Check if the adapter's station address is to be overridden.
1767 * If not, read it from the EEPROM and set in ether->ea prior to
1768 * loading the station address in the hardware.
1769 */
1770 memset(ea, 0, Eaddrlen);
1771 if(memcmp(ea, ether->ea, Eaddrlen) == 0)
1772 memmove(ether->ea, ctlr->sromea, Eaddrlen);
1773
1774 /*
1775 * Look for a medium override in case there's no autonegotiation
1776 * (no MII) or the autonegotiation fails.
1777 */
1778 for(i = 0; i < ether->nopt; i++){
1779 if(cistrcmp(ether->opt[i], "FD") == 0){
1780 ctlr->fd = 1;
1781 continue;
1782 }
1783 for(x = 0; x < nelem(mediatable); x++){
1784 debug("compare <%s> <%s>\n", mediatable[x],
1785 ether->opt[i]);
1786 if(cistrcmp(mediatable[x], ether->opt[i]))
1787 continue;
1788 ctlr->medium = x;
1789
1790 switch(ctlr->medium){
1791 default:
1792 ctlr->fd = 0;
1793 break;
1794
1795 case 0x04: /* 10BASE-TFD */
1796 case 0x05: /* 100BASE-TXFD */
1797 case 0x08: /* 100BASE-FXFD */
1798 ctlr->fd = 1;
1799 break;
1800 }
1801 break;
1802 }
1803 }
1804
1805 ether->mbps = media(ether, 1);
1806
1807 /*
1808 * Initialise descriptor rings, ethernet address.
1809 */
1810 ctlr->nrdr = Nrde;
1811 ctlr->ntdr = Ntde;
1812 pcisetbme(ctlr->pcidev);
1813 ctlrinit(ether);
1814
1815 /*
1816 * Linkage to the generic ethernet driver.
1817 */
1818 ether->attach = attach;
1819 ether->transmit = transmit;
1820 ether->interrupt = interrupt;
1821 ether->ifstat = ifstat;
1822
1823 ether->arg = ether;
1824 ether->shutdown = shutdown;
1825 ether->multicast = multicast;
1826 ether->promiscuous = promiscuous;
1827
1828 return 0;
1829 }
1830
1831 void
ether2114xlink(void)1832 ether2114xlink(void)
1833 {
1834 addethercard("2114x", reset);
1835 addethercard("21140", reset);
1836 }
1837