1 typedef struct BIOS32si BIOS32si; 2 typedef struct BIOS32ci BIOS32ci; 3 typedef struct Conf Conf; 4 typedef struct Confmem Confmem; 5 typedef union FPsave FPsave; 6 typedef struct FPssestate FPssestate; 7 typedef struct FPstate FPstate; 8 typedef struct ISAConf ISAConf; 9 typedef struct Label Label; 10 typedef struct Lock Lock; 11 typedef struct MMU MMU; 12 typedef struct Mach Mach; 13 typedef struct Notsave Notsave; 14 typedef struct PCArch PCArch; 15 typedef struct Pcidev Pcidev; 16 typedef struct PCMmap PCMmap; 17 typedef struct PCMslot PCMslot; 18 typedef struct Page Page; 19 typedef struct PMMU PMMU; 20 typedef struct Proc Proc; 21 typedef struct Segdesc Segdesc; 22 typedef vlong Tval; 23 typedef struct Ureg Ureg; 24 typedef struct Vctl Vctl; 25 26 #pragma incomplete BIOS32si 27 #pragma incomplete Pcidev 28 #pragma incomplete Ureg 29 30 #define MAXSYSARG 5 /* for mount(fd, afd, mpt, flag, arg) */ 31 32 #define KMESGSIZE (256*1024) /* lots, for acpi debugging */ 33 #define STAGESIZE 2048 34 35 /* 36 * parameters for sysproc.c 37 */ 38 #define AOUT_MAGIC (I_MAGIC) 39 40 struct Lock 41 { 42 ulong key; 43 ulong sr; 44 ulong pc; 45 Proc *p; 46 Mach *m; 47 ushort isilock; 48 long lockcycles; 49 }; 50 51 struct Label 52 { 53 ulong sp; 54 ulong pc; 55 }; 56 57 58 /* 59 * FPsave.status 60 */ 61 enum 62 { 63 /* this is a state */ 64 FPinit= 0, 65 FPactive= 1, 66 FPinactive= 2, 67 68 /* the following is a bit that can be or'd into the state */ 69 FPillegal= 0x100, 70 }; 71 72 struct FPstate /* x87 fpu state */ 73 { 74 ushort control; 75 ushort r1; 76 ushort status; 77 ushort r2; 78 ushort tag; 79 ushort r3; 80 ulong pc; 81 ushort selector; 82 ushort r4; 83 ulong operand; 84 ushort oselector; 85 ushort r5; 86 uchar regs[80]; /* floating point registers */ 87 }; 88 89 struct FPssestate /* SSE fp state */ 90 { 91 ushort fcw; /* control */ 92 ushort fsw; /* status */ 93 ushort ftw; /* tag */ 94 ushort fop; /* opcode */ 95 ulong fpuip; /* pc */ 96 ushort cs; /* pc segment */ 97 ushort r1; /* reserved */ 98 ulong fpudp; /* data pointer */ 99 ushort ds; /* data pointer segment */ 100 ushort r2; 101 ulong mxcsr; /* MXCSR register state */ 102 ulong mxcsr_mask; /* MXCSR mask register */ 103 uchar xregs[480]; /* extended registers */ 104 uchar alignpad[FPalign]; 105 }; 106 107 /* 108 * the FP regs must be stored here, not somewhere pointed to from here. 109 * port code assumes this. 110 */ 111 union FPsave { 112 FPstate; 113 FPssestate; 114 }; 115 116 struct Confmem 117 { 118 ulong base; 119 ulong npage; 120 ulong kbase; 121 ulong klimit; 122 }; 123 124 struct Conf 125 { 126 ulong nmach; /* processors */ 127 ulong nproc; /* processes */ 128 ulong monitor; /* has monitor? */ 129 Confmem mem[4]; /* physical memory */ 130 ulong npage; /* total physical pages of memory */ 131 ulong upages; /* user page pool */ 132 ulong nimage; /* number of page cache image headers */ 133 ulong nswap; /* number of swap pages */ 134 int nswppo; /* max # of pageouts per segment pass */ 135 ulong base0; /* base of bank 0 */ 136 ulong base1; /* base of bank 1 */ 137 ulong copymode; /* 0 is copy on write, 1 is copy on reference */ 138 ulong ialloc; /* max interrupt time allocation in bytes */ 139 ulong pipeqsize; /* size in bytes of pipe queues */ 140 int nuart; /* number of uart devices */ 141 }; 142 143 /* 144 * MMU stuff in proc 145 */ 146 #define NCOLOR 1 147 struct PMMU 148 { 149 Page* mmupdb; /* page directory base */ 150 Page* mmufree; /* unused page table pages */ 151 Page* mmuused; /* used page table pages */ 152 Page* kmaptable; /* page table used by kmap */ 153 uint lastkmap; /* last entry used by kmap */ 154 int nkmap; /* number of current kmaps */ 155 }; 156 157 /* 158 * things saved in the Proc structure during a notify 159 */ 160 struct Notsave 161 { 162 ulong svflags; 163 ulong svcs; 164 ulong svss; 165 }; 166 167 #include "../port/portdat.h" 168 169 typedef struct { 170 ulong link; /* link (old TSS selector) */ 171 ulong esp0; /* privilege level 0 stack pointer */ 172 ulong ss0; /* privilege level 0 stack selector */ 173 ulong esp1; /* privilege level 1 stack pointer */ 174 ulong ss1; /* privilege level 1 stack selector */ 175 ulong esp2; /* privilege level 2 stack pointer */ 176 ulong ss2; /* privilege level 2 stack selector */ 177 ulong xcr3; /* page directory base register - not used because we don't use trap gates */ 178 ulong eip; /* instruction pointer */ 179 ulong eflags; /* flags register */ 180 ulong eax; /* general registers */ 181 ulong ecx; 182 ulong edx; 183 ulong ebx; 184 ulong esp; 185 ulong ebp; 186 ulong esi; 187 ulong edi; 188 ulong es; /* segment selectors */ 189 ulong cs; 190 ulong ss; 191 ulong ds; 192 ulong fs; 193 ulong gs; 194 ulong ldt; /* selector for task's LDT */ 195 ulong iomap; /* I/O map base address + T-bit */ 196 } Tss; 197 198 struct Segdesc 199 { 200 ulong d0; 201 ulong d1; 202 }; 203 204 struct Mach 205 { 206 int machno; /* physical id of processor (KNOWN TO ASSEMBLY) */ 207 ulong splpc; /* pc of last caller to splhi */ 208 209 ulong* pdb; /* page directory base for this processor (va) */ 210 Tss* tss; /* tss for this processor */ 211 Segdesc *gdt; /* gdt for this processor */ 212 213 Proc* proc; /* current process on this processor */ 214 Proc* externup; /* extern register Proc *up */ 215 216 Page* pdbpool; 217 int pdbcnt; 218 219 ulong ticks; /* of the clock since boot time */ 220 Label sched; /* scheduler wakeup */ 221 Lock alarmlock; /* access to alarm list */ 222 void* alarm; /* alarms bound to this clock */ 223 int inclockintr; 224 225 Proc* readied; /* for runproc */ 226 ulong schedticks; /* next forced context switch */ 227 228 int tlbfault; 229 int tlbpurge; 230 int pfault; 231 int cs; 232 int syscall; 233 int load; 234 int intr; 235 int flushmmu; /* make current proc flush it's mmu state */ 236 int ilockdepth; 237 Perf perf; /* performance counters */ 238 239 ulong spuriousintr; 240 int lastintr; 241 242 int loopconst; 243 244 Lock apictimerlock; 245 int cpumhz; 246 uvlong cyclefreq; /* Frequency of user readable cycle counter */ 247 uvlong cpuhz; 248 int cpuidax; 249 int cpuiddx; 250 char cpuidid[16]; 251 char* cpuidtype; 252 int havetsc; 253 int havepge; 254 uvlong tscticks; 255 int pdballoc; 256 int pdbfree; 257 FPsave *fpsavalign; 258 259 vlong mtrrcap; 260 vlong mtrrdef; 261 vlong mtrrfix[11]; 262 vlong mtrrvar[32]; /* 256 max. */ 263 264 int stack[1]; 265 }; 266 267 /* 268 * KMap the structure doesn't exist, but the functions do. 269 */ 270 typedef struct KMap KMap; 271 #define VA(k) ((void*)(k)) 272 KMap* kmap(Page*); 273 void kunmap(KMap*); 274 275 struct 276 { 277 Lock; 278 int machs; /* bitmap of active CPUs */ 279 int exiting; /* shutdown */ 280 int ispanic; /* shutdown in response to a panic */ 281 int thunderbirdsarego; /* lets the added processors continue to schedinit */ 282 int rebooting; /* just idle cpus > 0 */ 283 }active; 284 285 /* 286 * routines for things outside the PC model, like power management 287 */ 288 struct PCArch 289 { 290 char* id; 291 int (*ident)(void); /* this should be in the model */ 292 void (*reset)(void); /* this should be in the model */ 293 int (*serialpower)(int); /* 1 == on, 0 == off */ 294 int (*modempower)(int); /* 1 == on, 0 == off */ 295 296 void (*intrinit)(void); 297 int (*intrenable)(Vctl*); 298 int (*intrvecno)(int); 299 int (*intrdisable)(int); 300 void (*introff)(void); 301 void (*intron)(void); 302 303 void (*clockenable)(void); 304 uvlong (*fastclock)(uvlong*); 305 void (*timerset)(uvlong); 306 307 void (*resetothers)(void); /* put other cpus into reset */ 308 }; 309 310 /* cpuid instruction result register bits */ 311 enum { 312 /* dx */ 313 Fpuonchip = 1<<0, 314 Vmex = 1<<1, /* virtual-mode extensions */ 315 Pse = 1<<3, /* page size extensions */ 316 Tsc = 1<<4, /* time-stamp counter */ 317 Cpumsr = 1<<5, /* model-specific registers, rdmsr/wrmsr */ 318 Pae = 1<<6, /* physical-addr extensions */ 319 Mce = 1<<7, /* machine-check exception */ 320 Cmpxchg8b = 1<<8, 321 Cpuapic = 1<<9, 322 Mtrr = 1<<12, /* memory-type range regs. */ 323 Pge = 1<<13, /* page global extension */ 324 Pse2 = 1<<17, /* more page size extensions */ 325 Clflush = 1<<19, 326 Mmx = 1<<23, 327 Fxsr = 1<<24, /* have SSE FXSAVE/FXRSTOR */ 328 Sse = 1<<25, /* thus sfence instr. */ 329 Sse2 = 1<<26, /* thus mfence & lfence instr.s */ 330 }; 331 332 /* 333 * a parsed plan9.ini line 334 */ 335 #define NISAOPT 8 336 337 struct ISAConf { 338 char *type; 339 ulong port; 340 int irq; 341 ulong dma; 342 ulong mem; 343 ulong size; 344 ulong freq; 345 346 int nopt; 347 char *opt[NISAOPT]; 348 }; 349 350 extern PCArch *arch; /* PC architecture */ 351 352 /* 353 * Each processor sees its own Mach structure at address MACHADDR. 354 * However, the Mach structures must also be available via the per-processor 355 * MMU information array machp, mainly for disambiguation and access to 356 * the clock which is only maintained by the bootstrap processor (0). 357 */ 358 Mach* machp[MAXMACH]; 359 360 #define MACHP(n) (machp[n]) 361 362 extern Mach *m; 363 #define up (((Mach*)MACHADDR)->externup) 364 365 /* 366 * hardware info about a device 367 */ 368 typedef struct { 369 ulong port; 370 int size; 371 } Devport; 372 373 struct DevConf 374 { 375 ulong intnum; /* interrupt number */ 376 char *type; /* card type, malloced */ 377 int nports; /* Number of ports */ 378 Devport *ports; /* The ports themselves */ 379 }; 380 381 typedef struct BIOS32ci { /* BIOS32 Calling Interface */ 382 u32int eax; 383 u32int ebx; 384 u32int ecx; 385 u32int edx; 386 u32int esi; 387 u32int edi; 388 } BIOS32ci; 389