1 typedef struct BIOS32si BIOS32si; 2 typedef struct BIOS32ci BIOS32ci; 3 typedef struct Conf Conf; 4 typedef struct Confmem Confmem; 5 typedef union FPsave FPsave; 6 typedef struct FPssestate FPssestate; 7 typedef struct FPstate FPstate; 8 typedef struct ISAConf ISAConf; 9 typedef struct Label Label; 10 typedef struct Lock Lock; 11 typedef struct MMU MMU; 12 typedef struct Mach Mach; 13 typedef struct PCArch PCArch; 14 typedef struct Pcidev Pcidev; 15 typedef struct PCMmap PCMmap; 16 typedef struct PCMslot PCMslot; 17 typedef struct Page Page; 18 typedef struct PMMU PMMU; 19 typedef struct Proc Proc; 20 typedef struct Segdesc Segdesc; 21 typedef struct SFPssestate SFPssestate; 22 typedef vlong Tval; 23 typedef struct Ureg Ureg; 24 typedef struct Vctl Vctl; 25 26 #pragma incomplete BIOS32si 27 #pragma incomplete Pcidev 28 #pragma incomplete Ureg 29 30 #define MAXSYSARG 5 /* for mount(fd, afd, mpt, flag, arg) */ 31 32 #define KMESGSIZE (256*1024) /* lots, for acpi debugging */ 33 #define STAGESIZE 2048 34 35 /* 36 * parameters for sysproc.c 37 */ 38 #define AOUT_MAGIC (I_MAGIC) 39 40 struct Lock 41 { 42 ulong key; 43 ulong sr; 44 ulong pc; 45 Proc *p; 46 Mach *m; 47 ushort isilock; 48 long lockcycles; 49 }; 50 51 struct Label 52 { 53 ulong sp; 54 ulong pc; 55 }; 56 57 58 /* 59 * FPsave.status 60 */ 61 enum 62 { 63 /* this is a state */ 64 FPinit= 0, 65 FPactive= 1, 66 FPinactive= 2, 67 68 /* the following is a bit that can be or'd into the state */ 69 FPillegal= 0x100, 70 }; 71 72 struct FPstate /* x87 fpu state */ 73 { 74 ushort control; 75 ushort r1; 76 ushort status; 77 ushort r2; 78 ushort tag; 79 ushort r3; 80 ulong pc; 81 ushort selector; 82 ushort r4; 83 ulong operand; 84 ushort oselector; 85 ushort r5; 86 uchar regs[80]; /* floating point registers */ 87 }; 88 89 struct FPssestate /* SSE fp state */ 90 { 91 ushort fcw; /* control */ 92 ushort fsw; /* status */ 93 ushort ftw; /* tag */ 94 ushort fop; /* opcode */ 95 ulong fpuip; /* pc */ 96 ushort cs; /* pc segment */ 97 ushort r1; /* reserved */ 98 ulong fpudp; /* data pointer */ 99 ushort ds; /* data pointer segment */ 100 ushort r2; 101 ulong mxcsr; /* MXCSR register state */ 102 ulong mxcsr_mask; /* MXCSR mask register */ 103 uchar xregs[480]; /* extended registers */ 104 }; 105 106 struct SFPssestate /* SSE fp state with alignment slop */ 107 { 108 FPssestate; 109 uchar alignpad[FPalign]; /* slop to allow copying to aligned addr */ 110 ulong magic; /* debugging: check for overrun */ 111 }; 112 113 /* 114 * the FP regs must be stored here, not somewhere pointed to from here. 115 * port code assumes this. 116 */ 117 union FPsave { 118 FPstate; 119 SFPssestate; 120 }; 121 122 struct Confmem 123 { 124 ulong base; 125 ulong npage; 126 ulong kbase; 127 ulong klimit; 128 }; 129 130 struct Conf 131 { 132 ulong nmach; /* processors */ 133 ulong nproc; /* processes */ 134 ulong monitor; /* has monitor? */ 135 Confmem mem[4]; /* physical memory */ 136 ulong npage; /* total physical pages of memory */ 137 ulong upages; /* user page pool */ 138 ulong nimage; /* number of page cache image headers */ 139 ulong nswap; /* number of swap pages */ 140 int nswppo; /* max # of pageouts per segment pass */ 141 ulong base0; /* base of bank 0 */ 142 ulong base1; /* base of bank 1 */ 143 ulong copymode; /* 0 is copy on write, 1 is copy on reference */ 144 ulong ialloc; /* max interrupt time allocation in bytes */ 145 ulong pipeqsize; /* size in bytes of pipe queues */ 146 int nuart; /* number of uart devices */ 147 }; 148 149 /* 150 * MMU stuff in proc 151 */ 152 #define NCOLOR 1 153 struct PMMU 154 { 155 Page* mmupdb; /* page directory base */ 156 Page* mmufree; /* unused page table pages */ 157 Page* mmuused; /* used page table pages */ 158 Page* kmaptable; /* page table used by kmap */ 159 uint lastkmap; /* last entry used by kmap */ 160 int nkmap; /* number of current kmaps */ 161 }; 162 163 #include "../port/portdat.h" 164 165 typedef struct { 166 ulong link; /* link (old TSS selector) */ 167 ulong esp0; /* privilege level 0 stack pointer */ 168 ulong ss0; /* privilege level 0 stack selector */ 169 ulong esp1; /* privilege level 1 stack pointer */ 170 ulong ss1; /* privilege level 1 stack selector */ 171 ulong esp2; /* privilege level 2 stack pointer */ 172 ulong ss2; /* privilege level 2 stack selector */ 173 ulong xcr3; /* page directory base register - not used because we don't use trap gates */ 174 ulong eip; /* instruction pointer */ 175 ulong eflags; /* flags register */ 176 ulong eax; /* general registers */ 177 ulong ecx; 178 ulong edx; 179 ulong ebx; 180 ulong esp; 181 ulong ebp; 182 ulong esi; 183 ulong edi; 184 ulong es; /* segment selectors */ 185 ulong cs; 186 ulong ss; 187 ulong ds; 188 ulong fs; 189 ulong gs; 190 ulong ldt; /* selector for task's LDT */ 191 ulong iomap; /* I/O map base address + T-bit */ 192 } Tss; 193 194 struct Segdesc 195 { 196 ulong d0; 197 ulong d1; 198 }; 199 200 struct Mach 201 { 202 int machno; /* physical id of processor (KNOWN TO ASSEMBLY) */ 203 ulong splpc; /* pc of last caller to splhi */ 204 205 ulong* pdb; /* page directory base for this processor (va) */ 206 Tss* tss; /* tss for this processor */ 207 Segdesc *gdt; /* gdt for this processor */ 208 209 Proc* proc; /* current process on this processor */ 210 Proc* externup; /* extern register Proc *up */ 211 212 Page* pdbpool; 213 int pdbcnt; 214 215 ulong ticks; /* of the clock since boot time */ 216 Label sched; /* scheduler wakeup */ 217 Lock alarmlock; /* access to alarm list */ 218 void* alarm; /* alarms bound to this clock */ 219 int inclockintr; 220 221 Proc* readied; /* for runproc */ 222 ulong schedticks; /* next forced context switch */ 223 224 int tlbfault; 225 int tlbpurge; 226 int pfault; 227 int cs; 228 int syscall; 229 int load; 230 int intr; 231 int flushmmu; /* make current proc flush it's mmu state */ 232 int ilockdepth; 233 Perf perf; /* performance counters */ 234 235 ulong spuriousintr; 236 int lastintr; 237 238 int loopconst; 239 240 Lock apictimerlock; 241 int cpumhz; 242 uvlong cyclefreq; /* Frequency of user readable cycle counter */ 243 uvlong cpuhz; 244 int cpuidax; 245 int cpuiddx; 246 char cpuidid[16]; 247 char* cpuidtype; 248 int havetsc; 249 int havepge; 250 uvlong tscticks; 251 int pdballoc; 252 int pdbfree; 253 FPsave *fpsavalign; 254 255 vlong mtrrcap; 256 vlong mtrrdef; 257 vlong mtrrfix[11]; 258 vlong mtrrvar[32]; /* 256 max. */ 259 260 int stack[1]; 261 }; 262 263 /* 264 * KMap the structure doesn't exist, but the functions do. 265 */ 266 typedef struct KMap KMap; 267 #define VA(k) ((void*)(k)) 268 KMap* kmap(Page*); 269 void kunmap(KMap*); 270 271 struct 272 { 273 Lock; 274 union { 275 uvlong machs; /* bitmap of active CPUs */ 276 ulong machsmap[(MAXMACH+BI2WD-1)/BI2WD]; 277 }; 278 int nmachs; /* number of bits set in machs(map) */ 279 int exiting; /* shutdown */ 280 int ispanic; /* shutdown in response to a panic */ 281 int thunderbirdsarego; /* lets the added processors continue to schedinit */ 282 int rebooting; /* just idle cpus > 0 */ 283 }active; 284 285 /* 286 * routines for things outside the PC model, like power management 287 */ 288 struct PCArch 289 { 290 char* id; 291 int (*ident)(void); /* this should be in the model */ 292 void (*reset)(void); /* this should be in the model */ 293 int (*serialpower)(int); /* 1 == on, 0 == off */ 294 int (*modempower)(int); /* 1 == on, 0 == off */ 295 296 void (*intrinit)(void); 297 int (*intrenable)(Vctl*); 298 int (*intrvecno)(int); 299 int (*intrdisable)(int); 300 void (*introff)(void); 301 void (*intron)(void); 302 303 void (*clockenable)(void); 304 uvlong (*fastclock)(uvlong*); 305 void (*timerset)(uvlong); 306 307 void (*resetothers)(void); /* put other cpus into reset */ 308 }; 309 310 /* cpuid instruction result register bits */ 311 enum { 312 /* dx */ 313 Fpuonchip = 1<<0, 314 Vmex = 1<<1, /* virtual-mode extensions */ 315 Pse = 1<<3, /* page size extensions */ 316 Tsc = 1<<4, /* time-stamp counter */ 317 Cpumsr = 1<<5, /* model-specific registers, rdmsr/wrmsr */ 318 Pae = 1<<6, /* physical-addr extensions */ 319 Mce = 1<<7, /* machine-check exception */ 320 Cmpxchg8b = 1<<8, 321 Cpuapic = 1<<9, 322 Mtrr = 1<<12, /* memory-type range regs. */ 323 Pge = 1<<13, /* page global extension */ 324 Pse2 = 1<<17, /* more page size extensions */ 325 Clflush = 1<<19, 326 Acpif = 1<<22, 327 Mmx = 1<<23, 328 Fxsr = 1<<24, /* have SSE FXSAVE/FXRSTOR */ 329 Sse = 1<<25, /* thus sfence instr. */ 330 Sse2 = 1<<26, /* thus mfence & lfence instr.s */ 331 }; 332 333 /* 334 * a parsed plan9.ini line 335 */ 336 #define NISAOPT 8 337 338 struct ISAConf { 339 char *type; 340 ulong port; 341 int irq; 342 ulong dma; 343 ulong mem; 344 ulong size; 345 ulong freq; 346 347 int nopt; 348 char *opt[NISAOPT]; 349 }; 350 351 extern PCArch *arch; /* PC architecture */ 352 353 /* 354 * Each processor sees its own Mach structure at address MACHADDR. 355 * However, the Mach structures must also be available via the per-processor 356 * MMU information array machp, mainly for disambiguation and access to 357 * the clock which is only maintained by the bootstrap processor (0). 358 */ 359 Mach* machp[MAXMACH]; 360 361 #define MACHP(n) (machp[n]) 362 363 extern Mach *m; 364 #define up (((Mach*)MACHADDR)->externup) 365 366 /* 367 * hardware info about a device 368 */ 369 typedef struct { 370 ulong port; 371 int size; 372 } Devport; 373 374 struct DevConf 375 { 376 ulong intnum; /* interrupt number */ 377 char *type; /* card type, malloced */ 378 int nports; /* Number of ports */ 379 Devport *ports; /* The ports themselves */ 380 }; 381 382 typedef struct BIOS32ci { /* BIOS32 Calling Interface */ 383 u32int eax; 384 u32int ebx; 385 u32int ecx; 386 u32int edx; 387 u32int esi; 388 u32int edi; 389 } BIOS32ci; 390