1 /* 2 * Time. 3 * 4 * HZ should divide 1000 evenly, ideally. 5 * 100, 125, 200, 250 and 333 are okay. 6 */ 7 #define HZ 100 /* clock frequency */ 8 #define MS2HZ (1000/HZ) /* millisec per clock tick */ 9 #define TK2SEC(t) ((t)/HZ) /* ticks to seconds */ 10 11 enum { 12 Mhz = 1000 * 1000, 13 }; 14 15 /* 16 * More accurate time 17 */ 18 #define MS2TMR(t) ((ulong)(((uvlong)(t) * m->cpuhz)/1000)) 19 #define US2TMR(t) ((ulong)(((uvlong)(t) * m->cpuhz)/1000000)) 20 21 /* 22 * we ignore the first 2 uarts on the omap3530 (see uarti8250.c) and use the 23 * third one but call it 0. 24 */ 25 #define CONSOLE 0 26 27 typedef struct Conf Conf; 28 typedef struct Confmem Confmem; 29 typedef struct FPsave FPsave; 30 typedef struct ISAConf ISAConf; 31 typedef struct Label Label; 32 typedef struct Lock Lock; 33 typedef struct Memcache Memcache; 34 typedef struct MMMU MMMU; 35 typedef struct Mach Mach; 36 typedef u32int Mreg; /* Msr - bloody UART */ 37 typedef struct Notsave Notsave; 38 typedef struct Page Page; 39 typedef struct PhysUart PhysUart; 40 typedef struct PMMU PMMU; 41 typedef struct Proc Proc; 42 typedef u32int PTE; 43 typedef struct Uart Uart; 44 typedef struct Ureg Ureg; 45 typedef uvlong Tval; 46 47 #pragma incomplete Ureg 48 49 #define MAXSYSARG 5 /* for mount(fd, mpt, flag, arg, srv) */ 50 51 /* 52 * parameters for sysproc.c 53 */ 54 #define AOUT_MAGIC (E_MAGIC) 55 56 struct Lock 57 { 58 ulong key; 59 u32int sr; 60 uintptr pc; 61 Proc* p; 62 Mach* m; 63 int isilock; 64 }; 65 66 struct Label 67 { 68 uintptr sp; 69 uintptr pc; 70 }; 71 72 /* 73 * emulated floating point 74 */ 75 struct FPsave 76 { 77 ulong status; 78 ulong control; 79 ulong regs[8][3]; 80 81 int fpstate; 82 }; 83 84 /* 85 * FPsave.status 86 */ 87 enum 88 { 89 FPinit, 90 FPactive, 91 FPinactive, 92 93 /* bit or'd with the state */ 94 FPillegal= 0x100, 95 }; 96 97 struct Confmem 98 { 99 uintptr base; 100 usize npage; 101 uintptr limit; 102 uintptr kbase; 103 uintptr klimit; 104 }; 105 106 struct Conf 107 { 108 ulong nmach; /* processors */ 109 ulong nproc; /* processes */ 110 Confmem mem[1]; /* physical memory */ 111 ulong npage; /* total physical pages of memory */ 112 usize upages; /* user page pool */ 113 ulong copymode; /* 0 is copy on write, 1 is copy on reference */ 114 ulong ialloc; /* max interrupt time allocation in bytes */ 115 ulong pipeqsize; /* size in bytes of pipe queues */ 116 ulong nimage; /* number of page cache image headers */ 117 ulong nswap; /* number of swap pages */ 118 int nswppo; /* max # of pageouts per segment pass */ 119 ulong hz; /* processor cycle freq */ 120 ulong mhz; 121 int monitor; /* flag */ 122 }; 123 124 /* 125 * things saved in the Proc structure during a notify 126 */ 127 struct Notsave { 128 int emptiness; 129 }; 130 131 /* 132 * MMU stuff in Mach. 133 */ 134 struct MMMU 135 { 136 PTE* mmul1; /* l1 for this processor */ 137 int mmul1lo; 138 int mmul1hi; 139 int mmupid; 140 }; 141 142 /* 143 * MMU stuff in proc 144 */ 145 #define NCOLOR 1 /* 1 level cache, don't worry about VCE's */ 146 struct PMMU 147 { 148 Page* mmul2; 149 Page* mmul2cache; /* free mmu pages */ 150 }; 151 152 #include "../port/portdat.h" 153 154 struct Mach 155 { 156 int machno; /* physical id of processor */ 157 uintptr splpc; /* pc of last caller to splhi */ 158 159 Proc* proc; /* current process */ 160 161 MMMU; 162 int flushmmu; /* flush current proc mmu state */ 163 164 ulong ticks; /* of the clock since boot time */ 165 Label sched; /* scheduler wakeup */ 166 Lock alarmlock; /* access to alarm list */ 167 void* alarm; /* alarms bound to this clock */ 168 int inclockintr; 169 170 Proc* readied; /* for runproc */ 171 ulong schedticks; /* next forced context switch */ 172 173 int cputype; 174 ulong delayloop; 175 176 /* stats */ 177 int tlbfault; 178 int tlbpurge; 179 int pfault; 180 int cs; 181 int syscall; 182 int load; 183 int intr; 184 uvlong fastclock; /* last sampled value */ 185 uvlong inidle; /* time spent in idlehands() */ 186 ulong spuriousintr; 187 int lastintr; 188 int ilockdepth; 189 Perf perf; /* performance counters */ 190 191 192 int cpumhz; 193 uvlong cpuhz; /* speed of cpu */ 194 uvlong cyclefreq; /* Frequency of user readable cycle counter */ 195 196 /* save areas for exceptions, hold R0-R4 */ 197 u32int sfiq[5]; 198 u32int sirq[5]; 199 u32int sund[5]; 200 u32int sabt[5]; 201 u32int smon[5]; /* probably not needed */ 202 u32int ssys[5]; 203 204 int stack[1]; 205 }; 206 207 /* 208 * Fake kmap. 209 */ 210 typedef void KMap; 211 #define VA(k) ((uintptr)(k)) 212 #define kmap(p) (KMap*)((p)->pa|kseg0) 213 #define kunmap(k) 214 215 struct 216 { 217 Lock; 218 int machs; /* bitmap of active CPUs */ 219 int exiting; /* shutdown */ 220 int ispanic; /* shutdown in response to a panic */ 221 }active; 222 223 extern register Mach* m; /* R10 */ 224 extern register Proc* up; /* R9 */ 225 extern uintptr kseg0; 226 extern Mach* machaddr[MAXMACH]; 227 extern ulong memsize; 228 extern int normalprint; 229 230 /* 231 * a parsed plan9.ini line 232 */ 233 #define NISAOPT 8 234 235 struct ISAConf { 236 char *type; 237 ulong port; 238 int irq; 239 ulong dma; 240 ulong mem; 241 ulong size; 242 ulong freq; 243 244 int nopt; 245 char *opt[NISAOPT]; 246 }; 247 248 #define MACHP(n) (machaddr[n]) 249 250 /* 251 * Horrid. But the alternative is 'defined'. 252 */ 253 #ifdef _DBGC_ 254 #define DBGFLG (dbgflg[_DBGC_]) 255 #else 256 #define DBGFLG (0) 257 #endif /* _DBGC_ */ 258 259 int vflag; 260 extern char dbgflg[256]; 261 262 #define dbgprint print /* for now */ 263 264 /* 265 * hardware info about a device 266 */ 267 typedef struct { 268 ulong port; 269 int size; 270 } Devport; 271 272 struct DevConf 273 { 274 ulong intnum; /* interrupt number */ 275 char *type; /* card type, malloced */ 276 int nports; /* Number of ports */ 277 Devport *ports; /* The ports themselves */ 278 }; 279 280 enum { 281 Dcache, 282 Icache, 283 Unified, 284 }; 285 286 /* characteristics of a given cache level */ 287 struct Memcache { 288 uint level; /* 1 is nearest processor, 2 further away */ 289 uint l1ip; /* l1 I policy */ 290 291 uint nways; /* associativity */ 292 uint nsets; 293 uint linelen; /* bytes per cache line */ 294 uint setsways; 295 296 uint log2linelen; 297 uint waysh; /* shifts for set/way register */ 298 uint setsh; 299 }; 300 301 enum Dmamode { 302 Const, 303 Postincr, 304 Index, 305 Index2, 306 }; 307