1 /* 2 * Time. 3 * 4 * HZ should divide 1000 evenly, ideally. 5 * 100, 125, 200, 250 and 333 are okay. 6 */ 7 #define HZ 100 /* clock frequency */ 8 #define MS2HZ (1000/HZ) /* millisec per clock tick */ 9 #define TK2SEC(t) ((t)/HZ) /* ticks to seconds */ 10 11 enum { 12 Mhz = 1000 * 1000, 13 }; 14 15 /* 16 * More accurate time 17 */ 18 #define MS2TMR(t) ((ulong)(((uvlong)(t) * m->cpuhz)/1000)) 19 #define US2TMR(t) ((ulong)(((uvlong)(t) * m->cpuhz)/1000000)) 20 21 /* 22 * we ignore the first 2 uarts on the omap3530 (see uarti8250.c) and use the 23 * third one but call it 0. 24 */ 25 #define CONSOLE 0 26 27 typedef struct Conf Conf; 28 typedef struct Confmem Confmem; 29 typedef struct FPsave FPsave; 30 typedef struct ISAConf ISAConf; 31 typedef struct Label Label; 32 typedef struct Lock Lock; 33 typedef struct Memcache Memcache; 34 typedef struct MMMU MMMU; 35 typedef struct Mach Mach; 36 typedef u32int Mreg; /* Msr - bloody UART */ 37 typedef struct Page Page; 38 typedef struct PhysUart PhysUart; 39 typedef struct PMMU PMMU; 40 typedef struct Proc Proc; 41 typedef u32int PTE; 42 typedef struct Uart Uart; 43 typedef struct Ureg Ureg; 44 typedef uvlong Tval; 45 46 #pragma incomplete Ureg 47 48 #define MAXSYSARG 5 /* for mount(fd, mpt, flag, arg, srv) */ 49 50 /* 51 * parameters for sysproc.c 52 */ 53 #define AOUT_MAGIC (E_MAGIC) 54 55 struct Lock 56 { 57 ulong key; 58 u32int sr; 59 uintptr pc; 60 Proc* p; 61 Mach* m; 62 int isilock; 63 }; 64 65 struct Label 66 { 67 uintptr sp; 68 uintptr pc; 69 }; 70 71 /* 72 * emulated floating point 73 */ 74 struct FPsave 75 { 76 ulong status; 77 ulong control; 78 ulong regs[8][3]; 79 80 int fpstate; 81 }; 82 83 /* 84 * FPsave.status 85 */ 86 enum 87 { 88 FPinit, 89 FPactive, 90 FPinactive, 91 92 /* bit or'd with the state */ 93 FPillegal= 0x100, 94 }; 95 96 struct Confmem 97 { 98 uintptr base; 99 usize npage; 100 uintptr limit; 101 uintptr kbase; 102 uintptr klimit; 103 }; 104 105 struct Conf 106 { 107 ulong nmach; /* processors */ 108 ulong nproc; /* processes */ 109 Confmem mem[1]; /* physical memory */ 110 ulong npage; /* total physical pages of memory */ 111 usize upages; /* user page pool */ 112 ulong copymode; /* 0 is copy on write, 1 is copy on reference */ 113 ulong ialloc; /* max interrupt time allocation in bytes */ 114 ulong pipeqsize; /* size in bytes of pipe queues */ 115 ulong nimage; /* number of page cache image headers */ 116 ulong nswap; /* number of swap pages */ 117 int nswppo; /* max # of pageouts per segment pass */ 118 ulong hz; /* processor cycle freq */ 119 ulong mhz; 120 int monitor; /* flag */ 121 }; 122 123 /* 124 * MMU stuff in Mach. 125 */ 126 struct MMMU 127 { 128 PTE* mmul1; /* l1 for this processor */ 129 int mmul1lo; 130 int mmul1hi; 131 int mmupid; 132 }; 133 134 /* 135 * MMU stuff in proc 136 */ 137 #define NCOLOR 1 /* 1 level cache, don't worry about VCE's */ 138 struct PMMU 139 { 140 Page* mmul2; 141 Page* mmul2cache; /* free mmu pages */ 142 }; 143 144 #include "../port/portdat.h" 145 146 struct Mach 147 { 148 int machno; /* physical id of processor */ 149 uintptr splpc; /* pc of last caller to splhi */ 150 151 Proc* proc; /* current process */ 152 153 MMMU; 154 int flushmmu; /* flush current proc mmu state */ 155 156 ulong ticks; /* of the clock since boot time */ 157 Label sched; /* scheduler wakeup */ 158 Lock alarmlock; /* access to alarm list */ 159 void* alarm; /* alarms bound to this clock */ 160 int inclockintr; 161 162 Proc* readied; /* for runproc */ 163 ulong schedticks; /* next forced context switch */ 164 165 int cputype; 166 ulong delayloop; 167 168 /* stats */ 169 int tlbfault; 170 int tlbpurge; 171 int pfault; 172 int cs; 173 int syscall; 174 int load; 175 int intr; 176 uvlong fastclock; /* last sampled value */ 177 ulong spuriousintr; 178 int lastintr; 179 int ilockdepth; 180 Perf perf; /* performance counters */ 181 182 183 int cpumhz; 184 uvlong cpuhz; /* speed of cpu */ 185 uvlong cyclefreq; /* Frequency of user readable cycle counter */ 186 187 /* save areas for exceptions, hold R0-R4 */ 188 u32int sfiq[5]; 189 u32int sirq[5]; 190 u32int sund[5]; 191 u32int sabt[5]; 192 u32int smon[5]; /* probably not needed */ 193 u32int ssys[5]; 194 195 int stack[1]; 196 }; 197 198 /* 199 * Fake kmap. 200 */ 201 typedef void KMap; 202 #define VA(k) ((uintptr)(k)) 203 #define kmap(p) (KMap*)((p)->pa|kseg0) 204 #define kunmap(k) 205 206 struct 207 { 208 Lock; 209 int machs; /* bitmap of active CPUs */ 210 int exiting; /* shutdown */ 211 int ispanic; /* shutdown in response to a panic */ 212 }active; 213 214 extern register Mach* m; /* R10 */ 215 extern register Proc* up; /* R9 */ 216 extern uintptr kseg0; 217 extern Mach* machaddr[MAXMACH]; 218 extern ulong memsize; 219 extern int normalprint; 220 221 /* 222 * a parsed plan9.ini line 223 */ 224 #define NISAOPT 8 225 226 struct ISAConf { 227 char *type; 228 ulong port; 229 int irq; 230 ulong dma; 231 ulong mem; 232 ulong size; 233 ulong freq; 234 235 int nopt; 236 char *opt[NISAOPT]; 237 }; 238 239 #define MACHP(n) (machaddr[n]) 240 241 /* 242 * Horrid. But the alternative is 'defined'. 243 */ 244 #ifdef _DBGC_ 245 #define DBGFLG (dbgflg[_DBGC_]) 246 #else 247 #define DBGFLG (0) 248 #endif /* _DBGC_ */ 249 250 int vflag; 251 extern char dbgflg[256]; 252 253 #define dbgprint print /* for now */ 254 255 /* 256 * hardware info about a device 257 */ 258 typedef struct { 259 ulong port; 260 int size; 261 } Devport; 262 263 struct DevConf 264 { 265 ulong intnum; /* interrupt number */ 266 char *type; /* card type, malloced */ 267 int nports; /* Number of ports */ 268 Devport *ports; /* The ports themselves */ 269 }; 270 271 enum { 272 Dcache, 273 Icache, 274 Unified, 275 }; 276 277 /* characteristics of a given cache level */ 278 struct Memcache { 279 uint level; /* 1 is nearest processor, 2 further away */ 280 uint l1ip; /* l1 I policy */ 281 282 uint nways; /* associativity */ 283 uint nsets; 284 uint linelen; /* bytes per cache line */ 285 uint setsways; 286 287 uint log2linelen; 288 uint waysh; /* shifts for set/way register */ 289 uint setsh; 290 }; 291 292 enum Dmamode { 293 Const, 294 Postincr, 295 Index, 296 Index2, 297 }; 298