1 enum { 2 Mhz = 1000*1000, 3 }; 4 5 /* 6 * duarts, frequency and registers 7 */ 8 #define DUARTFREQ 1843200 9 10 /* 11 * interrupt levels on CPU boards. 12 */ 13 enum 14 { 15 ILmin = 2, 16 /* 17 ILpci = 2, 18 ILunused3 = 3, 19 ILduart0 = 4, 20 IL8259 = 5, 21 ILperf = 6, 22 */ 23 IL8259 = 2, 24 ILduart0 = 3, 25 ILunused4 = 4, 26 ILunused5 = 5, 27 ILpci = 6, 28 29 ILclock = 7, 30 ILmax = 7, 31 32 ILshift = 8, 33 }; 34 35 /* 36 * PCI configuration regesters and interrupt bits 37 */ 38 #define Reset (ulong*)(PCICFG+0x104) 39 #define Rstcpucold (1<<2) /* cpu cold reset */ 40 41 #define Pcimapcfg (ulong*)(PCICFG+0x118) 42 #define Pciintrsts (ulong*)(PCICFG+0x13c) 43 #define Pciintren (ulong*)(PCICFG+0x138) 44 #define Pciintrenset (ulong*)(PCICFG+0x130) 45 #define Pciintrenclr (ulong*)(PCICFG+0x134) 46 #define Pciintrpol (ulong*)(PCICFG+0x12c) 47 #define Pciintredge (ulong*)(PCICFG+0x124) 48 49 #define Pciintrbase 25 50 51 /* 52 * i8259 interrupts 53 */ 54 enum { 55 IrqCLOCK = 0, 56 IrqKBD = 1, 57 IrqUART1 = 3, 58 IrqUART0 = 4, 59 IrqPCMCIA = 5, 60 IrqFLOPPY = 6, 61 IrqLPT = 7, 62 IrqIRQ7 = 7, 63 IrqAUX = 12, /* PS/2 port */ 64 IrqIRQ13 = 13, /* coprocessor on 386 */ 65 IrqATA0 = 14, 66 IrqATA1 = 15, 67 MaxIrqPIC = 15, 68 69 VectorPIC = 0, 70 MaxVectorPIC = VectorPIC+MaxIrqPIC, 71 }; 72 73 74 /* 75 * mostly PCI from here on 76 */ 77 78 typedef struct Pcisiz Pcisiz; 79 typedef struct Pcidev Pcidev; 80 typedef struct Vctl Vctl; 81 82 struct Vctl { 83 Vctl* next; /* handlers on this vector */ 84 85 char name[KNAMELEN]; /* of driver */ 86 int isintr; /* interrupt or fault/trap */ 87 int irq; 88 int tbdf; 89 int (*isr)(int); /* get isr bit for this irq */ 90 int (*eoi)(int); /* eoi */ 91 92 void (*f)(Ureg*, void*); /* handler to call */ 93 void* a; /* argument to call it with */ 94 }; 95 96 enum { 97 BusCBUS = 0, /* Corollary CBUS */ 98 BusCBUSII, /* Corollary CBUS II */ 99 BusEISA, /* Extended ISA */ 100 BusFUTURE, /* IEEE Futurebus */ 101 BusINTERN, /* Internal bus */ 102 BusISA, /* Industry Standard Architecture */ 103 BusMBI, /* Multibus I */ 104 BusMBII, /* Multibus II */ 105 BusMCA, /* Micro Channel Architecture */ 106 BusMPI, /* MPI */ 107 BusMPSA, /* MPSA */ 108 BusNUBUS, /* Apple Macintosh NuBus */ 109 BusPCI, /* Peripheral Component Interconnect */ 110 BusPCMCIA, /* PC Memory Card International Association */ 111 BusTC, /* DEC TurboChannel */ 112 BusVL, /* VESA Local bus */ 113 BusVME, /* VMEbus */ 114 BusXPRESS, /* Express System Bus */ 115 }; 116 117 #define MKBUS(t,b,d,f) (((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8)) 118 #define BUSFNO(tbdf) (((tbdf)>>8)&0x07) 119 #define BUSDNO(tbdf) (((tbdf)>>11)&0x1F) 120 #define BUSBNO(tbdf) (((tbdf)>>16)&0xFF) 121 #define BUSTYPE(tbdf) ((tbdf)>>24) 122 #define BUSBDF(tbdf) ((tbdf)&0x00FFFF00) 123 #define BUSUNKNOWN (-1) 124 125 enum { 126 MaxEISA = 16, 127 CfgEISA = 0xC80, 128 }; 129 130 /* 131 * PCI support code. 132 */ 133 enum { /* type 0 & type 1 pre-defined header */ 134 PciVID = 0x00, /* vendor ID */ 135 PciDID = 0x02, /* device ID */ 136 PciPCR = 0x04, /* command */ 137 PciPSR = 0x06, /* status */ 138 PciRID = 0x08, /* revision ID */ 139 PciCCRp = 0x09, /* programming interface class code */ 140 PciCCRu = 0x0A, /* sub-class code */ 141 PciCCRb = 0x0B, /* base class code */ 142 PciCLS = 0x0C, /* cache line size */ 143 PciLTR = 0x0D, /* latency timer */ 144 PciHDT = 0x0E, /* header type */ 145 PciBST = 0x0F, /* BIST */ 146 147 PciBAR0 = 0x10, /* base address */ 148 PciBAR1 = 0x14, 149 150 PciINTL = 0x3C, /* interrupt line */ 151 PciINTP = 0x3D, /* interrupt pin */ 152 }; 153 154 /* ccrb (base class code) values; controller types */ 155 enum { 156 Pcibcpci1 = 0, /* pci 1.0; no class codes defined */ 157 Pcibcstore = 1, /* mass storage */ 158 Pcibcnet = 2, /* network */ 159 Pcibcdisp = 3, /* display */ 160 Pcibcmmedia = 4, /* multimedia */ 161 Pcibcmem = 5, /* memory */ 162 Pcibcbridge = 6, /* bridge */ 163 Pcibccomm = 7, /* simple comms (e.g., serial) */ 164 Pcibcbasesys = 8, /* base system */ 165 Pcibcinput = 9, /* input */ 166 Pcibcdock = 0xa, /* docking stations */ 167 Pcibcproc = 0xb, /* processors */ 168 Pcibcserial = 0xc, /* serial bus (e.g., USB) */ 169 Pcibcwireless = 0xd, /* wireless */ 170 Pcibcintell = 0xe, /* intelligent i/o */ 171 Pcibcsatcom = 0xf, /* satellite comms */ 172 Pcibccrypto = 0x10, /* encryption/decryption */ 173 Pcibcdacq = 0x11, /* data acquisition & signal proc. */ 174 }; 175 176 /* ccru (sub-class code) values; common cases only */ 177 enum { 178 /* mass storage */ 179 Pciscscsi = 0, /* SCSI */ 180 Pciscide = 1, /* IDE (ATA) */ 181 Pciscsata = 6, /* SATA */ 182 183 /* network */ 184 Pciscether = 0, /* Ethernet */ 185 186 /* display */ 187 Pciscvga = 0, /* VGA */ 188 Pciscxga = 1, /* XGA */ 189 Pcisc3d = 2, /* 3D */ 190 191 /* bridges */ 192 Pcischostpci = 0, /* host/pci */ 193 Pciscpcicpci = 1, /* pci/pci */ 194 195 /* simple comms */ 196 Pciscserial = 0, /* 16450, etc. */ 197 Pciscmultiser = 1, /* multiport serial */ 198 199 /* serial bus */ 200 Pciscusb = 3, /* USB */ 201 }; 202 203 enum { /* type 0 pre-defined header */ 204 PciCIS = 0x28, /* cardbus CIS pointer */ 205 PciSVID = 0x2C, /* subsystem vendor ID */ 206 PciSID = 0x2E, /* cardbus CIS pointer */ 207 PciEBAR0 = 0x30, /* expansion ROM base address */ 208 PciMGNT = 0x3E, /* burst period length */ 209 PciMLT = 0x3F, /* maximum latency between bursts */ 210 }; 211 212 enum { /* type 1 pre-defined header */ 213 PciPBN = 0x18, /* primary bus number */ 214 PciSBN = 0x19, /* secondary bus number */ 215 PciUBN = 0x1A, /* subordinate bus number */ 216 PciSLTR = 0x1B, /* secondary latency timer */ 217 PciIBR = 0x1C, /* I/O base */ 218 PciILR = 0x1D, /* I/O limit */ 219 PciSPSR = 0x1E, /* secondary status */ 220 PciMBR = 0x20, /* memory base */ 221 PciMLR = 0x22, /* memory limit */ 222 PciPMBR = 0x24, /* prefetchable memory base */ 223 PciPMLR = 0x26, /* prefetchable memory limit */ 224 PciPUBR = 0x28, /* prefetchable base upper 32 bits */ 225 PciPULR = 0x2C, /* prefetchable limit upper 32 bits */ 226 PciIUBR = 0x30, /* I/O base upper 16 bits */ 227 PciIULR = 0x32, /* I/O limit upper 16 bits */ 228 PciEBAR1 = 0x28, /* expansion ROM base address */ 229 PciBCR = 0x3E, /* bridge control register */ 230 }; 231 232 enum { /* type 2 pre-defined header */ 233 PciCBExCA = 0x10, 234 PciCBSPSR = 0x16, 235 PciCBPBN = 0x18, /* primary bus number */ 236 PciCBSBN = 0x19, /* secondary bus number */ 237 PciCBUBN = 0x1A, /* subordinate bus number */ 238 PciCBSLTR = 0x1B, /* secondary latency timer */ 239 PciCBMBR0 = 0x1C, 240 PciCBMLR0 = 0x20, 241 PciCBMBR1 = 0x24, 242 PciCBMLR1 = 0x28, 243 PciCBIBR0 = 0x2C, /* I/O base */ 244 PciCBILR0 = 0x30, /* I/O limit */ 245 PciCBIBR1 = 0x34, /* I/O base */ 246 PciCBILR1 = 0x38, /* I/O limit */ 247 PciCBSVID = 0x40, /* subsystem vendor ID */ 248 PciCBSID = 0x42, /* subsystem ID */ 249 PciCBLMBAR = 0x44, /* legacy mode base address */ 250 }; 251 252 struct Pcisiz 253 { 254 Pcidev* dev; 255 int siz; 256 int bar; 257 }; 258 259 struct Pcidev 260 { 261 int tbdf; /* type+bus+device+function */ 262 ushort vid; /* vendor ID */ 263 ushort did; /* device ID */ 264 265 ushort pcr; 266 267 uchar rid; 268 uchar ccrp; 269 uchar ccru; 270 uchar ccrb; 271 uchar cls; 272 uchar ltr; 273 274 struct { 275 ulong bar; /* base address */ 276 int size; 277 } mem[6]; 278 279 struct { 280 ulong bar; 281 int size; 282 } rom; 283 uchar intl; /* interrupt line */ 284 uchar intp; /* interrupt pin */ 285 286 Pcidev* list; 287 Pcidev* link; /* next device on this bno */ 288 289 Pcidev* bridge; /* down a bus */ 290 struct { 291 ulong bar; 292 int size; 293 } ioa, mema; 294 295 int pmrb; /* power management register block */ 296 }; 297 298 enum { 299 /* vendor ids */ 300 Vatiamd = 0x1002, 301 Vintel = 0x8086, 302 Vjmicron= 0x197b, 303 Vmarvell= 0x1b4b, 304 Vmyricom= 0x14c1, 305 Vrtl = 0x10ec, 306 }; 307 308 #define PCIWINDOW 0x80000000 309 #define PCIWADDR(va) (PADDR(va)+PCIWINDOW) 310 #define ISAWINDOW 0 311 #define ISAWADDR(va) (PADDR(va)+ISAWINDOW) 312 313 #define PCIMEMADDR(pa) ((pa)|PCIMEM) 314 315 /* SMBus transactions */ 316 enum 317 { 318 SMBquick, /* sends address only */ 319 320 /* write */ 321 SMBsend, /* sends address and cmd */ 322 SMBbytewrite, /* sends address and cmd and 1 byte */ 323 SMBwordwrite, /* sends address and cmd and 2 bytes */ 324 325 /* read */ 326 SMBrecv, /* sends address, recvs 1 byte */ 327 SMBbyteread, /* sends address and cmd, recv's byte */ 328 SMBwordread, /* sends address and cmd, recv's 2 bytes */ 329 }; 330 331 typedef struct SMBus SMBus; 332 struct SMBus { 333 QLock; /* mutex */ 334 Rendez r; /* rendezvous point for completion interrupts */ 335 void *arg; /* implementation dependent */ 336 ulong base; /* port or memory base of smbus */ 337 int busy; 338 void (*transact)(SMBus*, int, int, int, uchar*); 339 }; 340 341 #pragma varargck type "T" int 342 #pragma varargck type "T" uint 343