1 /*
2 * Realtek 8139 (but not the 8129).
3 * Error recovery for the various over/under -flow conditions
4 * may need work.
5 */
6 #include "u.h"
7 #include "../port/lib.h"
8 #include "mem.h"
9 #include "dat.h"
10 #include "fns.h"
11 #include "io.h"
12 #include "../port/error.h"
13 #include "../port/netif.h"
14
15 #include "etherif.h"
16
17 enum { /* registers */
18 Idr0 = 0x0000, /* MAC address */
19 Mar0 = 0x0008, /* Multicast address */
20 Tsd0 = 0x0010, /* Transmit Status Descriptor0 */
21 Tsad0 = 0x0020, /* Transmit Start Address Descriptor0 */
22 Rbstart = 0x0030, /* Receive Buffer Start Address */
23 Erbcr = 0x0034, /* Early Receive Byte Count */
24 Ersr = 0x0036, /* Early Receive Status */
25 Cr = 0x0037, /* Command Register */
26 Capr = 0x0038, /* Current Address of Packet Read */
27 Cbr = 0x003A, /* Current Buffer Address */
28 Imr = 0x003C, /* Interrupt Mask */
29 Isr = 0x003E, /* Interrupt Status */
30 Tcr = 0x0040, /* Transmit Configuration */
31 Rcr = 0x0044, /* Receive Configuration */
32 Tctr = 0x0048, /* Timer Count */
33 Mpc = 0x004C, /* Missed Packet Counter */
34 Cr9346 = 0x0050, /* 9346 Command Register */
35 Config0 = 0x0051, /* Configuration Register 0 */
36 Config1 = 0x0052, /* Configuration Register 1 */
37 TimerInt = 0x0054, /* Timer Interrupt */
38 Msr = 0x0058, /* Media Status */
39 Config3 = 0x0059, /* Configuration Register 3 */
40 Config4 = 0x005A, /* Configuration Register 4 */
41 Mulint = 0x005C, /* Multiple Interrupt Select */
42 RerID = 0x005E, /* PCI Revision ID */
43 Tsad = 0x0060, /* Transmit Status of all Descriptors */
44
45 Bmcr = 0x0062, /* Basic Mode Control */
46 Bmsr = 0x0064, /* Basic Mode Status */
47 Anar = 0x0066, /* Auto-Negotiation Advertisment */
48 Anlpar = 0x0068, /* Auto-Negotiation Link Partner */
49 Aner = 0x006A, /* Auto-Negotiation Expansion */
50 Dis = 0x006C, /* Disconnect Counter */
51 Fcsc = 0x006E, /* False Carrier Sense Counter */
52 Nwaytr = 0x0070, /* N-way Test */
53 Rec = 0x0072, /* RX_ER Counter */
54 Cscr = 0x0074, /* CS Configuration */
55 Phy1parm = 0x0078, /* PHY Parameter 1 */
56 Twparm = 0x007C, /* Twister Parameter */
57 Phy2parm = 0x0080, /* PHY Parameter 2 */
58 };
59
60 enum { /* Cr */
61 Bufe = 0x01, /* Rx Buffer Empty */
62 Te = 0x04, /* Transmitter Enable */
63 Re = 0x08, /* Receiver Enable */
64 Rst = 0x10, /* Software Reset */
65 };
66
67 enum { /* Imr/Isr */
68 Rok = 0x0001, /* Receive OK */
69 Rer = 0x0002, /* Receive Error */
70 Tok = 0x0004, /* Transmit OK */
71 Ter = 0x0008, /* Transmit Error */
72 Rxovw = 0x0010, /* Receive Buffer Overflow */
73 PunLc = 0x0020, /* Packet Underrun or Link Change */
74 Fovw = 0x0040, /* Receive FIFO Overflow */
75 Clc = 0x2000, /* Cable Length Change */
76 Timerbit = 0x4000, /* Timer */
77 Serr = 0x8000, /* System Error */
78 };
79
80 enum { /* Tcr */
81 Clrabt = 0x00000001, /* Clear Abort */
82 TxrrSHIFT = 4, /* Transmit Retry Count */
83 TxrrMASK = 0x000000F0,
84 MtxdmaSHIFT = 8, /* Max. DMA Burst Size */
85 MtxdmaMASK = 0x00000700,
86 Mtxdma2048 = 0x00000700,
87 Acrc = 0x00010000, /* Append CRC (not) */
88 LbkSHIFT = 17, /* Loopback Test */
89 LbkMASK = 0x00060000,
90 Rtl8139ArevG = 0x00800000, /* RTL8139A Rev. G ID */
91 IfgSHIFT = 24, /* Interframe Gap */
92 IfgMASK = 0x03000000,
93 HwveridSHIFT = 26, /* Hardware Version ID */
94 HwveridMASK = 0x7C000000,
95 };
96
97 enum { /* Rcr */
98 Aap = 0x00000001, /* Accept All Packets */
99 Apm = 0x00000002, /* Accept Physical Match */
100 Am = 0x00000004, /* Accept Multicast */
101 Ab = 0x00000008, /* Accept Broadcast */
102 Ar = 0x00000010, /* Accept Runt */
103 Aer = 0x00000020, /* Accept Error */
104 Sel9356 = 0x00000040, /* 9356 EEPROM used */
105 Wrap = 0x00000080, /* Rx Buffer Wrap Control */
106 MrxdmaSHIFT = 8, /* Max. DMA Burst Size */
107 MrxdmaMASK = 0x00000700,
108 Mrxdmaunlimited = 0x00000700,
109 RblenSHIFT = 11, /* Receive Buffer Length */
110 RblenMASK = 0x00001800,
111 Rblen8K = 0x00000000, /* 8KB+16 */
112 Rblen16K = 0x00000800, /* 16KB+16 */
113 Rblen32K = 0x00001000, /* 32KB+16 */
114 Rblen64K = 0x00001800, /* 64KB+16 */
115 RxfthSHIFT = 13, /* Receive Buffer Length */
116 RxfthMASK = 0x0000E000,
117 Rxfth256 = 0x00008000,
118 Rxfthnone = 0x0000E000,
119 Rer8 = 0x00010000, /* Accept Error Packets > 8 bytes */
120 MulERINT = 0x00020000, /* Multiple Early Interrupt Select */
121 ErxthSHIFT = 24, /* Early Rx Threshold */
122 ErxthMASK = 0x0F000000,
123 Erxthnone = 0x00000000,
124 };
125
126 enum { /* Received Packet Status */
127 Rcok = 0x0001, /* Receive Completed OK */
128 Fae = 0x0002, /* Frame Alignment Error */
129 Crc = 0x0004, /* CRC Error */
130 Long = 0x0008, /* Long Packet */
131 Runt = 0x0010, /* Runt Packet Received */
132 Ise = 0x0020, /* Invalid Symbol Error */
133 Bar = 0x2000, /* Broadcast Address Received */
134 Pam = 0x4000, /* Physical Address Matched */
135 Mar = 0x8000, /* Multicast Address Received */
136 };
137
138 enum { /* Media Status Register */
139 Rxpf = 0x01, /* Pause Flag */
140 Txpf = 0x02, /* Pause Flag */
141 Linkb = 0x04, /* Inverse of Link Status */
142 Speed10 = 0x08, /* 10Mbps */
143 Auxstatus = 0x10, /* Aux. Power Present Status */
144 Rxfce = 0x40, /* Receive Flow Control Enable */
145 Txfce = 0x80, /* Transmit Flow Control Enable */
146 };
147
148 typedef struct Td Td;
149 struct Td { /* Soft Transmit Descriptor */
150 int tsd;
151 int tsad;
152 uchar* data;
153 Block* bp;
154 };
155
156 enum { /* Tsd0 */
157 SizeSHIFT = 0, /* Descriptor Size */
158 SizeMASK = 0x00001FFF,
159 Own = 0x00002000,
160 Tun = 0x00004000, /* Transmit FIFO Underrun */
161 Tcok = 0x00008000, /* Transmit COmpleted OK */
162 EtxthSHIFT = 16, /* Early Tx Threshold */
163 EtxthMASK = 0x001F0000,
164 NccSHIFT = 24, /* Number of Collisions Count */
165 NccMASK = 0x0F000000,
166 Cdh = 0x10000000, /* CD Heartbeat */
167 Owc = 0x20000000, /* Out of Window Collision */
168 Tabt = 0x40000000, /* Transmit Abort */
169 Crs = 0x80000000, /* Carrier Sense Lost */
170 };
171
172 enum {
173 Rblen = Rblen64K, /* Receive Buffer Length */
174 Ntd = 4, /* Number of Transmit Descriptors */
175 Tdbsz = ROUNDUP(sizeof(Etherpkt), 4),
176 };
177
178 typedef struct Ctlr Ctlr;
179 typedef struct Ctlr {
180 int port;
181 Pcidev* pcidev;
182 Ctlr* next;
183 int active;
184 int id;
185
186 QLock alock; /* attach */
187 Lock ilock; /* init */
188 void* alloc; /* base of per-Ctlr allocated data */
189
190 int pcie; /* flag: pci-express device? */
191
192 uvlong mchash; /* multicast hash */
193
194 int rcr; /* receive configuration register */
195 uchar* rbstart; /* receive buffer */
196 int rblen; /* receive buffer length */
197 int ierrs; /* receive errors */
198
199 Lock tlock; /* transmit */
200 Td td[Ntd];
201 int ntd; /* descriptors active */
202 int tdh; /* host index into td */
203 int tdi; /* interface index into td */
204 int etxth; /* early transmit threshold */
205 int taligned; /* packet required no alignment */
206 int tunaligned; /* packet required alignment */
207
208 int dis; /* disconnect counter */
209 int fcsc; /* false carrier sense counter */
210 int rec; /* RX_ER counter */
211 uint mcast;
212 } Ctlr;
213
214 static Ctlr* ctlrhead;
215 static Ctlr* ctlrtail;
216
217 #define csr8r(c, r) (inb((c)->port+(r)))
218 #define csr16r(c, r) (ins((c)->port+(r)))
219 #define csr32r(c, r) (inl((c)->port+(r)))
220 #define csr8w(c, r, b) (outb((c)->port+(r), (int)(b)))
221 #define csr16w(c, r, w) (outs((c)->port+(r), (ushort)(w)))
222 #define csr32w(c, r, l) (outl((c)->port+(r), (ulong)(l)))
223
224 static void
rtl8139promiscuous(void * arg,int on)225 rtl8139promiscuous(void* arg, int on)
226 {
227 Ether *edev;
228 Ctlr * ctlr;
229
230 edev = arg;
231 ctlr = edev->ctlr;
232 ilock(&ctlr->ilock);
233
234 if(on)
235 ctlr->rcr |= Aap;
236 else
237 ctlr->rcr &= ~Aap;
238 csr32w(ctlr, Rcr, ctlr->rcr);
239 iunlock(&ctlr->ilock);
240 }
241
242 enum {
243 /* everyone else uses 0x04c11db7, but they both produce the same crc */
244 Etherpolybe = 0x04c11db6,
245 Bytemask = (1<<8) - 1,
246 };
247
248 static ulong
ethercrcbe(uchar * addr,long len)249 ethercrcbe(uchar *addr, long len)
250 {
251 int i, j;
252 ulong c, crc, carry;
253
254 crc = ~0UL;
255 for (i = 0; i < len; i++) {
256 c = addr[i];
257 for (j = 0; j < 8; j++) {
258 carry = ((crc & (1UL << 31))? 1: 0) ^ (c & 1);
259 crc <<= 1;
260 c >>= 1;
261 if (carry)
262 crc = (crc ^ Etherpolybe) | carry;
263 }
264 }
265 return crc;
266 }
267
268 static ulong
swabl(ulong l)269 swabl(ulong l)
270 {
271 return l>>24 | (l>>8) & (Bytemask<<8) |
272 (l<<8) & (Bytemask<<16) | l<<24;
273 }
274
275 static void
rtl8139multicast(void * ether,uchar * eaddr,int add)276 rtl8139multicast(void* ether, uchar *eaddr, int add)
277 {
278 Ether *edev;
279 Ctlr *ctlr;
280
281 if (!add)
282 return; /* ok to keep receiving on old mcast addrs */
283
284 edev = ether;
285 ctlr = edev->ctlr;
286 ilock(&ctlr->ilock);
287
288 ctlr->mchash |= 1ULL << (ethercrcbe(eaddr, Eaddrlen) >> 26);
289
290 ctlr->rcr |= Am;
291 csr32w(ctlr, Rcr, ctlr->rcr);
292
293 /* pci-e variants reverse the order of the hash byte registers */
294 if (0 && ctlr->pcie) {
295 csr32w(ctlr, Mar0, swabl(ctlr->mchash>>32));
296 csr32w(ctlr, Mar0+4, swabl(ctlr->mchash));
297 } else {
298 csr32w(ctlr, Mar0, ctlr->mchash);
299 csr32w(ctlr, Mar0+4, ctlr->mchash>>32);
300 }
301
302 iunlock(&ctlr->ilock);
303 }
304
305 static long
rtl8139ifstat(Ether * edev,void * a,long n,ulong offset)306 rtl8139ifstat(Ether* edev, void* a, long n, ulong offset)
307 {
308 int l;
309 char *p;
310 Ctlr *ctlr;
311
312 ctlr = edev->ctlr;
313 p = malloc(READSTR);
314 if(p == nil)
315 error(Enomem);
316 l = snprint(p, READSTR, "rcr %#8.8ux\n", ctlr->rcr);
317 l += snprint(p+l, READSTR-l, "multicast %ud\n", ctlr->mcast);
318 l += snprint(p+l, READSTR-l, "ierrs %d\n", ctlr->ierrs);
319 l += snprint(p+l, READSTR-l, "etxth %d\n", ctlr->etxth);
320 l += snprint(p+l, READSTR-l, "taligned %d\n", ctlr->taligned);
321 l += snprint(p+l, READSTR-l, "tunaligned %d\n", ctlr->tunaligned);
322 ctlr->dis += csr16r(ctlr, Dis);
323 l += snprint(p+l, READSTR-l, "dis %d\n", ctlr->dis);
324 ctlr->fcsc += csr16r(ctlr, Fcsc);
325 l += snprint(p+l, READSTR-l, "fcscnt %d\n", ctlr->fcsc);
326 ctlr->rec += csr16r(ctlr, Rec);
327 l += snprint(p+l, READSTR-l, "rec %d\n", ctlr->rec);
328
329 l += snprint(p+l, READSTR-l, "Tsd0-3 %#8.8lux %#8.8lux %#8.8lux %#8.8lux\n",
330 csr32r(ctlr, Tsd0), csr32r(ctlr, Tsd0+4),
331 csr32r(ctlr, Tsd0+8), csr32r(ctlr, Tsd0+12));
332 l += snprint(p+l, READSTR-l, "Cr %#2.2ux\n", csr8r(ctlr, Cr));
333 l += snprint(p+l, READSTR-l, "Tcr %#8.8lux\n", csr32r(ctlr, Tcr));
334 l += snprint(p+l, READSTR-1, "Rcr %#8.8lux\n", csr32r(ctlr, Rcr));
335 l += snprint(p+l, READSTR-1, "Rbstart %#8.8lux\n", csr32r(ctlr, Rbstart));
336 l += snprint(p+l, READSTR-1, "Capr %#4.4ux\n", csr16r(ctlr, Capr));
337 l += snprint(p+l, READSTR-1, "Cbr %#4.4ux\n", csr16r(ctlr, Cbr));
338 l += snprint(p+l, READSTR-l, "Config0 %#2.2ux\n", csr8r(ctlr, Config0));
339 l += snprint(p+l, READSTR-l, "Config1 %#2.2ux\n", csr8r(ctlr, Config1));
340 l += snprint(p+l, READSTR-l, "Msr %#2.2ux\n", csr8r(ctlr, Msr));
341 l += snprint(p+l, READSTR-l, "Config3 %#2.2ux\n", csr8r(ctlr, Config3));
342 l += snprint(p+l, READSTR-l, "Config4 %#2.2ux\n", csr8r(ctlr, Config4));
343
344 l += snprint(p+l, READSTR-l, "Bmcr %#4.4ux\n", csr16r(ctlr, Bmcr));
345 l += snprint(p+l, READSTR-l, "Bmsr %#4.4ux\n", csr16r(ctlr, Bmsr));
346 l += snprint(p+l, READSTR-l, "Anar %#4.4ux\n", csr16r(ctlr, Anar));
347 l += snprint(p+l, READSTR-l, "Anlpar %#4.4ux\n", csr16r(ctlr, Anlpar));
348 l += snprint(p+l, READSTR-l, "Aner %#4.4ux\n", csr16r(ctlr, Aner));
349 l += snprint(p+l, READSTR-l, "Nwaytr %#4.4ux\n", csr16r(ctlr, Nwaytr));
350 snprint(p+l, READSTR-l, "Cscr %#4.4ux\n", csr16r(ctlr, Cscr));
351 n = readstr(offset, a, n, p);
352 free(p);
353
354 return n;
355 }
356
357 static int
rtl8139reset(Ctlr * ctlr)358 rtl8139reset(Ctlr* ctlr)
359 {
360 int timeo;
361
362 /* stop interrupts */
363 csr16w(ctlr, Imr, 0);
364 csr16w(ctlr, Isr, ~0);
365 csr32w(ctlr, TimerInt, 0);
366
367 /*
368 * Soft reset the controller.
369 */
370 csr8w(ctlr, Cr, Rst);
371 for(timeo = 0; timeo < 1000; timeo++){
372 if(!(csr8r(ctlr, Cr) & Rst))
373 return 0;
374 delay(1);
375 }
376
377 return -1;
378 }
379
380 static void
rtl8139halt(Ctlr * ctlr)381 rtl8139halt(Ctlr* ctlr)
382 {
383 int i;
384
385 csr8w(ctlr, Cr, 0);
386 csr16w(ctlr, Imr, 0);
387 csr16w(ctlr, Isr, ~0);
388 csr32w(ctlr, TimerInt, 0);
389
390 for(i = 0; i < Ntd; i++){
391 if(ctlr->td[i].bp == nil)
392 continue;
393 freeb(ctlr->td[i].bp);
394 ctlr->td[i].bp = nil;
395 }
396 }
397
398 static void
rtl8139shutdown(Ether * edev)399 rtl8139shutdown(Ether *edev)
400 {
401 Ctlr *ctlr;
402
403 ctlr = edev->ctlr;
404 ilock(&ctlr->ilock);
405 rtl8139halt(ctlr);
406 rtl8139reset(ctlr);
407 iunlock(&ctlr->ilock);
408 }
409
410 static void
rtl8139init(Ether * edev)411 rtl8139init(Ether* edev)
412 {
413 int i;
414 ulong r;
415 Ctlr *ctlr;
416 uchar *alloc;
417
418 ctlr = edev->ctlr;
419 ilock(&ctlr->ilock);
420
421 rtl8139halt(ctlr);
422
423 /*
424 * MAC Address.
425 */
426 r = (edev->ea[3]<<24)|(edev->ea[2]<<16)|(edev->ea[1]<<8)|edev->ea[0];
427 csr32w(ctlr, Idr0, r);
428 r = (edev->ea[5]<<8)|edev->ea[4];
429 csr32w(ctlr, Idr0+4, r);
430
431 /*
432 * Receiver
433 */
434 alloc = (uchar*)ROUNDUP((uintptr)ctlr->alloc, 32);
435 ctlr->rbstart = KSEG1ADDR(alloc);
436 alloc += ctlr->rblen+16;
437 memset(ctlr->rbstart, 0, ctlr->rblen+16);
438 csr32w(ctlr, Rbstart, PCIWADDR(ctlr->rbstart));
439 ctlr->rcr = Rxfth256|Rblen|Mrxdmaunlimited|Ab|Am|Apm;
440
441 /*
442 * Transmitter.
443 */
444 for(i = 0; i < Ntd; i++){
445 ctlr->td[i].tsd = Tsd0+i*4;
446 ctlr->td[i].tsad = Tsad0+i*4;
447 ctlr->td[i].data = alloc;
448 alloc += Tdbsz;
449 ctlr->td[i].bp = nil;
450 }
451 ctlr->ntd = ctlr->tdh = ctlr->tdi = 0;
452 ctlr->etxth = 128/32;
453
454 /*
455 * Enable receiver/transmitter.
456 * Need to enable before writing the Rcr or it won't take.
457 */
458 csr8w(ctlr, Cr, Te|Re);
459 csr32w(ctlr, Tcr, Mtxdma2048);
460 csr32w(ctlr, Rcr, ctlr->rcr);
461 csr32w(ctlr, Mar0, 0);
462 csr32w(ctlr, Mar0+4, 0);
463 ctlr->mchash = 0;
464
465 /*
466 * Interrupts.
467 */
468 csr32w(ctlr, TimerInt, 0);
469 csr16w(ctlr, Imr, Serr|Timerbit|Fovw|PunLc|Rxovw|Ter|Tok|Rer|Rok);
470 csr32w(ctlr, Mpc, 0);
471
472 iunlock(&ctlr->ilock);
473 }
474
475 static void
rtl8139attach(Ether * edev)476 rtl8139attach(Ether* edev)
477 {
478 Ctlr *ctlr;
479
480 if(edev == nil) {
481 print("rtl8139attach: nil edev\n");
482 return;
483 }
484 ctlr = edev->ctlr;
485 if(ctlr == nil) {
486 print("rtl8139attach: nil ctlr for Ether %#p\n", edev);
487 return;
488 }
489 qlock(&ctlr->alock);
490 if(ctlr->alloc == nil){
491 ctlr->rblen = 1<<((Rblen>>RblenSHIFT)+13);
492 ctlr->alloc = malloc(ctlr->rblen+16 + Ntd*Tdbsz + 32);
493 if(ctlr->alloc == nil) {
494 qunlock(&ctlr->alock);
495 error(Enomem);
496 }
497 rtl8139init(edev);
498 }
499 qunlock(&ctlr->alock);
500 }
501
502 static void
rtl8139txstart(Ether * edev)503 rtl8139txstart(Ether* edev)
504 {
505 Td *td;
506 int size;
507 Block *bp;
508 Ctlr *ctlr;
509
510 ctlr = edev->ctlr;
511 while(ctlr->ntd < Ntd){
512 bp = qget(edev->oq);
513 if(bp == nil)
514 break;
515 size = BLEN(bp);
516
517 td = &ctlr->td[ctlr->tdh];
518 memmove(KSEG1ADDR(td->data), bp->rp, size);
519 freeb(bp);
520 csr32w(ctlr, td->tsad, PCIWADDR(td->data));
521 ctlr->tunaligned++;
522 /* if(1 || ((int)bp->rp) & 0x03){
523 memmove(KSEG1ADDR(td->data), bp->rp, size);
524 freeb(bp);
525 csr32w(ctlr, td->tsad, PCIWADDR(td->data));
526 ctlr->tunaligned++;
527 }
528 else{
529 td->bp = bp;
530 csr32w(ctlr, td->tsad, PCIWADDR(bp->rp));
531 ctlr->taligned++;
532 }
533 */
534 csr32w(ctlr, td->tsd, (ctlr->etxth<<EtxthSHIFT)|size);
535
536 ctlr->ntd++;
537 ctlr->tdh = NEXT(ctlr->tdh, Ntd);
538 }
539 }
540
541 static void
rtl8139transmit(Ether * edev)542 rtl8139transmit(Ether* edev)
543 {
544 Ctlr *ctlr;
545
546 ctlr = edev->ctlr;
547 ilock(&ctlr->tlock);
548 rtl8139txstart(edev);
549 iunlock(&ctlr->tlock);
550 }
551
552 static void
rtl8139receive(Ether * edev)553 rtl8139receive(Ether* edev)
554 {
555 Block *bp;
556 Ctlr *ctlr;
557 ushort capr;
558 uchar cr, *p;
559 int l, length, status;
560
561 ctlr = edev->ctlr;
562
563 /*
564 * Capr is where the host is reading from,
565 * Cbr is where the NIC is currently writing.
566 */
567 if(ctlr->rblen == 0)
568 return; /* not attached yet (shouldn't happen) */
569 capr = (csr16r(ctlr, Capr)+16) % ctlr->rblen;
570 while(!(csr8r(ctlr, Cr) & Bufe)){
571 p = ctlr->rbstart+capr;
572
573 /*
574 * Apparently the packet length may be 0xFFF0 if
575 * the NIC is still copying the packet into memory.
576 */
577 length = (*(p+3)<<8)|*(p+2);
578 if(length == 0xFFF0)
579 break;
580 status = (*(p+1)<<8)|*p;
581
582 if(!(status & Rcok)){
583 if(status & (Ise|Fae))
584 edev->frames++;
585 if(status & Crc)
586 edev->crcs++;
587 if(status & (Runt|Long))
588 edev->buffs++;
589
590 /*
591 * Reset the receiver.
592 * Also may have to restore the multicast list
593 * here too if it ever gets used.
594 */
595 cr = csr8r(ctlr, Cr);
596 csr8w(ctlr, Cr, cr & ~Re);
597 csr32w(ctlr, Rbstart, PCIWADDR(ctlr->rbstart));
598 csr8w(ctlr, Cr, cr);
599 csr32w(ctlr, Rcr, ctlr->rcr);
600
601 continue;
602 }
603
604 /*
605 * Receive Completed OK.
606 * Very simplistic; there are ways this could be done
607 * without copying, but the juice probably isn't worth
608 * the squeeze.
609 * The packet length includes a 4 byte CRC on the end.
610 */
611 capr = (capr+4) % ctlr->rblen;
612 p = ctlr->rbstart+capr;
613 capr = (capr+length) % ctlr->rblen;
614 if(status & Mar)
615 ctlr->mcast++;
616
617 if((bp = iallocb(length)) != nil){
618 if(p+length >= ctlr->rbstart+ctlr->rblen){
619 l = ctlr->rbstart+ctlr->rblen - p;
620 memmove(bp->wp, p, l);
621 bp->wp += l;
622 length -= l;
623 p = ctlr->rbstart;
624 }
625 if(length > 0){
626 memmove(bp->wp, p, length);
627 bp->wp += length;
628 }
629 bp->wp -= 4;
630 etheriq(edev, bp, 1);
631 }
632
633 capr = ROUNDUP(capr, 4);
634 csr16w(ctlr, Capr, capr-16);
635 }
636 }
637
638 static void
rtl8139interrupt(Ureg *,void * arg)639 rtl8139interrupt(Ureg*, void* arg)
640 {
641 Td *td;
642 Ctlr *ctlr;
643 Ether *edev;
644 int isr, msr, tsd;
645
646 edev = arg;
647 ctlr = edev->ctlr;
648 if(ctlr == nil) { /* not attached yet? (shouldn't happen) */
649 print("rtl8139interrupt: interrupt for unattached Ether %#p\n",
650 edev);
651 return;
652 }
653
654 while((isr = csr16r(ctlr, Isr)) != 0){
655 csr16w(ctlr, Isr, isr);
656 if(ctlr->alloc == nil) {
657 print("rtl8139interrupt: interrupt for unattached Ctlr "
658 "%#p port %#p\n", ctlr, (void *)ctlr->port);
659 return; /* not attached yet (shouldn't happen) */
660 }
661 if(isr & (Fovw|PunLc|Rxovw|Rer|Rok)){
662 rtl8139receive(edev);
663 if(!(isr & Rok))
664 ctlr->ierrs++;
665 isr &= ~(Fovw|Rxovw|Rer|Rok);
666 }
667
668 if(isr & (Ter|Tok)){
669 ilock(&ctlr->tlock);
670 while(ctlr->ntd){
671 td = &ctlr->td[ctlr->tdi];
672 tsd = csr32r(ctlr, td->tsd);
673 if(!(tsd & (Tabt|Tun|Tcok)))
674 break;
675
676 if(!(tsd & Tcok)){
677 if(tsd & Tun){
678 if(ctlr->etxth < ETHERMAXTU/32)
679 ctlr->etxth++;
680 }
681 edev->oerrs++;
682 }
683
684 if(td->bp != nil){
685 freeb(td->bp);
686 td->bp = nil;
687 }
688
689 ctlr->ntd--;
690 ctlr->tdi = NEXT(ctlr->tdi, Ntd);
691 }
692 rtl8139txstart(edev);
693 iunlock(&ctlr->tlock);
694 isr &= ~(Ter|Tok);
695 }
696
697 if(isr & PunLc){
698 /*
699 * Maybe the link changed - do we care very much?
700 */
701 msr = csr8r(ctlr, Msr);
702 if(!(msr & Linkb)){
703 if(!(msr & Speed10) && edev->mbps != 100){
704 edev->mbps = 100;
705 qsetlimit(edev->oq, 256*1024);
706 }
707 else if((msr & Speed10) && edev->mbps != 10){
708 edev->mbps = 10;
709 qsetlimit(edev->oq, 65*1024);
710 }
711 }
712 isr &= ~(Clc|PunLc);
713 }
714
715 /*
716 * Only Serr|Timerbit should be left by now.
717 * Should anything be done to tidy up? TimerInt isn't
718 * used so that can be cleared. A PCI bus error is indicated
719 * by Serr, that's pretty serious; is there anyhing to do
720 * other than try to reinitialise the chip?
721 */
722 if((isr & (Serr|Timerbit)) != 0){
723 iprint("rtl8139interrupt: imr %#4.4ux isr %#4.4ux\n",
724 csr16r(ctlr, Imr), isr);
725 if(isr & Timerbit)
726 csr32w(ctlr, TimerInt, 0);
727 if(isr & Serr)
728 rtl8139init(edev);
729 }
730 }
731 }
732
733 static Ctlr*
rtl8139match(Ether * edev,int id)734 rtl8139match(Ether* edev, int id)
735 {
736 Pcidev *p;
737 Ctlr *ctlr;
738 int i, port;
739
740 /*
741 * Any adapter matches if no edev->port is supplied,
742 * otherwise the ports must match.
743 */
744 for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){
745 if(ctlr->active)
746 continue;
747 p = ctlr->pcidev;
748 if(((p->did<<16)|p->vid) != id)
749 continue;
750 port = p->mem[0].bar & ~0x01;
751 if(edev->port != 0 && edev->port != port)
752 continue;
753
754 pcisetioe(p);
755
756 if(pcigetpms(p) > 0){
757 pcisetpms(p, 0);
758
759 for(i = 0; i < 6; i++)
760 pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar);
761 pcicfgw8(p, PciINTL, p->intl);
762 pcicfgw8(p, PciLTR, p->ltr);
763 pcicfgw8(p, PciCLS, p->cls);
764 pcicfgw16(p, PciPCR, p->pcr);
765 }
766
767 ctlr->port = port;
768 if(rtl8139reset(ctlr))
769 continue;
770 pcisetbme(p);
771
772 ctlr->active = 1;
773 return ctlr;
774 }
775 return nil;
776 }
777
778 static struct {
779 char* name;
780 int id;
781 } rtl8139pci[] = {
782 { "rtl8139", (0x8139<<16)|0x10EC, }, /* generic */
783 { "smc1211", (0x1211<<16)|0x1113, }, /* SMC EZ-Card */
784 { "dfe-538tx", (0x1300<<16)|0x1186, }, /* D-Link DFE-538TX */
785 { "dfe-560txd", (0x1340<<16)|0x1186, }, /* D-Link DFE-560TXD */
786 { nil },
787 };
788
789 static int
rtl8139pnp(Ether * edev)790 rtl8139pnp(Ether* edev)
791 {
792 int i, id;
793 Pcidev *p;
794 Ctlr *ctlr;
795 uchar ea[Eaddrlen];
796
797 /*
798 * Make a list of all ethernet controllers
799 * if not already done.
800 */
801 if(ctlrhead == nil){
802 p = nil;
803 while(p = pcimatch(p, 0, 0)){
804 if(p->ccrb != 0x02 || p->ccru != 0)
805 continue;
806 ctlr = malloc(sizeof(Ctlr));
807 if(ctlr == nil)
808 error(Enomem);
809 ctlr->pcidev = p;
810 ctlr->id = (p->did<<16)|p->vid;
811
812 if(ctlrhead != nil)
813 ctlrtail->next = ctlr;
814 else
815 ctlrhead = ctlr;
816 ctlrtail = ctlr;
817 }
818 }
819
820 /*
821 * Is it an RTL8139 under a different name?
822 * Normally a search is made through all the found controllers
823 * for one which matches any of the known vid+did pairs.
824 * If a vid+did pair is specified a search is made for that
825 * specific controller only.
826 */
827 id = 0;
828 for(i = 0; i < edev->nopt; i++){
829 if(cistrncmp(edev->opt[i], "id=", 3) == 0)
830 id = strtol(&edev->opt[i][3], nil, 0);
831 }
832
833 ctlr = nil;
834 if(id != 0)
835 ctlr = rtl8139match(edev, id);
836 else for(i = 0; rtl8139pci[i].name; i++){
837 if((ctlr = rtl8139match(edev, rtl8139pci[i].id)) != nil)
838 break;
839 }
840 if(ctlr == nil)
841 return -1;
842
843 edev->ctlr = ctlr;
844 edev->port = ctlr->port;
845 // edev->irq = ctlr->pcidev->intl;
846 edev->tbdf = ctlr->pcidev->tbdf;
847
848 /*
849 * Check if the adapter's station address is to be overridden.
850 * If not, read it from the device and set in edev->ea.
851 */
852 memset(ea, 0, Eaddrlen);
853 if(memcmp(ea, edev->ea, Eaddrlen) == 0){
854 i = csr32r(ctlr, Idr0);
855 edev->ea[0] = i;
856 edev->ea[1] = i>>8;
857 edev->ea[2] = i>>16;
858 edev->ea[3] = i>>24;
859 i = csr32r(ctlr, Idr0+4);
860 edev->ea[4] = i;
861 edev->ea[5] = i>>8;
862 }
863
864 edev->arg = edev;
865 edev->attach = rtl8139attach;
866 edev->transmit = rtl8139transmit;
867 edev->interrupt = rtl8139interrupt;
868 edev->ifstat = rtl8139ifstat;
869
870 edev->promiscuous = rtl8139promiscuous;
871 edev->multicast = rtl8139multicast;
872 edev->shutdown = rtl8139shutdown;
873
874 /*
875 * This should be much more dynamic but will do for now.
876 */
877 if((csr8r(ctlr, Msr) & (Speed10|Linkb)) == 0)
878 edev->mbps = 100;
879
880 return 0;
881 }
882
883 void
ether8139link(void)884 ether8139link(void)
885 {
886 addethercard("rtl8139", rtl8139pnp);
887 }
888