1 typedef struct Conf Conf; 2 typedef struct Confmem Confmem; 3 typedef struct FPsave FPsave; 4 typedef struct ISAConf ISAConf; 5 typedef struct Label Label; 6 typedef struct Lock Lock; 7 typedef struct Memcache Memcache; 8 typedef struct MMMU MMMU; 9 typedef struct Mach Mach; 10 typedef struct Page Page; 11 typedef struct Pcidev Pcidev; 12 typedef struct PhysUart PhysUart; 13 typedef struct PMMU PMMU; 14 typedef struct Proc Proc; 15 typedef u32int PTE; 16 typedef struct Soc Soc; 17 typedef struct Uart Uart; 18 typedef struct Ureg Ureg; 19 typedef uvlong Tval; 20 21 #pragma incomplete Pcidev 22 #pragma incomplete Ureg 23 24 #define MAXSYSARG 5 /* for mount(fd, mpt, flag, arg, srv) */ 25 26 /* 27 * parameters for sysproc.c 28 */ 29 #define AOUT_MAGIC (E_MAGIC) 30 31 struct Lock 32 { 33 ulong key; 34 u32int sr; 35 uintptr pc; 36 Proc* p; 37 Mach* m; 38 int isilock; 39 }; 40 41 struct Label 42 { 43 uintptr sp; 44 uintptr pc; 45 }; 46 47 /* 48 * emulated floating point 49 */ 50 struct FPsave 51 { 52 ulong status; 53 ulong control; 54 ulong regs[8][3]; 55 56 int fpstate; 57 }; 58 59 /* 60 * FPsave.status 61 */ 62 enum 63 { 64 FPinit, 65 FPactive, 66 FPinactive, 67 68 /* bit or'd with the state */ 69 FPillegal= 0x100, 70 }; 71 72 struct Confmem 73 { 74 uintptr base; 75 usize npage; 76 uintptr limit; 77 uintptr kbase; 78 uintptr klimit; 79 }; 80 81 struct Conf 82 { 83 ulong nmach; /* processors */ 84 ulong nproc; /* processes */ 85 ulong monitor; /* has monitor? */ 86 Confmem mem[1]; /* physical memory */ 87 ulong npage; /* total physical pages of memory */ 88 usize upages; /* user page pool */ 89 ulong copymode; /* 0 is copy on write, 1 is copy on reference */ 90 ulong ialloc; /* max interrupt time allocation in bytes */ 91 ulong pipeqsize; /* size in bytes of pipe queues */ 92 ulong nimage; /* number of page cache image headers */ 93 ulong nswap; /* number of swap pages */ 94 int nswppo; /* max # of pageouts per segment pass */ 95 // ulong hz; /* processor cycle freq */ 96 // ulong mhz; 97 }; 98 99 /* 100 * MMU stuff in Mach. 101 */ 102 struct MMMU 103 { 104 PTE* mmul1; /* l1 for this processor */ 105 int mmul1lo; 106 int mmul1hi; 107 int mmupid; 108 }; 109 110 /* 111 * MMU stuff in proc 112 */ 113 #define NCOLOR 1 /* 1 level cache, don't worry about VCE's */ 114 struct PMMU 115 { 116 Page* mmul2; 117 Page* mmul2cache; /* free mmu pages */ 118 }; 119 120 #include "../port/portdat.h" 121 122 struct Mach 123 { 124 int machno; /* physical id of processor */ 125 uintptr splpc; /* pc of last caller to splhi */ 126 127 Proc* proc; /* current process */ 128 129 MMMU; 130 int flushmmu; /* flush current proc mmu state */ 131 132 ulong ticks; /* of the clock since boot time */ 133 Label sched; /* scheduler wakeup */ 134 Lock alarmlock; /* access to alarm list */ 135 void* alarm; /* alarms bound to this clock */ 136 int inclockintr; 137 138 Proc* readied; /* for runproc */ 139 ulong schedticks; /* next forced context switch */ 140 141 int cputype; 142 int socrev; /* system-on-chip revision */ 143 ulong delayloop; 144 145 /* stats */ 146 int tlbfault; 147 int tlbpurge; 148 int pfault; 149 int cs; 150 int syscall; 151 int load; 152 int intr; 153 vlong fastclock; /* last sampled value */ 154 ulong spuriousintr; 155 int lastintr; 156 int ilockdepth; 157 Perf perf; /* performance counters */ 158 159 uvlong cpuhz; /* speed of cpu */ 160 uvlong cyclefreq; /* Frequency of user readable cycle counter */ 161 162 /* save areas for exceptions */ 163 u32int sfiq[5]; 164 u32int sirq[5]; 165 u32int sund[5]; 166 u32int sabt[5]; 167 #define fiqstack sfiq 168 #define irqstack sirq 169 #define abtstack sabt 170 #define undstack sund 171 172 int stack[1]; 173 }; 174 175 /* 176 * Fake kmap. 177 */ 178 typedef void KMap; 179 #define VA(k) ((uintptr)(k)) 180 #define kmap(p) (KMap*)((p)->pa|kseg0) 181 #define kunmap(k) 182 183 struct 184 { 185 Lock; 186 int machs; /* bitmap of active CPUs */ 187 int exiting; /* shutdown */ 188 int ispanic; /* shutdown in response to a panic */ 189 }active; 190 191 enum { 192 Frequency = 1200*1000*1000, /* the processor clock */ 193 }; 194 195 extern register Mach* m; /* R10 */ 196 extern register Proc* up; /* R9 */ 197 198 extern uintptr kseg0; 199 extern Mach* machaddr[MAXMACH]; 200 extern ulong memsize; 201 202 enum { 203 Nvec = 8, /* # of vectors at start of lexception.s */ 204 }; 205 206 /* 207 * Layout of physical 0. 208 */ 209 typedef struct Vectorpage { 210 void (*vectors[Nvec])(void); 211 uint vtable[Nvec]; 212 } Vectorpage; 213 214 /* 215 * a parsed plan9.ini line 216 */ 217 #define NISAOPT 8 218 219 struct ISAConf { 220 char *type; 221 ulong port; 222 int irq; 223 ulong dma; 224 ulong mem; 225 ulong size; 226 ulong freq; 227 228 int nopt; 229 char *opt[NISAOPT]; 230 }; 231 232 #define MACHP(n) (machaddr[n]) 233 234 /* 235 * Horrid. But the alternative is 'defined'. 236 */ 237 #ifdef _DBGC_ 238 #define DBGFLG (dbgflg[_DBGC_]) 239 #else 240 #define DBGFLG (0) 241 #endif /* _DBGC_ */ 242 243 int vflag; 244 extern char dbgflg[256]; 245 246 #define dbgprint print /* for now */ 247 248 /* 249 * hardware info about a device 250 */ 251 typedef struct { 252 ulong port; 253 int size; 254 } Devport; 255 256 struct DevConf 257 { 258 ulong intnum; /* interrupt number */ 259 char *type; /* card type, malloced */ 260 int nports; /* Number of ports */ 261 Devport *ports; /* The ports themselves */ 262 }; 263 264 enum { 265 Dcache, 266 Icache, 267 Unified, 268 }; 269 270 /* characteristics of a given cache level */ 271 struct Memcache { 272 uint level; /* 1 is nearest processor, 2 further away */ 273 uint kind; /* I, D or unified */ 274 275 uint size; 276 uint nways; /* associativity */ 277 uint nsets; 278 uint linelen; /* bytes per cache line */ 279 uint setsways; 280 281 uint log2linelen; 282 uint waysh; /* shifts for set/way register */ 283 uint setsh; 284 }; 285 286 struct Soc { /* addr's of SoC controllers */ 287 uintptr cpu; 288 uintptr devid; 289 uintptr l2cache; 290 uintptr sdramc; 291 292 uintptr iocfg; 293 uintptr addrmap; 294 uintptr intr; 295 uintptr nand; 296 uintptr cesa; /* crypto accel. */ 297 uintptr ehci; 298 uintptr spi; 299 uintptr twsi; 300 301 uintptr analog; 302 uintptr pci; 303 uintptr pcibase; 304 305 uintptr rtc; /* real-time clock */ 306 uintptr clock; 307 308 uintptr ether[2]; 309 uintptr sata[3]; 310 uintptr uart[2]; 311 uintptr gpio[2]; 312 } soc; 313 extern Soc soc; 314