1/* 2 * Common startup and coprocessor instructions for armv6 and armv7 3 * The rest of l.s has been moved to armv[67].s 4 */ 5 6#include "arm.s" 7 8/* 9 * on bcm2836, only cpu0 starts here 10 * other cpus enter at cpureset in armv7.s 11 */ 12TEXT _start(SB), 1, $-4 13 /* 14 * load physical base for SB addressing while mmu is off 15 * keep a handy zero in R0 until first function call 16 */ 17 MOVW $setR12(SB), R12 18 SUB $KZERO, R12 19 ADD $PHYSDRAM, R12 20 MOVW $0, R0 21 22 /* 23 * start stack at top of mach (physical addr) 24 */ 25 MOVW $PADDR(MACHADDR+MACHSIZE-4), R13 26 27 /* 28 * do arch-dependent startup (no return) 29 */ 30 BL ,armstart(SB) 31 B ,0(PC) 32 33 RET 34 35/* 36 * coprocessor instructions for local timer (armv7) 37 */ 38TEXT cprdfeat1(SB), 1, $-4 39 MRC CpSC, 0, R0, C(CpID), C(CpIDfeat), 1 40 RET 41TEXT cpwrtimerphysctl(SB), 1, $-4 42 MCR CpSC, 0, R0, C(CpTIMER), C(CpTIMERphys), CpTIMERphysctl 43 RET 44TEXT cpwrtimerphysval(SB), 1, $-4 45 MCR CpSC, 0, R0, C(CpTIMER), C(CpTIMERphys), CpTIMERphysval 46 RET 47 48/* 49 * coprocessor instructions for vfp3 50 */ 51 52#define VSTR(fpreg,Rn,off) \ 53 WORD $(0xed800000 | (fpreg&15)<<12 | ((fpreg&16)<<(22-4)) | Rn<<16 | CpDFP<<8 | (off)) 54#define VLDR(fpreg,Rn,off) \ 55 WORD $(0xed900000 | (fpreg&15)<<12 | ((fpreg&16)<<(22-4)) | Rn<<16 | CpDFP<<8 | (off)) 56#define VMSR(fpctlreg,Rt) WORD $(0xeee00010 | fpctlreg<<16 | Rt<<12 | CpFP<<8) 57#define VMRS(Rt,fpctlreg) WORD $(0xeef00010 | fpctlreg<<16 | Rt<<12 | CpFP<<8) 58#define Fpsid 0 59#define Fpscr 1 60#define Fpexc 8 61 62TEXT cprdcpaccess(SB), 1, $-4 63 MRC CpSC, 0, R0, C(CpCONTROL), C(0), CpCPaccess 64 RET 65TEXT cpwrcpaccess(SB), 1, $-4 66 MCR CpSC, 0, R0, C(CpCONTROL), C(0), CpCPaccess 67 BARRIERS 68 RET 69TEXT fprdsid(SB), 1, $-4 70 VMRS(0,Fpsid) 71 RET 72TEXT fprdscr(SB), 1, $-4 73 VMRS(0,Fpscr) 74 RET 75TEXT fprdexc(SB), 1, $-4 76 VMRS(0,Fpexc) 77 RET 78TEXT fpwrscr(SB), 1, $-4 79 VMSR(Fpscr,0) 80 RET 81TEXT fpwrexc(SB), 1, $-4 82 VMSR(Fpexc,0) 83 RET 84 85TEXT fpsaveregs(SB), 1, $-4 86 MOVW R0, R1 /* dest */ 87 MOVW 4(FP), R2 /* reg count */ 88 VSTR(0, 1, 0*2) 89 VSTR(1, 1, 1*2) 90 VSTR(2, 1, 2*2) 91 VSTR(3, 1, 3*2) 92 VSTR(4, 1, 4*2) 93 VSTR(5, 1, 5*2) 94 VSTR(6, 1, 6*2) 95 VSTR(7, 1, 7*2) 96 VSTR(8, 1, 8*2) 97 VSTR(9, 1, 9*2) 98 VSTR(10, 1, 10*2) 99 VSTR(11, 1, 11*2) 100 VSTR(12, 1, 12*2) 101 VSTR(13, 1, 13*2) 102 VSTR(14, 1, 14*2) 103 VSTR(15, 1, 15*2) 104 CMP $16, R2 105 BEQ fpsavex 106 VSTR(16, 1, 16*2) 107 VSTR(17, 1, 17*2) 108 VSTR(18, 1, 18*2) 109 VSTR(19, 1, 19*2) 110 VSTR(20, 1, 20*2) 111 VSTR(21, 1, 21*2) 112 VSTR(22, 1, 22*2) 113 VSTR(23, 1, 23*2) 114 VSTR(24, 1, 24*2) 115 VSTR(25, 1, 25*2) 116 VSTR(26, 1, 26*2) 117 VSTR(27, 1, 27*2) 118 VSTR(28, 1, 28*2) 119 VSTR(29, 1, 29*2) 120 VSTR(30, 1, 30*2) 121 VSTR(31, 1, 31*2) 122fpsavex: 123 RET 124 125TEXT fprestregs(SB), 1, $-4 126 MOVW R0, R1 /* src */ 127 MOVW 4(FP), R2 /* reg count */ 128 VLDR(0, 1, 0*2) 129 VLDR(1, 1, 1*2) 130 VLDR(2, 1, 2*2) 131 VLDR(3, 1, 3*2) 132 VLDR(4, 1, 4*2) 133 VLDR(5, 1, 5*2) 134 VLDR(6, 1, 6*2) 135 VLDR(7, 1, 7*2) 136 VLDR(8, 1, 8*2) 137 VLDR(9, 1, 9*2) 138 VLDR(10, 1, 10*2) 139 VLDR(11, 1, 11*2) 140 VLDR(12, 1, 12*2) 141 VLDR(13, 1, 13*2) 142 VLDR(14, 1, 14*2) 143 VLDR(15, 1, 15*2) 144 CMP $16, R2 145 BEQ fprestx 146 VLDR(16, 1, 16*2) 147 VLDR(17, 1, 17*2) 148 VLDR(18, 1, 18*2) 149 VLDR(19, 1, 19*2) 150 VLDR(20, 1, 20*2) 151 VLDR(21, 1, 21*2) 152 VLDR(22, 1, 22*2) 153 VLDR(23, 1, 23*2) 154 VLDR(24, 1, 24*2) 155 VLDR(25, 1, 25*2) 156 VLDR(26, 1, 26*2) 157 VLDR(27, 1, 27*2) 158 VLDR(28, 1, 28*2) 159 VLDR(29, 1, 29*2) 160 VLDR(30, 1, 30*2) 161 VLDR(31, 1, 31*2) 162fprestx: 163 RET 164