1 enum { 2 IRQtimer0 = 0, 3 IRQtimer1 = 1, 4 IRQtimer2 = 2, 5 IRQtimer3 = 3, 6 IRQclock = IRQtimer3, 7 IRQusb = 9, 8 IRQdma0 = 16, 9 #define IRQDMA(chan) (IRQdma0+(chan)) 10 IRQaux = 29, 11 IRQi2c = 53, 12 IRQspi = 54, 13 IRQsdhost = 56, 14 IRQmmc = 62, 15 16 IRQbasic = 64, 17 IRQtimerArm = IRQbasic + 0, 18 19 IRQpci = 84, 20 IRQether = 93, 21 22 IRQlocal = 96, 23 IRQcntps = IRQlocal + 0, 24 IRQcntpns = IRQlocal + 1, 25 IRQmbox0 = IRQlocal + 4, 26 IRQmbox1 = IRQlocal + 5, 27 IRQmbox2 = IRQlocal + 6, 28 IRQmbox3 = IRQlocal + 7, 29 IRQlocaltmr = IRQlocal + 11, 30 31 IRQfiq = IRQusb, /* only one source can be FIQ */ 32 33 DmaD2M = 0, /* device to memory */ 34 DmaM2D = 1, /* memory to device */ 35 DmaM2M = 2, /* memory to memory */ 36 37 DmaChanEmmc = 4, /* can only use 2-5, maybe 0 */ 38 DmaChanSdhost = 5, 39 DmaChanSpiTx= 2, 40 DmaChanSpiRx= 0, 41 42 DmaDevSpiTx = 6, 43 DmaDevSpiRx = 7, 44 DmaDevEmmc = 11, 45 DmaDevSdhost = 13, 46 47 PowerSd = 0, 48 PowerUart0, 49 PowerUart1, 50 PowerUsb, 51 PowerI2c0, 52 PowerI2c1, 53 PowerI2c2, 54 PowerSpi, 55 PowerCcp2tx, 56 57 ClkEmmc = 1, 58 ClkUart, 59 ClkArm, 60 ClkCore, 61 ClkV3d, 62 ClkH264, 63 ClkIsp, 64 ClkSdram, 65 ClkPixel, 66 ClkPwm, 67 }; 68