1/* 2 * armv6/v7 machine assist, definitions 3 * 4 * loader uses R11 as scratch. 5 */ 6 7#include "mem.h" 8#include "arm.h" 9 10#define PADDR(va) (PHYSDRAM | ((va) & ~KSEGM)) 11 12#define L1X(va) (((((va))>>20) & 0x0fff)<<2) 13 14/* 15 * new instructions 16 */ 17 18#define ISB \ 19 MOVW $0, R0; \ 20 MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEwait 21 22#define DSB \ 23 MOVW $0, R0; \ 24 MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEwait 25 26#define BARRIERS DSB; ISB 27 28#define MCRR(coproc, op, rd, rn, crm) \ 29 WORD $(0xec400000|(rn)<<16|(rd)<<12|(coproc)<<8|(op)<<4|(crm)) 30#define MRRC(coproc, op, rd, rn, crm) \ 31 WORD $(0xec500000|(rn)<<16|(rd)<<12|(coproc)<<8|(op)<<4|(crm)) 32#define MSR(R, rn, m, m1) \ 33 WORD $(0xe120f200|(R)<<22|(m1)<<16|(m)<<8|(rn)) 34 35#define LDREX(fp,t) WORD $(0xe<<28|0x01900f9f | (fp)<<16 | (t)<<12) 36/* `The order of operands is from left to right in dataflow order' - asm man */ 37#define STREX(f,tp,r) WORD $(0xe<<28|0x01800f90 | (tp)<<16 | (r)<<12 | (f)<<0) 38#define CLREX WORD $0xf57ff01f 39 40#define CPSIE WORD $0xf1080080 /* intr enable: zeroes I bit */ 41#define CPSID WORD $0xf10c0080 /* intr disable: sets I bit */ 42 43#define OKAY \ 44 MOVW $0x7E200028,R2; \ 45 MOVW $0x10000,R3; \ 46 MOVW R3,(R2) 47 48#define PUTC(s) 49 50/* 51 * get cpu id, or zero if armv6 52 */ 53#define CPUID(r) \ 54 MRC CpSC, 0, r, C(CpID), C(CpIDfeat), 7; \ 55 CMP $0, r; \ 56 B.EQ 2(PC); \ 57 MRC CpSC, 0, r, C(CpID), C(CpIDidct), CpIDmpid; \ 58 AND.S $(MAXMACH-1), r 59 60