1 /* 2 * arm-specific definitions for armv6 (arm11), armv7 (cortex-a8 and -a7) 3 * these are used in C and assembler 4 */ 5 6 /* 7 * Program Status Registers 8 */ 9 #define PsrMusr 0x00000010 /* mode */ 10 #define PsrMfiq 0x00000011 11 #define PsrMirq 0x00000012 12 #define PsrMsvc 0x00000013 /* `protected mode for OS' */ 13 #define PsrMmon 0x00000016 /* `secure monitor' (trustzone hyper) */ 14 #define PsrMabt 0x00000017 15 #define PsrMhyp 0x0000001A 16 #define PsrMund 0x0000001B 17 #define PsrMsys 0x0000001F /* `privileged user mode for OS' (trustzone) */ 18 #define PsrMask 0x0000001F 19 20 #define PsrDfiq 0x00000040 /* disable FIQ interrupts */ 21 #define PsrDirq 0x00000080 /* disable IRQ interrupts */ 22 23 #define PsrV 0x10000000 /* overflow */ 24 #define PsrC 0x20000000 /* carry/borrow/extend */ 25 #define PsrZ 0x40000000 /* zero */ 26 #define PsrN 0x80000000 /* negative/less than */ 27 28 /* instruction decoding */ 29 #define ISCPOP(op) ((op) == 0xE || ((op) & ~1) == 0xC) 30 #define ISFPAOP(cp, op) ((cp) == CpOFPA && ISCPOP(op)) 31 #define ISVFPOP(cp, op) (((cp) == CpDFP || (cp) == CpFP) && ISCPOP(op)) 32 33 /* 34 * Coprocessors 35 */ 36 #define CpOFPA 1 /* ancient 7500 FPA */ 37 #define CpFP 10 /* float FP, VFP cfg. */ 38 #define CpDFP 11 /* double FP */ 39 #define CpSC 15 /* System Control */ 40 41 /* 42 * Primary (CRn) CpSC registers. 43 */ 44 #define CpID 0 /* ID and cache type */ 45 #define CpCONTROL 1 /* miscellaneous control */ 46 #define CpTTB 2 /* Translation Table Base(s) */ 47 #define CpDAC 3 /* Domain Access Control */ 48 #define CpFSR 5 /* Fault Status */ 49 #define CpFAR 6 /* Fault Address */ 50 #define CpCACHE 7 /* cache/write buffer control */ 51 #define CpTLB 8 /* TLB control */ 52 #define CpCLD 9 /* L2 Cache Lockdown, op1==1 */ 53 #define CpTLD 10 /* TLB Lockdown, with op2 */ 54 #define CpVECS 12 /* vector bases, op1==0, Crm==0, op2s (cortex) */ 55 #define CpPID 13 /* Process ID */ 56 #define CpTIMER 14 /* Generic timer (cortex-a7) */ 57 #define CpSPM 15 /* system performance monitor (arm1176) */ 58 59 /* 60 * CpTIMER op1==0 Crm and opcode2 registers (cortex-a7) 61 */ 62 #define CpTIMERcntfrq 0 63 #define CpTIMERphys 2 64 65 #define CpTIMERphysval 0 66 #define CpTIMERphysctl 1 67 68 /* 69 * CpTTB op1==0, Crm==0 opcode2 values. 70 */ 71 #define CpTTB0 0 72 #define CpTTB1 1 /* cortex */ 73 #define CpTTBctl 2 /* cortex */ 74 75 /* 76 * CpFSR opcode2 values. 77 */ 78 #define CpFSRdata 0 /* armv6, armv7 */ 79 #define CpFSRinst 1 /* armv6, armv7 */ 80 81 /* 82 * CpID Secondary (CRm) registers. 83 */ 84 #define CpIDidct 0 85 #define CpIDfeat 1 86 87 /* 88 * CpID op1==0 opcode2 fields. 89 * the cortex has more op1 codes for cache size, etc. 90 */ 91 #define CpIDid 0 /* main ID */ 92 #define CpIDct 1 /* cache type */ 93 #define CpIDtlb 3 /* tlb type (cortex) */ 94 #define CpIDmpid 5 /* multiprocessor id (cortex) */ 95 #define CpIDrevid 6 /* extra revision ID */ 96 97 /* CpIDid op1 values */ 98 #define CpIDcsize 1 /* cache size (cortex) */ 99 #define CpIDcssel 2 /* cache size select (cortex) */ 100 101 /* 102 * CpCONTROL op2 codes, op1==0, Crm==0. 103 */ 104 #define CpMainctl 0 105 #define CpAuxctl 1 106 #define CpCPaccess 2 107 108 /* 109 * CpCONTROL: op1==0, CRm==0, op2==CpMainctl. 110 * main control register. 111 * cortex/armv7 has more ops and CRm values. 112 */ 113 #define CpCmmu 0x00000001 /* M: MMU enable */ 114 #define CpCalign 0x00000002 /* A: alignment fault enable */ 115 #define CpCdcache 0x00000004 /* C: data cache on */ 116 #define CpCsbo (3<<22|1<<18|1<<16|017<<3) /* must be 1 (armv7) */ 117 #define CpCsbz (CpCtre|1<<26|CpCve|1<<15|7<<7) /* must be 0 (armv7) */ 118 #define CpCsw (1<<10) /* SW: SWP(B) enable (deprecated in v7) */ 119 #define CpCpredict 0x00000800 /* Z: branch prediction (armv7) */ 120 #define CpCicache 0x00001000 /* I: instruction cache on */ 121 #define CpChv 0x00002000 /* V: high vectors */ 122 #define CpCrr (1<<14) /* RR: round robin vs random cache replacement */ 123 #define CpCha (1<<17) /* HA: hw access flag enable */ 124 #define CpCdz (1<<19) /* DZ: divide by zero fault enable */ 125 #define CpCfi (1<<21) /* FI: fast intrs */ 126 #define CpCve (1<<24) /* VE: intr vectors enable */ 127 #define CpCee (1<<25) /* EE: exception endianness */ 128 #define CpCnmfi (1<<27) /* NMFI: non-maskable fast intrs. */ 129 #define CpCtre (1<<28) /* TRE: TEX remap enable */ 130 #define CpCafe (1<<29) /* AFE: access flag (ttb) enable */ 131 132 /* 133 * CpCONTROL: op1==0, CRm==0, op2==CpAuxctl. 134 * Auxiliary control register on cortex at least. 135 */ 136 #define CpACcachenopipe (1<<20) /* don't pipeline cache maint. */ 137 #define CpACcp15serial (1<<18) /* serialise CP1[45] ops. */ 138 #define CpACcp15waitidle (1<<17) /* CP1[45] wait-on-idle */ 139 #define CpACcp15pipeflush (1<<16) /* CP1[45] flush pipeline */ 140 #define CpACneonissue1 (1<<12) /* neon single issue */ 141 #define CpACldstissue1 (1<<11) /* force single issue ld, st */ 142 #define CpACissue1 (1<<10) /* force single issue */ 143 #define CpACnobsm (1<<7) /* no branch size mispredicts */ 144 #define CpACibe (1<<6) /* cp15 invalidate & btb enable */ 145 #define CpACl1neon (1<<5) /* cache neon (FP) data in L1 cache */ 146 #define CpACasa (1<<4) /* enable speculative accesses */ 147 #define CpACl1pe (1<<3) /* l1 cache parity enable */ 148 #define CpACl2en (1<<1) /* l2 cache enable; default 1 */ 149 150 /* cortex-a7 and cortex-a9 */ 151 #define CpACsmp (1<<6) /* SMP l1 caches coherence; needed for ldrex/strex */ 152 #define CpACl1pctl (3<<13) /* l1 prefetch control */ 153 /* 154 * CpCONTROL Secondary (CRm) registers and opcode2 fields. 155 */ 156 #define CpCONTROLscr 1 157 158 #define CpSCRscr 0 159 160 /* 161 * CpCACHE Secondary (CRm) registers and opcode2 fields. op1==0. 162 * In ARM-speak, 'flush' means invalidate and 'clean' means writeback. 163 */ 164 #define CpCACHEintr 0 /* interrupt (op2==4) */ 165 #define CpCACHEisi 1 /* inner-sharable I cache (v7) */ 166 #define CpCACHEpaddr 4 /* 0: phys. addr (cortex) */ 167 #define CpCACHEinvi 5 /* instruction, branch table */ 168 #define CpCACHEinvd 6 /* data or unified */ 169 #define CpCACHEinvu 7 /* unified (not on cortex) */ 170 #define CpCACHEva2pa 8 /* va -> pa translation (cortex) */ 171 #define CpCACHEwb 10 /* writeback to PoC */ 172 #define CpCACHEwbu 11 /* writeback to PoU */ 173 #define CpCACHEwbi 14 /* writeback+invalidate (to PoC) */ 174 175 #define CpCACHEall 0 /* entire (not for invd nor wb(i) on cortex) */ 176 #define CpCACHEse 1 /* single entry */ 177 #define CpCACHEsi 2 /* set/index (set/way) */ 178 #define CpCACHEtest 3 /* test loop */ 179 #define CpCACHEwait 4 /* wait (prefetch flush on cortex) */ 180 #define CpCACHEdmbarr 5 /* wb only (cortex) */ 181 #define CpCACHEflushbtc 6 /* flush branch-target cache (cortex) */ 182 #define CpCACHEflushbtse 7 /* ⋯ or just one entry in it (cortex) */ 183 184 /* 185 * CpTLB Secondary (CRm) registers and opcode2 fields. 186 */ 187 #define CpTLBinvi 5 /* instruction */ 188 #define CpTLBinvd 6 /* data */ 189 #define CpTLBinvu 7 /* unified */ 190 191 #define CpTLBinv 0 /* invalidate all */ 192 #define CpTLBinvse 1 /* invalidate single entry */ 193 #define CpTBLasid 2 /* by ASID (cortex) */ 194 195 /* 196 * CpCLD Secondary (CRm) registers and opcode2 fields for op1==0. (cortex) 197 */ 198 #define CpCLDena 12 /* enables */ 199 #define CpCLDcyc 13 /* cycle counter */ 200 #define CpCLDuser 14 /* user enable */ 201 202 #define CpCLDenapmnc 0 203 #define CpCLDenacyc 1 204 205 /* 206 * CpCLD Secondary (CRm) registers and opcode2 fields for op1==1. 207 */ 208 #define CpCLDl2 0 /* l2 cache */ 209 210 #define CpCLDl2aux 2 /* auxiliary control */ 211 212 /* 213 * l2 cache aux. control 214 */ 215 #define CpCl2ecc (1<<28) /* use ecc, not parity */ 216 #define CpCl2noldforw (1<<27) /* no ld forwarding */ 217 #define CpCl2nowrcomb (1<<25) /* no write combining */ 218 #define CpCl2nowralldel (1<<24) /* no write allocate delay */ 219 #define CpCl2nowrallcomb (1<<23) /* no write allocate combine */ 220 #define CpCl2nowralloc (1<<22) /* no write allocate */ 221 #define CpCl2eccparity (1<<21) /* enable ecc or parity */ 222 #define CpCl2inner (1<<16) /* inner cacheability */ 223 /* other bits are tag ram & data ram latencies */ 224 225 /* 226 * CpTLD Secondary (CRm) registers and opcode2 fields. 227 */ 228 #define CpTLDlock 0 /* TLB lockdown registers */ 229 #define CpTLDpreload 1 /* TLB preload */ 230 231 #define CpTLDi 0 /* TLB instr. lockdown reg. */ 232 #define CpTLDd 1 /* " data " " */ 233 234 /* 235 * CpVECS Secondary (CRm) registers and opcode2 fields. 236 */ 237 #define CpVECSbase 0 238 239 #define CpVECSnorm 0 /* (non-)secure base addr */ 240 #define CpVECSmon 1 /* secure monitor base addr */ 241 242 /* 243 * CpSPM Secondary (CRm) registers and opcode2 fields (armv6) 244 */ 245 #define CpSPMperf 12 /* various counters */ 246 247 #define CpSPMctl 0 /* performance monitor control */ 248 #define CpSPMcyc 1 /* cycle counter register */ 249 250 /* 251 * CpCACHERANGE opcode2 fields for MCRR instruction (armv6) 252 */ 253 #define CpCACHERANGEinvi 5 /* invalidate instruction */ 254 #define CpCACHERANGEinvd 6 /* invalidate data */ 255 #define CpCACHERANGEdwb 12 /* writeback */ 256 #define CpCACHERANGEdwbi 14 /* writeback+invalidate */ 257 258 /* 259 * CpTTB cache control bits 260 */ 261 #define CpTTBnos (1<<5) /* only Inner cache shareable */ 262 #define CpTTBinc (0<<0|0<<6) /* inner non-cacheable */ 263 #define CpTTBiwba (0<<0|1<<6) /* inner write-back write-allocate */ 264 #define CpTTBiwt (1<<0|0<<6) /* inner write-through */ 265 #define CpTTBiwb (1<<0|1<<6) /* inner write-back no write-allocate */ 266 #define CpTTBonc (0<<3) /* outer non-cacheable */ 267 #define CpTTBowba (1<<3) /* outer write-back write-allocate */ 268 #define CpTTBowt (2<<3) /* outer write-through */ 269 #define CpTTBowb (3<<3) /* outer write-back no write-allocate */ 270 #define CpTTBs (1<<1) /* page table in shareable memory */ 271 #define CpTTBbase ~0x7F /* mask off control bits */ 272 273 /* 274 * MMU page table entries. 275 * Mbz (0x10) bit is implementation-defined and must be 0 on the cortex. 276 */ 277 #define Mbz (0<<4) 278 #define Fault 0x00000000 /* L[12] pte: unmapped */ 279 280 #define Coarse (Mbz|1) /* L1 */ 281 #define Section (Mbz|2) /* L1 1MB */ 282 #define Fine (Mbz|3) /* L1 */ 283 #define Super (1<<18) /* L1 16MB */ 284 285 #define Large 0x00000001 /* L2 64KB */ 286 #define Small 0x00000002 /* L2 4KB */ 287 #define Tiny 0x00000003 /* L2 1KB: not in v7 */ 288 #define Buffered 0x00000004 /* L[12]: write-back not -thru */ 289 #define Cached 0x00000008 /* L[12] */ 290 #define Dom0 0 291 292 #define L1wralloc (1<<12) /* L1 TEX */ 293 #define L1sharable (1<<16) 294 #define L1noexec (1<<4) 295 #define L2wralloc (1<<6) /* L2 TEX (small pages) */ 296 #define L2sharable (1<<10) 297 298 /* attributes for memory containing locks -- differs between armv6 and armv7 */ 299 //#define L1ptedramattrs (Cached | Buffered | L1wralloc | L1sharable) 300 //#define L2ptedramattrs (Cached | Buffered | L2wralloc | L2sharable) 301 302 #define Noaccess 0 /* AP, DAC */ 303 #define Krw 1 /* AP */ 304 /* armv7 deprecates AP[2] == 1 & AP[1:0] == 2 (Uro), prefers 3 (new in v7) */ 305 #define Uro 2 /* AP */ 306 #define Urw 3 /* AP */ 307 #define Client 1 /* DAC */ 308 #define Manager 3 /* DAC */ 309 310 #define F(v, o, w) (((v) & ((1<<(w))-1))<<(o)) 311 #define AP(n, v) F((v), ((n)*2)+4, 2) 312 #define L1AP(ap) (AP(3, (ap))) 313 /* L2AP differs between armv6 and armv7 -- see l2ap in arch*.c */ 314 #define DAC(n, v) F((v), (n)*2, 2) 315 316 #define HVECTORS 0xffff0000 317