1 /* $OpenBSD: sdhc.c,v 1.75 2023/04/19 02:01:02 dlg Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * SD Host Controller driver based on the SD Host Controller Standard 21 * Simplified Specification Version 1.00 (www.sdcard.org). 22 */ 23 24 #include <sys/param.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/malloc.h> 28 #include <sys/proc.h> 29 #include <sys/systm.h> 30 #include <sys/time.h> 31 32 #include <dev/sdmmc/sdhcreg.h> 33 #include <dev/sdmmc/sdhcvar.h> 34 #include <dev/sdmmc/sdmmcchip.h> 35 #include <dev/sdmmc/sdmmcreg.h> 36 #include <dev/sdmmc/sdmmcvar.h> 37 #include <dev/sdmmc/sdmmc_ioreg.h> 38 39 /* Timeouts in seconds */ 40 #define SDHC_COMMAND_TIMEOUT 1 41 #define SDHC_BUFFER_TIMEOUT 1 42 #define SDHC_TRANSFER_TIMEOUT 1 43 #define SDHC_DMA_TIMEOUT 3 44 45 struct sdhc_host { 46 struct sdhc_softc *sc; /* host controller device */ 47 struct device *sdmmc; /* generic SD/MMC device */ 48 bus_space_tag_t iot; /* host register set tag */ 49 bus_space_handle_t ioh; /* host register set handle */ 50 u_int16_t version; /* specification version */ 51 u_int clkbase; /* base clock frequency in KHz */ 52 int maxblklen; /* maximum block length */ 53 int flags; /* flags for this host */ 54 u_int32_t ocr; /* OCR value from capabilities */ 55 u_int8_t regs[14]; /* host controller state */ 56 u_int16_t intr_status; /* soft interrupt status */ 57 u_int16_t intr_error_status; /* soft error status */ 58 59 bus_dmamap_t adma_map; 60 bus_dma_segment_t adma_segs[1]; 61 caddr_t adma2; 62 63 uint16_t block_size; 64 uint16_t block_count; 65 uint16_t transfer_mode; 66 }; 67 68 /* flag values */ 69 #define SHF_USE_DMA 0x0001 70 #define SHF_USE_DMA64 0x0002 71 #define SHF_USE_32BIT_ACCESS 0x0004 72 73 #define HREAD1(hp, reg) \ 74 (sdhc_read_1((hp), (reg))) 75 #define HREAD2(hp, reg) \ 76 (sdhc_read_2((hp), (reg))) 77 #define HREAD4(hp, reg) \ 78 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 79 #define HWRITE1(hp, reg, val) \ 80 sdhc_write_1((hp), (reg), (val)) 81 #define HWRITE2(hp, reg, val) \ 82 sdhc_write_2((hp), (reg), (val)) 83 #define HWRITE4(hp, reg, val) \ 84 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 85 #define HCLR1(hp, reg, bits) \ 86 HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)) 87 #define HCLR2(hp, reg, bits) \ 88 HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)) 89 #define HSET1(hp, reg, bits) \ 90 HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)) 91 #define HSET2(hp, reg, bits) \ 92 HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)) 93 94 int sdhc_host_reset(sdmmc_chipset_handle_t); 95 u_int32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 96 int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 97 int sdhc_card_detect(sdmmc_chipset_handle_t); 98 int sdhc_bus_power(sdmmc_chipset_handle_t, u_int32_t); 99 int sdhc_bus_clock(sdmmc_chipset_handle_t, int, int); 100 int sdhc_bus_width(sdmmc_chipset_handle_t, int); 101 void sdhc_card_intr_mask(sdmmc_chipset_handle_t, int); 102 void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 103 int sdhc_signal_voltage(sdmmc_chipset_handle_t, int); 104 void sdhc_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *); 105 int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 106 int sdhc_wait_state(struct sdhc_host *, u_int32_t, u_int32_t); 107 int sdhc_soft_reset(struct sdhc_host *, int); 108 int sdhc_wait_intr_cold(struct sdhc_host *, int, int); 109 int sdhc_wait_intr(struct sdhc_host *, int, int); 110 void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 111 void sdhc_read_data(struct sdhc_host *, u_char *, int); 112 void sdhc_write_data(struct sdhc_host *, u_char *, int); 113 int sdhc_hibernate_init(sdmmc_chipset_handle_t, void *); 114 115 #ifdef SDHC_DEBUG 116 int sdhcdebug = 0; 117 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 118 void sdhc_dump_regs(struct sdhc_host *); 119 #else 120 #define DPRINTF(n,s) do {} while(0) 121 #endif 122 123 struct sdmmc_chip_functions sdhc_functions = { 124 .host_reset = sdhc_host_reset, 125 .host_ocr = sdhc_host_ocr, 126 .host_maxblklen = sdhc_host_maxblklen, 127 .card_detect = sdhc_card_detect, 128 .bus_power = sdhc_bus_power, 129 .bus_clock = sdhc_bus_clock, 130 .bus_width = sdhc_bus_width, 131 .exec_command = sdhc_exec_command, 132 .card_intr_mask = sdhc_card_intr_mask, 133 .card_intr_ack = sdhc_card_intr_ack, 134 .signal_voltage = sdhc_signal_voltage, 135 .hibernate_init = sdhc_hibernate_init, 136 }; 137 138 struct cfdriver sdhc_cd = { 139 NULL, "sdhc", DV_DULL 140 }; 141 142 /* 143 * Some controllers live on a bus that only allows 32-bit 144 * transactions. In that case we use a RMW cycle for 8-bit and 16-bit 145 * register writes. However that doesn't work for the Transfer Mode 146 * register as this register lives in the same 32-bit word as the 147 * Command register and writing the Command register triggers SD 148 * command generation. We avoid this issue by using a shadow variable 149 * for the Transfer Mode register that we write out when we write the 150 * Command register. 151 * 152 * The Arasan controller integrated on the Broadcom SoCs 153 * used in the Raspberry Pi has an interesting bug where writing the 154 * same 32-bit register twice doesn't work. This means that we lose 155 * writes to the Block Sine and/or Block Count register. We work 156 * around that issue by using shadow variables as well. 157 */ 158 159 uint8_t 160 sdhc_read_1(struct sdhc_host *hp, bus_size_t offset) 161 { 162 uint32_t reg; 163 164 if (hp->flags & SHF_USE_32BIT_ACCESS) { 165 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~3); 166 return (reg >> ((offset & 3) * 8)) & 0xff; 167 } 168 169 return bus_space_read_1(hp->iot, hp->ioh, offset); 170 } 171 172 uint16_t 173 sdhc_read_2(struct sdhc_host *hp, bus_size_t offset) 174 { 175 uint32_t reg; 176 177 if (hp->flags & SHF_USE_32BIT_ACCESS) { 178 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~2); 179 return (reg >> ((offset & 2) * 8)) & 0xffff; 180 } 181 182 return bus_space_read_2(hp->iot, hp->ioh, offset); 183 } 184 185 void 186 sdhc_write_1(struct sdhc_host *hp, bus_size_t offset, uint8_t value) 187 { 188 uint32_t reg; 189 190 if (hp->flags & SHF_USE_32BIT_ACCESS) { 191 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~3); 192 reg &= ~(0xff << ((offset & 3) * 8)); 193 reg |= (value << ((offset & 3) * 8)); 194 bus_space_write_4(hp->iot, hp->ioh, offset & ~3, reg); 195 return; 196 } 197 198 bus_space_write_1(hp->iot, hp->ioh, offset, value); 199 } 200 201 void 202 sdhc_write_2(struct sdhc_host *hp, bus_size_t offset, uint16_t value) 203 { 204 uint32_t reg; 205 206 if (hp->flags & SHF_USE_32BIT_ACCESS) { 207 switch (offset) { 208 case SDHC_BLOCK_SIZE: 209 hp->block_size = value; 210 return; 211 case SDHC_BLOCK_COUNT: 212 hp->block_count = value; 213 return; 214 case SDHC_TRANSFER_MODE: 215 hp->transfer_mode = value; 216 return; 217 case SDHC_COMMAND: 218 bus_space_write_4(hp->iot, hp->ioh, SDHC_BLOCK_SIZE, 219 (hp->block_count << 16) | hp->block_size); 220 bus_space_write_4(hp->iot, hp->ioh, SDHC_TRANSFER_MODE, 221 (value << 16) | hp->transfer_mode); 222 return; 223 } 224 225 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~2); 226 reg &= ~(0xffff << ((offset & 2) * 8)); 227 reg |= (value << ((offset & 2) * 8)); 228 bus_space_write_4(hp->iot, hp->ioh, offset & ~2, reg); 229 return; 230 } 231 232 bus_space_write_2(hp->iot, hp->ioh, offset, value); 233 } 234 235 /* 236 * Called by attachment driver. For each SD card slot there is one SD 237 * host controller standard register set. (1.3) 238 */ 239 int 240 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 241 bus_space_handle_t ioh, bus_size_t iosize, int usedma, uint64_t capmask, 242 uint64_t capset) 243 { 244 struct sdmmcbus_attach_args saa; 245 struct sdhc_host *hp; 246 uint32_t caps; 247 int error = 1; 248 int max_clock; 249 250 /* Allocate one more host structure. */ 251 sc->sc_nhosts++; 252 hp = malloc(sizeof(*hp), M_DEVBUF, M_WAITOK | M_ZERO); 253 sc->sc_host[sc->sc_nhosts - 1] = hp; 254 255 if (ISSET(sc->sc_flags, SDHC_F_32BIT_ACCESS)) 256 SET(hp->flags, SHF_USE_32BIT_ACCESS); 257 258 /* Fill in the new host structure. */ 259 hp->sc = sc; 260 hp->iot = iot; 261 hp->ioh = ioh; 262 263 /* Store specification version. */ 264 hp->version = HREAD2(hp, SDHC_HOST_CTL_VERSION); 265 266 /* 267 * Reset the host controller and enable interrupts. 268 */ 269 (void)sdhc_host_reset(hp); 270 271 /* Determine host capabilities. */ 272 caps = HREAD4(hp, SDHC_CAPABILITIES); 273 caps &= ~capmask; 274 caps |= capset; 275 276 /* Use DMA if the host system and the controller support it. */ 277 if (usedma && ISSET(caps, SDHC_ADMA2_SUPP)) { 278 SET(hp->flags, SHF_USE_DMA); 279 if (ISSET(caps, SDHC_64BIT_DMA_SUPP)) 280 SET(hp->flags, SHF_USE_DMA64); 281 } 282 283 /* 284 * Determine the base clock frequency. (2.2.24) 285 */ 286 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 287 /* SDHC 3.0 supports 10-255 MHz. */ 288 max_clock = 255000; 289 if (SDHC_BASE_FREQ_KHZ_V3(caps) != 0) 290 hp->clkbase = SDHC_BASE_FREQ_KHZ_V3(caps); 291 } else { 292 /* SDHC 1.0/2.0 supports only 10-63 MHz. */ 293 max_clock = 63000; 294 if (SDHC_BASE_FREQ_KHZ(caps) != 0) 295 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 296 } 297 if (hp->clkbase == 0) { 298 /* Make sure we can clock down to 400 kHz. */ 299 max_clock = 400 * SDHC_SDCLK_DIV_MAX_V3; 300 hp->clkbase = sc->sc_clkbase; 301 } 302 if (hp->clkbase == 0) { 303 /* The attachment driver must tell us. */ 304 printf("%s: base clock frequency unknown\n", 305 sc->sc_dev.dv_xname); 306 goto err; 307 } else if (hp->clkbase < 10000 || hp->clkbase > max_clock) { 308 printf("%s: base clock frequency out of range: %u MHz\n", 309 sc->sc_dev.dv_xname, hp->clkbase / 1000); 310 goto err; 311 } 312 313 printf("%s: SDHC %d.0, %d MHz base clock\n", DEVNAME(sc), 314 SDHC_SPEC_VERSION(hp->version) + 1, hp->clkbase / 1000); 315 316 /* 317 * XXX Set the data timeout counter value according to 318 * capabilities. (2.2.15) 319 */ 320 321 /* 322 * Determine SD bus voltage levels supported by the controller. 323 */ 324 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)) 325 SET(hp->ocr, MMC_OCR_1_65V_1_95V); 326 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) 327 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 328 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) 329 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 330 331 /* 332 * Determine the maximum block length supported by the host 333 * controller. (2.2.24) 334 */ 335 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 336 case SDHC_MAX_BLK_LEN_512: 337 hp->maxblklen = 512; 338 break; 339 case SDHC_MAX_BLK_LEN_1024: 340 hp->maxblklen = 1024; 341 break; 342 case SDHC_MAX_BLK_LEN_2048: 343 hp->maxblklen = 2048; 344 break; 345 default: 346 hp->maxblklen = 1; 347 break; 348 } 349 350 if (ISSET(hp->flags, SHF_USE_DMA)) { 351 int rseg; 352 353 /* Allocate ADMA2 descriptor memory */ 354 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 355 PAGE_SIZE, hp->adma_segs, 1, &rseg, 356 BUS_DMA_WAITOK | BUS_DMA_ZERO); 357 if (error) 358 goto adma_done; 359 error = bus_dmamem_map(sc->sc_dmat, hp->adma_segs, rseg, 360 PAGE_SIZE, &hp->adma2, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 361 if (error) { 362 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg); 363 goto adma_done; 364 } 365 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 366 0, BUS_DMA_WAITOK, &hp->adma_map); 367 if (error) { 368 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE); 369 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg); 370 goto adma_done; 371 } 372 error = bus_dmamap_load(sc->sc_dmat, hp->adma_map, 373 hp->adma2, PAGE_SIZE, NULL, 374 BUS_DMA_WAITOK | BUS_DMA_WRITE); 375 if (error) { 376 bus_dmamap_destroy(sc->sc_dmat, hp->adma_map); 377 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE); 378 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg); 379 goto adma_done; 380 } 381 382 adma_done: 383 if (error) { 384 printf("%s: can't allocate DMA descriptor table\n", 385 DEVNAME(hp->sc)); 386 CLR(hp->flags, SHF_USE_DMA); 387 } 388 } 389 390 /* 391 * Attach the generic SD/MMC bus driver. (The bus driver must 392 * not invoke any chipset functions before it is attached.) 393 */ 394 bzero(&saa, sizeof(saa)); 395 saa.saa_busname = "sdmmc"; 396 saa.sct = &sdhc_functions; 397 saa.sch = hp; 398 saa.caps = SMC_CAPS_4BIT_MODE; 399 saa.dmat = sc->sc_dmat; 400 saa.dma_boundary = sc->sc_dma_boundary; 401 if (ISSET(hp->flags, SHF_USE_DMA)) 402 saa.caps |= SMC_CAPS_DMA; 403 404 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 405 saa.caps |= SMC_CAPS_SD_HIGHSPEED; 406 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 407 saa.caps |= SMC_CAPS_MMC_HIGHSPEED; 408 409 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 410 uint32_t caps2 = HREAD4(hp, SDHC_CAPABILITIES2); 411 caps2 &= ~(capmask >> 32); 412 caps2 |= capset >> 32; 413 414 if (ISSET(caps, SDHC_8BIT_MODE_SUPP)) 415 saa.caps |= SMC_CAPS_8BIT_MODE; 416 417 if (ISSET(caps2, SDHC_DDR50_SUPP)) 418 saa.caps |= SMC_CAPS_MMC_DDR52; 419 } 420 421 if (ISSET(sc->sc_flags, SDHC_F_NONREMOVABLE)) 422 saa.caps |= SMC_CAPS_NONREMOVABLE; 423 424 hp->sdmmc = config_found(&sc->sc_dev, &saa, NULL); 425 if (hp->sdmmc == NULL) { 426 error = 0; 427 goto err; 428 } 429 430 return 0; 431 432 err: 433 free(hp, M_DEVBUF, sizeof *hp); 434 sc->sc_host[sc->sc_nhosts - 1] = NULL; 435 sc->sc_nhosts--; 436 return (error); 437 } 438 439 int 440 sdhc_activate(struct device *self, int act) 441 { 442 struct sdhc_softc *sc = (struct sdhc_softc *)self; 443 struct sdhc_host *hp; 444 int n, i, rv = 0; 445 446 switch (act) { 447 case DVACT_SUSPEND: 448 rv = config_activate_children(self, act); 449 450 /* Save the host controller state. */ 451 for (n = 0; n < sc->sc_nhosts; n++) { 452 hp = sc->sc_host[n]; 453 for (i = 0; i < sizeof hp->regs; i++) 454 hp->regs[i] = HREAD1(hp, i); 455 } 456 break; 457 case DVACT_RESUME: 458 /* Restore the host controller state. */ 459 for (n = 0; n < sc->sc_nhosts; n++) { 460 hp = sc->sc_host[n]; 461 (void)sdhc_host_reset(hp); 462 for (i = 0; i < sizeof hp->regs; i++) 463 HWRITE1(hp, i, hp->regs[i]); 464 } 465 rv = config_activate_children(self, act); 466 break; 467 case DVACT_POWERDOWN: 468 rv = config_activate_children(self, act); 469 sdhc_shutdown(self); 470 break; 471 default: 472 rv = config_activate_children(self, act); 473 break; 474 } 475 return (rv); 476 } 477 478 /* 479 * Shutdown hook established by or called from attachment driver. 480 */ 481 void 482 sdhc_shutdown(void *arg) 483 { 484 struct sdhc_softc *sc = arg; 485 struct sdhc_host *hp; 486 int i; 487 488 /* XXX chip locks up if we don't disable it before reboot. */ 489 for (i = 0; i < sc->sc_nhosts; i++) { 490 hp = sc->sc_host[i]; 491 (void)sdhc_host_reset(hp); 492 } 493 } 494 495 /* 496 * Reset the host controller. Called during initialization, when 497 * cards are removed, upon resume, and during error recovery. 498 */ 499 int 500 sdhc_host_reset(sdmmc_chipset_handle_t sch) 501 { 502 struct sdhc_host *hp = sch; 503 u_int16_t imask; 504 int error; 505 int s; 506 507 s = splsdmmc(); 508 509 /* Disable all interrupts. */ 510 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 511 512 /* 513 * Reset the entire host controller and wait up to 100ms for 514 * the controller to clear the reset bit. 515 */ 516 if ((error = sdhc_soft_reset(hp, SDHC_RESET_ALL)) != 0) { 517 splx(s); 518 return (error); 519 } 520 521 /* Set data timeout counter value to max for now. */ 522 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 523 524 /* Enable interrupts. */ 525 imask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 526 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 527 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 528 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 529 530 HWRITE2(hp, SDHC_NINTR_STATUS_EN, imask); 531 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 532 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, imask); 533 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 534 535 splx(s); 536 return 0; 537 } 538 539 u_int32_t 540 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 541 { 542 struct sdhc_host *hp = sch; 543 return hp->ocr; 544 } 545 546 int 547 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 548 { 549 struct sdhc_host *hp = sch; 550 return hp->maxblklen; 551 } 552 553 /* 554 * Return non-zero if the card is currently inserted. 555 */ 556 int 557 sdhc_card_detect(sdmmc_chipset_handle_t sch) 558 { 559 struct sdhc_host *hp = sch; 560 561 if (hp->sc->sc_card_detect) 562 return hp->sc->sc_card_detect(hp->sc); 563 564 return ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED) ? 565 1 : 0; 566 } 567 568 /* 569 * Set or change SD bus voltage and enable or disable SD bus power. 570 * Return zero on success. 571 */ 572 int 573 sdhc_bus_power(sdmmc_chipset_handle_t sch, u_int32_t ocr) 574 { 575 struct sdhc_host *hp = sch; 576 u_int8_t vdd; 577 int s; 578 579 s = splsdmmc(); 580 581 /* 582 * Disable bus power before voltage change. 583 */ 584 if (!(hp->sc->sc_flags & SDHC_F_NOPWR0)) 585 HWRITE1(hp, SDHC_POWER_CTL, 0); 586 587 /* If power is disabled, reset the host and return now. */ 588 if (ocr == 0) { 589 splx(s); 590 (void)sdhc_host_reset(hp); 591 return 0; 592 } 593 594 /* 595 * Select the maximum voltage according to capabilities. 596 */ 597 ocr &= hp->ocr; 598 if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) 599 vdd = SDHC_VOLTAGE_3_3V; 600 else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) 601 vdd = SDHC_VOLTAGE_3_0V; 602 else if (ISSET(ocr, MMC_OCR_1_65V_1_95V)) 603 vdd = SDHC_VOLTAGE_1_8V; 604 else { 605 /* Unsupported voltage level requested. */ 606 splx(s); 607 return EINVAL; 608 } 609 610 /* 611 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 612 * voltage ramp until power rises. 613 */ 614 HWRITE1(hp, SDHC_POWER_CTL, (vdd << SDHC_VOLTAGE_SHIFT) | 615 SDHC_BUS_POWER); 616 sdmmc_delay(10000); 617 618 /* 619 * The host system may not power the bus due to battery low, 620 * etc. In that case, the host controller should clear the 621 * bus power bit. 622 */ 623 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 624 splx(s); 625 return ENXIO; 626 } 627 628 splx(s); 629 return 0; 630 } 631 632 /* 633 * Return the smallest possible base clock frequency divisor value 634 * for the CLOCK_CTL register to produce `freq' (KHz). 635 */ 636 static int 637 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq) 638 { 639 int div; 640 641 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 642 if (hp->clkbase <= freq) 643 return 0; 644 645 for (div = 2; div <= SDHC_SDCLK_DIV_MAX_V3; div += 2) 646 if ((hp->clkbase / div) <= freq) 647 return (div / 2); 648 } else { 649 for (div = 1; div <= SDHC_SDCLK_DIV_MAX; div *= 2) 650 if ((hp->clkbase / div) <= freq) 651 return (div / 2); 652 } 653 654 /* No divisor found. */ 655 return -1; 656 } 657 658 /* 659 * Set or change SDCLK frequency or disable the SD clock. 660 * Return zero on success. 661 */ 662 int 663 sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing) 664 { 665 struct sdhc_host *hp = sch; 666 struct sdhc_softc *sc = hp->sc; 667 int s; 668 int div; 669 int sdclk; 670 int timo; 671 int error = 0; 672 673 s = splsdmmc(); 674 675 if (hp->sc->sc_bus_clock_pre) 676 hp->sc->sc_bus_clock_pre(hp->sc, freq, timing); 677 678 #ifdef DIAGNOSTIC 679 /* Must not stop the clock if commands are in progress. */ 680 if (ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK) && 681 sdhc_card_detect(hp)) 682 printf("sdhc_sdclk_frequency_select: command in progress\n"); 683 #endif 684 685 /* 686 * Stop SD clock before changing the frequency. 687 */ 688 HWRITE2(hp, SDHC_CLOCK_CTL, 0); 689 if (freq == SDMMC_SDCLK_OFF) 690 goto ret; 691 692 if (!ISSET(sc->sc_flags, SDHC_F_NO_HS_BIT)) { 693 if (timing == SDMMC_TIMING_LEGACY) 694 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 695 else 696 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 697 } 698 699 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 700 switch (timing) { 701 case SDMMC_TIMING_MMC_DDR52: 702 HCLR2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_MASK); 703 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_DDR50); 704 break; 705 } 706 } 707 708 /* 709 * Set the minimum base clock frequency divisor. 710 */ 711 if ((div = sdhc_clock_divisor(hp, freq)) < 0) { 712 /* Invalid base clock frequency or `freq' value. */ 713 error = EINVAL; 714 goto ret; 715 } 716 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) 717 sdclk = SDHC_SDCLK_DIV_V3(div); 718 else 719 sdclk = SDHC_SDCLK_DIV(div); 720 HWRITE2(hp, SDHC_CLOCK_CTL, sdclk); 721 722 /* 723 * Start internal clock. Wait 10ms for stabilization. 724 */ 725 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 726 for (timo = 1000; timo > 0; timo--) { 727 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), SDHC_INTCLK_STABLE)) 728 break; 729 sdmmc_delay(10); 730 } 731 if (timo == 0) { 732 error = ETIMEDOUT; 733 goto ret; 734 } 735 736 /* 737 * Enable SD clock. 738 */ 739 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 740 741 if (hp->sc->sc_bus_clock_post) 742 hp->sc->sc_bus_clock_post(hp->sc, freq, timing); 743 744 ret: 745 splx(s); 746 return error; 747 } 748 749 int 750 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 751 { 752 struct sdhc_host *hp = (struct sdhc_host *)sch; 753 int reg; 754 int s; 755 756 if (width != 1 && width != 4 && width != 8) 757 return EINVAL; 758 759 s = splsdmmc(); 760 761 reg = HREAD1(hp, SDHC_HOST_CTL); 762 reg &= ~SDHC_4BIT_MODE; 763 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 764 reg &= ~SDHC_8BIT_MODE; 765 } 766 if (width == 4) { 767 reg |= SDHC_4BIT_MODE; 768 } else if (width == 8) { 769 KASSERT(SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3); 770 reg |= SDHC_8BIT_MODE; 771 } 772 HWRITE1(hp, SDHC_HOST_CTL, reg); 773 774 splx(s); 775 776 return 0; 777 } 778 779 void 780 sdhc_card_intr_mask(sdmmc_chipset_handle_t sch, int enable) 781 { 782 struct sdhc_host *hp = sch; 783 784 if (enable) { 785 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 786 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 787 } else { 788 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 789 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 790 } 791 } 792 793 void 794 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 795 { 796 struct sdhc_host *hp = sch; 797 798 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 799 } 800 801 int 802 sdhc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 803 { 804 struct sdhc_host *hp = sch; 805 806 if (hp->sc->sc_signal_voltage) 807 return hp->sc->sc_signal_voltage(hp->sc, signal_voltage); 808 809 if (SDHC_SPEC_VERSION(hp->version) < SDHC_SPEC_V3) 810 return EINVAL; 811 812 switch (signal_voltage) { 813 case SDMMC_SIGNAL_VOLTAGE_180: 814 HSET2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN); 815 break; 816 case SDMMC_SIGNAL_VOLTAGE_330: 817 HCLR2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN); 818 break; 819 default: 820 return EINVAL; 821 } 822 823 /* Regulator output shall be stable within 5 ms. */ 824 sdmmc_delay(5000); 825 826 /* Host controller clears this bit if 1.8V signalling fails. */ 827 if (signal_voltage == SDMMC_SIGNAL_VOLTAGE_180 && 828 !ISSET(HREAD2(hp, SDHC_HOST_CTL2), SDHC_1_8V_SIGNAL_EN)) 829 return EIO; 830 831 return 0; 832 } 833 834 int 835 sdhc_wait_state(struct sdhc_host *hp, u_int32_t mask, u_int32_t value) 836 { 837 u_int32_t state; 838 int timeout; 839 840 for (timeout = 10; timeout > 0; timeout--) { 841 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) 842 == value) 843 return 0; 844 sdmmc_delay(10000); 845 } 846 DPRINTF(0,("%s: timeout waiting for %x (state=%b)\n", DEVNAME(hp->sc), 847 value, state, SDHC_PRESENT_STATE_BITS)); 848 return ETIMEDOUT; 849 } 850 851 void 852 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 853 { 854 struct sdhc_host *hp = sch; 855 int error; 856 857 /* 858 * Start the MMC command, or mark `cmd' as failed and return. 859 */ 860 error = sdhc_start_command(hp, cmd); 861 if (error != 0) { 862 cmd->c_error = error; 863 SET(cmd->c_flags, SCF_ITSDONE); 864 return; 865 } 866 867 /* 868 * Wait until the command phase is done, or until the command 869 * is marked done for any other reason. 870 */ 871 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, 872 SDHC_COMMAND_TIMEOUT)) { 873 cmd->c_error = ETIMEDOUT; 874 SET(cmd->c_flags, SCF_ITSDONE); 875 return; 876 } 877 878 /* 879 * The host controller removes bits [0:7] from the response 880 * data (CRC) and we pass the data up unchanged to the bus 881 * driver (without padding). 882 */ 883 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 884 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 885 u_char *p = (u_char *)cmd->c_resp; 886 int i; 887 888 for (i = 0; i < 15; i++) 889 *p++ = HREAD1(hp, SDHC_RESPONSE + i); 890 } else 891 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE); 892 } 893 894 /* 895 * If the command has data to transfer in any direction, 896 * execute the transfer now. 897 */ 898 if (cmd->c_error == 0 && cmd->c_data != NULL) 899 sdhc_transfer_data(hp, cmd); 900 901 /* Turn off the LED. */ 902 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 903 904 DPRINTF(1,("%s: cmd %u done (flags=%#x error=%d)\n", 905 DEVNAME(hp->sc), cmd->c_opcode, cmd->c_flags, cmd->c_error)); 906 SET(cmd->c_flags, SCF_ITSDONE); 907 } 908 909 int 910 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 911 { 912 struct sdhc_adma2_descriptor32 *desc32 = (void *)hp->adma2; 913 struct sdhc_adma2_descriptor64 *desc64 = (void *)hp->adma2; 914 struct sdhc_softc *sc = hp->sc; 915 u_int16_t blksize = 0; 916 u_int16_t blkcount = 0; 917 u_int16_t mode; 918 u_int16_t command; 919 int error; 920 int seg; 921 int s; 922 923 DPRINTF(1,("%s: start cmd %u arg=%#x data=%p dlen=%d flags=%#x\n", 924 DEVNAME(hp->sc), cmd->c_opcode, cmd->c_arg, cmd->c_data, 925 cmd->c_datalen, cmd->c_flags)); 926 927 /* 928 * The maximum block length for commands should be the minimum 929 * of the host buffer size and the card buffer size. (1.7.2) 930 */ 931 932 /* Fragment the data into proper blocks. */ 933 if (cmd->c_datalen > 0) { 934 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 935 blkcount = cmd->c_datalen / blksize; 936 if (cmd->c_datalen % blksize > 0) { 937 /* XXX: Split this command. (1.7.4) */ 938 printf("%s: data not a multiple of %d bytes\n", 939 DEVNAME(hp->sc), blksize); 940 return EINVAL; 941 } 942 } 943 944 /* Check limit imposed by 9-bit block count. (1.7.2) */ 945 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 946 printf("%s: too much data\n", DEVNAME(hp->sc)); 947 return EINVAL; 948 } 949 950 /* Prepare transfer mode register value. (2.2.5) */ 951 mode = 0; 952 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 953 mode |= SDHC_READ_MODE; 954 if (blkcount > 0) { 955 mode |= SDHC_BLOCK_COUNT_ENABLE; 956 if (blkcount > 1) { 957 mode |= SDHC_MULTI_BLOCK_MODE; 958 if (cmd->c_opcode != SD_IO_RW_EXTENDED) 959 mode |= SDHC_AUTO_CMD12_ENABLE; 960 } 961 } 962 if (cmd->c_dmamap && cmd->c_datalen > 0 && 963 ISSET(hp->flags, SHF_USE_DMA)) 964 mode |= SDHC_DMA_ENABLE; 965 966 /* 967 * Prepare command register value. (2.2.6) 968 */ 969 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << 970 SDHC_COMMAND_INDEX_SHIFT; 971 972 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 973 command |= SDHC_CRC_CHECK_ENABLE; 974 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 975 command |= SDHC_INDEX_CHECK_ENABLE; 976 if (cmd->c_data != NULL) 977 command |= SDHC_DATA_PRESENT_SELECT; 978 979 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 980 command |= SDHC_NO_RESPONSE; 981 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 982 command |= SDHC_RESP_LEN_136; 983 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 984 command |= SDHC_RESP_LEN_48_CHK_BUSY; 985 else 986 command |= SDHC_RESP_LEN_48; 987 988 /* Wait until command and data inhibit bits are clear. (1.5) */ 989 if ((error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0)) != 0) 990 return error; 991 992 s = splsdmmc(); 993 994 /* Alert the user not to remove the card. */ 995 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 996 997 /* Set DMA start address if SHF_USE_DMA is set. */ 998 if (cmd->c_dmamap && ISSET(hp->flags, SHF_USE_DMA)) { 999 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 1000 bus_addr_t paddr = 1001 cmd->c_dmamap->dm_segs[seg].ds_addr; 1002 uint16_t len = 1003 cmd->c_dmamap->dm_segs[seg].ds_len == 65536 ? 1004 0 : cmd->c_dmamap->dm_segs[seg].ds_len; 1005 uint16_t attr; 1006 1007 attr = SDHC_ADMA2_VALID | SDHC_ADMA2_ACT_TRANS; 1008 if (seg == cmd->c_dmamap->dm_nsegs - 1) 1009 attr |= SDHC_ADMA2_END; 1010 1011 if (ISSET(hp->flags, SHF_USE_DMA64)) { 1012 desc64[seg].attribute = htole16(attr); 1013 desc64[seg].length = htole16(len); 1014 desc64[seg].address_lo = 1015 htole32((uint64_t)paddr & 0xffffffff); 1016 desc64[seg].address_hi = 1017 htole32((uint64_t)paddr >> 32); 1018 } else { 1019 desc32[seg].attribute = htole16(attr); 1020 desc32[seg].length = htole16(len); 1021 desc32[seg].address = htole32(paddr); 1022 } 1023 } 1024 1025 if (ISSET(hp->flags, SHF_USE_DMA64)) 1026 desc64[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 1027 else 1028 desc32[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 1029 1030 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE, 1031 BUS_DMASYNC_PREWRITE); 1032 1033 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT); 1034 if (ISSET(hp->flags, SHF_USE_DMA64)) 1035 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA64); 1036 else 1037 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA32); 1038 1039 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR, 1040 hp->adma_map->dm_segs[0].ds_addr); 1041 } else 1042 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT); 1043 1044 DPRINTF(1,("%s: cmd=%#x mode=%#x blksize=%d blkcount=%d\n", 1045 DEVNAME(hp->sc), command, mode, blksize, blkcount)); 1046 1047 /* 1048 * Start a CPU data transfer. Writing to the high order byte 1049 * of the SDHC_COMMAND register triggers the SD command. (1.5) 1050 */ 1051 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 1052 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 1053 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 1054 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1055 HWRITE2(hp, SDHC_COMMAND, command); 1056 1057 splx(s); 1058 return 0; 1059 } 1060 1061 void 1062 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 1063 { 1064 struct sdhc_softc *sc = hp->sc; 1065 u_char *datap = cmd->c_data; 1066 int i, datalen; 1067 int mask; 1068 int error; 1069 1070 if (cmd->c_dmamap) { 1071 int status; 1072 1073 error = 0; 1074 for (;;) { 1075 status = sdhc_wait_intr(hp, 1076 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 1077 SDHC_DMA_TIMEOUT); 1078 if (status & SDHC_TRANSFER_COMPLETE) 1079 break; 1080 if (!status) { 1081 error = ETIMEDOUT; 1082 break; 1083 } 1084 } 1085 1086 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE, 1087 BUS_DMASYNC_POSTWRITE); 1088 goto done; 1089 } 1090 1091 mask = ISSET(cmd->c_flags, SCF_CMD_READ) ? 1092 SDHC_BUFFER_READ_ENABLE : SDHC_BUFFER_WRITE_ENABLE; 1093 error = 0; 1094 datalen = cmd->c_datalen; 1095 1096 DPRINTF(1,("%s: resp=%#x datalen=%d\n", DEVNAME(hp->sc), 1097 MMC_R1(cmd->c_resp), datalen)); 1098 1099 #ifdef SDHC_DEBUG 1100 /* XXX I forgot why I wanted to know when this happens :-( */ 1101 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 1102 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) 1103 printf("%s: CMD52/53 error response flags %#x\n", 1104 DEVNAME(hp->sc), MMC_R1(cmd->c_resp) & 0xff00); 1105 #endif 1106 1107 while (datalen > 0) { 1108 if (!sdhc_wait_intr(hp, SDHC_BUFFER_READ_READY| 1109 SDHC_BUFFER_WRITE_READY, SDHC_BUFFER_TIMEOUT)) { 1110 error = ETIMEDOUT; 1111 break; 1112 } 1113 1114 if ((error = sdhc_wait_state(hp, mask, mask)) != 0) 1115 break; 1116 1117 i = MIN(datalen, cmd->c_blklen); 1118 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1119 sdhc_read_data(hp, datap, i); 1120 else 1121 sdhc_write_data(hp, datap, i); 1122 1123 datap += i; 1124 datalen -= i; 1125 } 1126 1127 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1128 SDHC_TRANSFER_TIMEOUT)) 1129 error = ETIMEDOUT; 1130 1131 done: 1132 if (error != 0) 1133 cmd->c_error = error; 1134 SET(cmd->c_flags, SCF_ITSDONE); 1135 1136 DPRINTF(1,("%s: data transfer done (error=%d)\n", 1137 DEVNAME(hp->sc), cmd->c_error)); 1138 } 1139 1140 void 1141 sdhc_read_data(struct sdhc_host *hp, u_char *datap, int datalen) 1142 { 1143 while (datalen > 3) { 1144 *(u_int32_t *)datap = HREAD4(hp, SDHC_DATA); 1145 datap += 4; 1146 datalen -= 4; 1147 } 1148 if (datalen > 0) { 1149 u_int32_t rv = HREAD4(hp, SDHC_DATA); 1150 do { 1151 *datap++ = rv & 0xff; 1152 rv = rv >> 8; 1153 } while (--datalen > 0); 1154 } 1155 } 1156 1157 void 1158 sdhc_write_data(struct sdhc_host *hp, u_char *datap, int datalen) 1159 { 1160 while (datalen > 3) { 1161 DPRINTF(3,("%08x\n", *(u_int32_t *)datap)); 1162 HWRITE4(hp, SDHC_DATA, *((u_int32_t *)datap)); 1163 datap += 4; 1164 datalen -= 4; 1165 } 1166 if (datalen > 0) { 1167 u_int32_t rv = *datap++; 1168 if (datalen > 1) 1169 rv |= *datap++ << 8; 1170 if (datalen > 2) 1171 rv |= *datap++ << 16; 1172 DPRINTF(3,("rv %08x\n", rv)); 1173 HWRITE4(hp, SDHC_DATA, rv); 1174 } 1175 } 1176 1177 /* Prepare for another command. */ 1178 int 1179 sdhc_soft_reset(struct sdhc_host *hp, int mask) 1180 { 1181 int timo; 1182 1183 DPRINTF(1,("%s: software reset reg=%#x\n", DEVNAME(hp->sc), mask)); 1184 1185 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1186 for (timo = 10; timo > 0; timo--) { 1187 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1188 break; 1189 sdmmc_delay(10000); 1190 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1191 } 1192 if (timo == 0) { 1193 DPRINTF(1,("%s: timeout reg=%#x\n", DEVNAME(hp->sc), 1194 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1195 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1196 return (ETIMEDOUT); 1197 } 1198 1199 return (0); 1200 } 1201 1202 int 1203 sdhc_wait_intr_cold(struct sdhc_host *hp, int mask, int secs) 1204 { 1205 int status, usecs; 1206 1207 mask |= SDHC_ERROR_INTERRUPT; 1208 usecs = secs * 1000000; 1209 status = hp->intr_status; 1210 while ((status & mask) == 0) { 1211 1212 status = HREAD2(hp, SDHC_NINTR_STATUS); 1213 if (ISSET(status, SDHC_NINTR_STATUS_MASK)) { 1214 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1215 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1216 uint16_t error; 1217 error = HREAD2(hp, SDHC_EINTR_STATUS); 1218 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1219 hp->intr_status |= status; 1220 1221 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1222 SDHC_DATA_TIMEOUT_ERROR)) 1223 break; 1224 } 1225 1226 if (ISSET(status, SDHC_BUFFER_READ_READY | 1227 SDHC_BUFFER_WRITE_READY | SDHC_COMMAND_COMPLETE | 1228 SDHC_TRANSFER_COMPLETE)) { 1229 hp->intr_status |= status; 1230 break; 1231 } 1232 1233 if (ISSET(status, SDHC_CARD_INTERRUPT)) { 1234 HSET2(hp, SDHC_NINTR_STATUS_EN, 1235 SDHC_CARD_INTERRUPT); 1236 } 1237 1238 continue; 1239 } 1240 1241 delay(1); 1242 if (usecs-- == 0) { 1243 status |= SDHC_ERROR_INTERRUPT; 1244 break; 1245 } 1246 } 1247 1248 hp->intr_status &= ~(status & mask); 1249 return (status & mask); 1250 } 1251 1252 int 1253 sdhc_wait_intr(struct sdhc_host *hp, int mask, int secs) 1254 { 1255 int status; 1256 int s; 1257 1258 if (cold) 1259 return (sdhc_wait_intr_cold(hp, mask, secs)); 1260 1261 mask |= SDHC_ERROR_INTERRUPT; 1262 1263 s = splsdmmc(); 1264 status = hp->intr_status & mask; 1265 while (status == 0) { 1266 if (tsleep_nsec(&hp->intr_status, PWAIT, "hcintr", 1267 SEC_TO_NSEC(secs)) == EWOULDBLOCK) { 1268 status |= SDHC_ERROR_INTERRUPT; 1269 break; 1270 } 1271 status = hp->intr_status & mask; 1272 } 1273 hp->intr_status &= ~status; 1274 1275 DPRINTF(2,("%s: intr status %#x error %#x\n", DEVNAME(hp->sc), status, 1276 hp->intr_error_status)); 1277 1278 /* Command timeout has higher priority than command complete. */ 1279 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1280 hp->intr_error_status = 0; 1281 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1282 status = 0; 1283 } 1284 1285 splx(s); 1286 return status; 1287 } 1288 1289 /* 1290 * Established by attachment driver at interrupt priority IPL_SDMMC. 1291 */ 1292 int 1293 sdhc_intr(void *arg) 1294 { 1295 struct sdhc_softc *sc = arg; 1296 int host; 1297 int done = 0; 1298 1299 /* We got an interrupt, but we don't know from which slot. */ 1300 for (host = 0; host < sc->sc_nhosts; host++) { 1301 struct sdhc_host *hp = sc->sc_host[host]; 1302 u_int16_t status; 1303 1304 if (hp == NULL) 1305 continue; 1306 1307 /* Find out which interrupts are pending. */ 1308 status = HREAD2(hp, SDHC_NINTR_STATUS); 1309 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1310 continue; /* no interrupt for us */ 1311 1312 /* Acknowledge the interrupts we are about to handle. */ 1313 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1314 DPRINTF(2,("%s: interrupt status=%b\n", DEVNAME(hp->sc), 1315 status, SDHC_NINTR_STATUS_BITS)); 1316 1317 /* Claim this interrupt. */ 1318 done = 1; 1319 1320 /* 1321 * Service error interrupts. 1322 */ 1323 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1324 u_int16_t error; 1325 1326 /* Acknowledge error interrupts. */ 1327 error = HREAD2(hp, SDHC_EINTR_STATUS); 1328 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1329 DPRINTF(2,("%s: error interrupt, status=%b\n", 1330 DEVNAME(hp->sc), error, SDHC_EINTR_STATUS_BITS)); 1331 1332 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1333 SDHC_DATA_TIMEOUT_ERROR)) { 1334 hp->intr_error_status |= error; 1335 hp->intr_status |= status; 1336 wakeup(&hp->intr_status); 1337 } 1338 } 1339 1340 /* 1341 * Wake up the sdmmc event thread to scan for cards. 1342 */ 1343 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) 1344 sdmmc_needs_discover(hp->sdmmc); 1345 1346 /* 1347 * Wake up the blocking process to service command 1348 * related interrupt(s). 1349 */ 1350 if (ISSET(status, SDHC_BUFFER_READ_READY| 1351 SDHC_BUFFER_WRITE_READY|SDHC_COMMAND_COMPLETE| 1352 SDHC_TRANSFER_COMPLETE)) { 1353 hp->intr_status |= status; 1354 wakeup(&hp->intr_status); 1355 } 1356 1357 /* 1358 * Service SD card interrupts. 1359 */ 1360 if (ISSET(status, SDHC_CARD_INTERRUPT)) { 1361 DPRINTF(0,("%s: card interrupt\n", DEVNAME(hp->sc))); 1362 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1363 sdmmc_card_intr(hp->sdmmc); 1364 } 1365 } 1366 return done; 1367 } 1368 1369 void 1370 sdhc_needs_discover(struct sdhc_softc *sc) 1371 { 1372 int host; 1373 1374 for (host = 0; host < sc->sc_nhosts; host++) 1375 sdmmc_needs_discover(sc->sc_host[host]->sdmmc); 1376 } 1377 1378 #ifdef SDHC_DEBUG 1379 void 1380 sdhc_dump_regs(struct sdhc_host *hp) 1381 { 1382 printf("0x%02x PRESENT_STATE: %b\n", SDHC_PRESENT_STATE, 1383 HREAD4(hp, SDHC_PRESENT_STATE), SDHC_PRESENT_STATE_BITS); 1384 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 1385 HREAD1(hp, SDHC_POWER_CTL)); 1386 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 1387 HREAD2(hp, SDHC_NINTR_STATUS)); 1388 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 1389 HREAD2(hp, SDHC_EINTR_STATUS)); 1390 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 1391 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 1392 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 1393 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 1394 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 1395 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 1396 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 1397 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 1398 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 1399 HREAD4(hp, SDHC_CAPABILITIES)); 1400 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 1401 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 1402 } 1403 #endif 1404 1405 int 1406 sdhc_hibernate_init(sdmmc_chipset_handle_t sch, void *fake_softc) 1407 { 1408 struct sdhc_host *hp, *fhp; 1409 fhp = fake_softc; 1410 hp = sch; 1411 *fhp = *hp; 1412 1413 return (0); 1414 } 1415