1 /* $OpenBSD: sdhc.c,v 1.78 2024/10/19 21:10:03 hastings Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * SD Host Controller driver based on the SD Host Controller Standard 21 * Simplified Specification Version 1.00 (www.sdcard.org). 22 */ 23 24 #include <sys/param.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/malloc.h> 28 #include <sys/proc.h> 29 #include <sys/systm.h> 30 #include <sys/time.h> 31 32 #include <dev/sdmmc/sdhcreg.h> 33 #include <dev/sdmmc/sdhcvar.h> 34 #include <dev/sdmmc/sdmmcchip.h> 35 #include <dev/sdmmc/sdmmcreg.h> 36 #include <dev/sdmmc/sdmmcvar.h> 37 #include <dev/sdmmc/sdmmc_ioreg.h> 38 39 /* Timeouts in seconds */ 40 #define SDHC_COMMAND_TIMEOUT 1 41 #define SDHC_BUFFER_TIMEOUT 1 42 #define SDHC_TRANSFER_TIMEOUT 1 43 #define SDHC_DMA_TIMEOUT 3 44 45 struct sdhc_host { 46 struct sdhc_softc *sc; /* host controller device */ 47 struct device *sdmmc; /* generic SD/MMC device */ 48 bus_space_tag_t iot; /* host register set tag */ 49 bus_space_handle_t ioh; /* host register set handle */ 50 u_int16_t version; /* specification version */ 51 u_int clkbase; /* base clock frequency in KHz */ 52 int maxblklen; /* maximum block length */ 53 int flags; /* flags for this host */ 54 u_int32_t ocr; /* OCR value from capabilities */ 55 u_int8_t regs[14]; /* host controller state */ 56 u_int16_t intr_status; /* soft interrupt status */ 57 u_int16_t intr_error_status; /* soft error status */ 58 59 bus_dmamap_t adma_map; 60 bus_dma_segment_t adma_segs[1]; 61 caddr_t adma2; 62 63 uint16_t block_size; 64 uint16_t block_count; 65 uint16_t transfer_mode; 66 }; 67 68 /* flag values */ 69 #define SHF_USE_DMA 0x0001 70 #define SHF_USE_DMA64 0x0002 71 #define SHF_USE_32BIT_ACCESS 0x0004 72 73 #define HREAD1(hp, reg) \ 74 (sdhc_read_1((hp), (reg))) 75 #define HREAD2(hp, reg) \ 76 (sdhc_read_2((hp), (reg))) 77 #define HREAD4(hp, reg) \ 78 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 79 #define HWRITE1(hp, reg, val) \ 80 sdhc_write_1((hp), (reg), (val)) 81 #define HWRITE2(hp, reg, val) \ 82 sdhc_write_2((hp), (reg), (val)) 83 #define HWRITE4(hp, reg, val) \ 84 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 85 #define HCLR1(hp, reg, bits) \ 86 HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)) 87 #define HCLR2(hp, reg, bits) \ 88 HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)) 89 #define HSET1(hp, reg, bits) \ 90 HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)) 91 #define HSET2(hp, reg, bits) \ 92 HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)) 93 94 int sdhc_host_reset(sdmmc_chipset_handle_t); 95 u_int32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 96 int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 97 int sdhc_card_detect(sdmmc_chipset_handle_t); 98 int sdhc_bus_power(sdmmc_chipset_handle_t, u_int32_t); 99 int sdhc_bus_clock(sdmmc_chipset_handle_t, int, int); 100 int sdhc_bus_width(sdmmc_chipset_handle_t, int); 101 void sdhc_card_intr_mask(sdmmc_chipset_handle_t, int); 102 void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 103 int sdhc_signal_voltage(sdmmc_chipset_handle_t, int); 104 void sdhc_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *); 105 int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 106 int sdhc_wait_state(struct sdhc_host *, u_int32_t, u_int32_t); 107 int sdhc_soft_reset(struct sdhc_host *, int); 108 int sdhc_wait_intr_cold(struct sdhc_host *, int, int); 109 int sdhc_wait_intr(struct sdhc_host *, int, int); 110 void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 111 void sdhc_read_data(struct sdhc_host *, u_char *, int); 112 void sdhc_write_data(struct sdhc_host *, u_char *, int); 113 int sdhc_hibernate_init(sdmmc_chipset_handle_t, void *); 114 115 #ifdef SDHC_DEBUG 116 int sdhcdebug = 0; 117 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 118 void sdhc_dump_regs(struct sdhc_host *); 119 #else 120 #define DPRINTF(n,s) do {} while(0) 121 #endif 122 123 struct sdmmc_chip_functions sdhc_functions = { 124 .host_reset = sdhc_host_reset, 125 .host_ocr = sdhc_host_ocr, 126 .host_maxblklen = sdhc_host_maxblklen, 127 .card_detect = sdhc_card_detect, 128 .bus_power = sdhc_bus_power, 129 .bus_clock = sdhc_bus_clock, 130 .bus_width = sdhc_bus_width, 131 .exec_command = sdhc_exec_command, 132 .card_intr_mask = sdhc_card_intr_mask, 133 .card_intr_ack = sdhc_card_intr_ack, 134 .signal_voltage = sdhc_signal_voltage, 135 .hibernate_init = sdhc_hibernate_init, 136 }; 137 138 struct cfdriver sdhc_cd = { 139 NULL, "sdhc", DV_DULL 140 }; 141 142 /* 143 * Some controllers live on a bus that only allows 32-bit 144 * transactions. In that case we use a RMW cycle for 8-bit and 16-bit 145 * register writes. However that doesn't work for the Transfer Mode 146 * register as this register lives in the same 32-bit word as the 147 * Command register and writing the Command register triggers SD 148 * command generation. We avoid this issue by using a shadow variable 149 * for the Transfer Mode register that we write out when we write the 150 * Command register. 151 * 152 * The Arasan controller integrated on the Broadcom SoCs 153 * used in the Raspberry Pi has an interesting bug where writing the 154 * same 32-bit register twice doesn't work. This means that we lose 155 * writes to the Block Sine and/or Block Count register. We work 156 * around that issue by using shadow variables as well. 157 */ 158 159 uint8_t 160 sdhc_read_1(struct sdhc_host *hp, bus_size_t offset) 161 { 162 uint32_t reg; 163 164 if (hp->flags & SHF_USE_32BIT_ACCESS) { 165 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~3); 166 return (reg >> ((offset & 3) * 8)) & 0xff; 167 } 168 169 return bus_space_read_1(hp->iot, hp->ioh, offset); 170 } 171 172 uint16_t 173 sdhc_read_2(struct sdhc_host *hp, bus_size_t offset) 174 { 175 uint32_t reg; 176 177 if (hp->flags & SHF_USE_32BIT_ACCESS) { 178 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~2); 179 return (reg >> ((offset & 2) * 8)) & 0xffff; 180 } 181 182 return bus_space_read_2(hp->iot, hp->ioh, offset); 183 } 184 185 void 186 sdhc_write_1(struct sdhc_host *hp, bus_size_t offset, uint8_t value) 187 { 188 uint32_t reg; 189 190 if (hp->flags & SHF_USE_32BIT_ACCESS) { 191 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~3); 192 reg &= ~(0xff << ((offset & 3) * 8)); 193 reg |= (value << ((offset & 3) * 8)); 194 bus_space_write_4(hp->iot, hp->ioh, offset & ~3, reg); 195 return; 196 } 197 198 bus_space_write_1(hp->iot, hp->ioh, offset, value); 199 } 200 201 void 202 sdhc_write_2(struct sdhc_host *hp, bus_size_t offset, uint16_t value) 203 { 204 uint32_t reg; 205 206 if (hp->flags & SHF_USE_32BIT_ACCESS) { 207 switch (offset) { 208 case SDHC_BLOCK_SIZE: 209 hp->block_size = value; 210 return; 211 case SDHC_BLOCK_COUNT: 212 hp->block_count = value; 213 return; 214 case SDHC_TRANSFER_MODE: 215 hp->transfer_mode = value; 216 return; 217 case SDHC_COMMAND: 218 bus_space_write_4(hp->iot, hp->ioh, SDHC_BLOCK_SIZE, 219 (hp->block_count << 16) | hp->block_size); 220 bus_space_write_4(hp->iot, hp->ioh, SDHC_TRANSFER_MODE, 221 (value << 16) | hp->transfer_mode); 222 return; 223 } 224 225 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~2); 226 reg &= ~(0xffff << ((offset & 2) * 8)); 227 reg |= (value << ((offset & 2) * 8)); 228 bus_space_write_4(hp->iot, hp->ioh, offset & ~2, reg); 229 return; 230 } 231 232 bus_space_write_2(hp->iot, hp->ioh, offset, value); 233 } 234 235 /* 236 * Called by attachment driver. For each SD card slot there is one SD 237 * host controller standard register set. (1.3) 238 */ 239 int 240 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 241 bus_space_handle_t ioh, bus_size_t iosize, int usedma, uint64_t capmask, 242 uint64_t capset) 243 { 244 struct sdmmcbus_attach_args saa; 245 struct sdhc_host *hp; 246 uint32_t caps; 247 int major, minor; 248 int error = 1; 249 int max_clock; 250 251 /* Allocate one more host structure. */ 252 sc->sc_nhosts++; 253 hp = malloc(sizeof(*hp), M_DEVBUF, M_WAITOK | M_ZERO); 254 sc->sc_host[sc->sc_nhosts - 1] = hp; 255 256 if (ISSET(sc->sc_flags, SDHC_F_32BIT_ACCESS)) 257 SET(hp->flags, SHF_USE_32BIT_ACCESS); 258 259 /* Fill in the new host structure. */ 260 hp->sc = sc; 261 hp->iot = iot; 262 hp->ioh = ioh; 263 264 /* Store specification version. */ 265 hp->version = HREAD2(hp, SDHC_HOST_CTL_VERSION); 266 267 /* 268 * Reset the host controller and enable interrupts. 269 */ 270 (void)sdhc_host_reset(hp); 271 272 /* Determine host capabilities. */ 273 caps = HREAD4(hp, SDHC_CAPABILITIES); 274 caps &= ~capmask; 275 caps |= capset; 276 277 /* Use DMA if the host system and the controller support it. */ 278 if (usedma && ISSET(caps, SDHC_ADMA2_SUPP)) { 279 SET(hp->flags, SHF_USE_DMA); 280 if (ISSET(caps, SDHC_64BIT_DMA_SUPP)) 281 SET(hp->flags, SHF_USE_DMA64); 282 } 283 284 /* 285 * Determine the base clock frequency. (2.2.24) 286 */ 287 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 288 /* SDHC 3.0 supports 10-255 MHz. */ 289 max_clock = 255000; 290 if (SDHC_BASE_FREQ_KHZ_V3(caps) != 0) 291 hp->clkbase = SDHC_BASE_FREQ_KHZ_V3(caps); 292 } else { 293 /* SDHC 1.0/2.0 supports only 10-63 MHz. */ 294 max_clock = 63000; 295 if (SDHC_BASE_FREQ_KHZ(caps) != 0) 296 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 297 } 298 if (hp->clkbase == 0) { 299 /* Make sure we can clock down to 400 kHz. */ 300 max_clock = 400 * SDHC_SDCLK_DIV_MAX_V3; 301 hp->clkbase = sc->sc_clkbase; 302 } 303 if (hp->clkbase == 0) { 304 /* The attachment driver must tell us. */ 305 printf("%s: base clock frequency unknown\n", 306 sc->sc_dev.dv_xname); 307 goto err; 308 } else if (hp->clkbase < 10000 || hp->clkbase > max_clock) { 309 printf("%s: base clock frequency out of range: %u MHz\n", 310 sc->sc_dev.dv_xname, hp->clkbase / 1000); 311 goto err; 312 } 313 314 switch (SDHC_SPEC_VERSION(hp->version)) { 315 case SDHC_SPEC_VERS_4_10: 316 major = 4, minor = 10; 317 break; 318 case SDHC_SPEC_VERS_4_20: 319 major = 4, minor = 20; 320 break; 321 default: 322 major = SDHC_SPEC_VERSION(hp->version) + 1, minor = 0; 323 break; 324 } 325 326 printf("%s: SDHC %d.%02d, %d MHz base clock\n", DEVNAME(sc), 327 major, minor, hp->clkbase / 1000); 328 329 /* 330 * XXX Set the data timeout counter value according to 331 * capabilities. (2.2.15) 332 */ 333 334 /* 335 * Determine SD bus voltage levels supported by the controller. 336 */ 337 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)) 338 SET(hp->ocr, MMC_OCR_1_65V_1_95V); 339 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) 340 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 341 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) 342 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 343 344 /* 345 * Determine the maximum block length supported by the host 346 * controller. (2.2.24) 347 */ 348 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 349 case SDHC_MAX_BLK_LEN_512: 350 hp->maxblklen = 512; 351 break; 352 case SDHC_MAX_BLK_LEN_1024: 353 hp->maxblklen = 1024; 354 break; 355 case SDHC_MAX_BLK_LEN_2048: 356 hp->maxblklen = 2048; 357 break; 358 default: 359 hp->maxblklen = 1; 360 break; 361 } 362 363 if (ISSET(hp->flags, SHF_USE_DMA)) { 364 int rseg; 365 366 /* Allocate ADMA2 descriptor memory */ 367 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 368 PAGE_SIZE, hp->adma_segs, 1, &rseg, 369 BUS_DMA_WAITOK | BUS_DMA_ZERO); 370 if (error) 371 goto adma_done; 372 error = bus_dmamem_map(sc->sc_dmat, hp->adma_segs, rseg, 373 PAGE_SIZE, &hp->adma2, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 374 if (error) { 375 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg); 376 goto adma_done; 377 } 378 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 379 0, BUS_DMA_WAITOK, &hp->adma_map); 380 if (error) { 381 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE); 382 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg); 383 goto adma_done; 384 } 385 error = bus_dmamap_load(sc->sc_dmat, hp->adma_map, 386 hp->adma2, PAGE_SIZE, NULL, 387 BUS_DMA_WAITOK | BUS_DMA_WRITE); 388 if (error) { 389 bus_dmamap_destroy(sc->sc_dmat, hp->adma_map); 390 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE); 391 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg); 392 goto adma_done; 393 } 394 395 adma_done: 396 if (error) { 397 printf("%s: can't allocate DMA descriptor table\n", 398 DEVNAME(hp->sc)); 399 CLR(hp->flags, SHF_USE_DMA); 400 } 401 } 402 403 /* 404 * Attach the generic SD/MMC bus driver. (The bus driver must 405 * not invoke any chipset functions before it is attached.) 406 */ 407 bzero(&saa, sizeof(saa)); 408 saa.saa_busname = "sdmmc"; 409 saa.sct = &sdhc_functions; 410 saa.sch = hp; 411 saa.caps = SMC_CAPS_4BIT_MODE; 412 saa.dmat = sc->sc_dmat; 413 saa.dma_boundary = sc->sc_dma_boundary; 414 if (ISSET(hp->flags, SHF_USE_DMA)) 415 saa.caps |= SMC_CAPS_DMA; 416 417 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 418 saa.caps |= SMC_CAPS_SD_HIGHSPEED; 419 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 420 saa.caps |= SMC_CAPS_MMC_HIGHSPEED; 421 422 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 423 uint32_t caps2 = HREAD4(hp, SDHC_CAPABILITIES2); 424 caps2 &= ~(capmask >> 32); 425 caps2 |= capset >> 32; 426 427 if (ISSET(caps, SDHC_8BIT_MODE_SUPP)) 428 saa.caps |= SMC_CAPS_8BIT_MODE; 429 430 if (ISSET(caps2, SDHC_DDR50_SUPP)) 431 saa.caps |= SMC_CAPS_MMC_DDR52; 432 } 433 434 if (ISSET(sc->sc_flags, SDHC_F_NONREMOVABLE)) 435 saa.caps |= SMC_CAPS_NONREMOVABLE; 436 437 hp->sdmmc = config_found(&sc->sc_dev, &saa, NULL); 438 if (hp->sdmmc == NULL) { 439 error = 0; 440 goto err; 441 } 442 443 return 0; 444 445 err: 446 free(hp, M_DEVBUF, sizeof *hp); 447 sc->sc_host[sc->sc_nhosts - 1] = NULL; 448 sc->sc_nhosts--; 449 return (error); 450 } 451 452 int 453 sdhc_activate(struct device *self, int act) 454 { 455 struct sdhc_softc *sc = (struct sdhc_softc *)self; 456 struct sdhc_host *hp; 457 int n, i, rv = 0; 458 459 switch (act) { 460 case DVACT_SUSPEND: 461 rv = config_activate_children(self, act); 462 463 /* Save the host controller state. */ 464 for (n = 0; n < sc->sc_nhosts; n++) { 465 hp = sc->sc_host[n]; 466 for (i = 0; i < sizeof hp->regs; i++) 467 hp->regs[i] = HREAD1(hp, i); 468 } 469 break; 470 case DVACT_RESUME: 471 /* Restore the host controller state. */ 472 for (n = 0; n < sc->sc_nhosts; n++) { 473 hp = sc->sc_host[n]; 474 (void)sdhc_host_reset(hp); 475 for (i = 0; i < sizeof hp->regs; i++) 476 HWRITE1(hp, i, hp->regs[i]); 477 } 478 rv = config_activate_children(self, act); 479 break; 480 case DVACT_POWERDOWN: 481 rv = config_activate_children(self, act); 482 sdhc_shutdown(self); 483 break; 484 default: 485 rv = config_activate_children(self, act); 486 break; 487 } 488 return (rv); 489 } 490 491 /* 492 * Shutdown hook established by or called from attachment driver. 493 */ 494 void 495 sdhc_shutdown(void *arg) 496 { 497 struct sdhc_softc *sc = arg; 498 struct sdhc_host *hp; 499 int i; 500 501 /* XXX chip locks up if we don't disable it before reboot. */ 502 for (i = 0; i < sc->sc_nhosts; i++) { 503 hp = sc->sc_host[i]; 504 (void)sdhc_host_reset(hp); 505 } 506 } 507 508 /* 509 * Reset the host controller. Called during initialization, when 510 * cards are removed, upon resume, and during error recovery. 511 */ 512 int 513 sdhc_host_reset(sdmmc_chipset_handle_t sch) 514 { 515 struct sdhc_host *hp = sch; 516 u_int16_t imask; 517 int error; 518 int s; 519 520 s = splsdmmc(); 521 522 /* Disable all interrupts. */ 523 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 524 525 /* 526 * Reset the entire host controller and wait up to 100ms for 527 * the controller to clear the reset bit. 528 */ 529 if ((error = sdhc_soft_reset(hp, SDHC_RESET_ALL)) != 0) { 530 splx(s); 531 return (error); 532 } 533 534 /* Set data timeout counter value to max for now. */ 535 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 536 537 /* Enable interrupts. */ 538 imask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 539 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 540 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 541 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 542 543 HWRITE2(hp, SDHC_NINTR_STATUS_EN, imask); 544 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 545 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, imask); 546 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 547 548 splx(s); 549 return 0; 550 } 551 552 u_int32_t 553 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 554 { 555 struct sdhc_host *hp = sch; 556 return hp->ocr; 557 } 558 559 int 560 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 561 { 562 struct sdhc_host *hp = sch; 563 return hp->maxblklen; 564 } 565 566 /* 567 * Return non-zero if the card is currently inserted. 568 */ 569 int 570 sdhc_card_detect(sdmmc_chipset_handle_t sch) 571 { 572 struct sdhc_host *hp = sch; 573 574 if (hp->sc->sc_card_detect) 575 return hp->sc->sc_card_detect(hp->sc); 576 577 return ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED) ? 578 1 : 0; 579 } 580 581 /* 582 * Set or change SD bus voltage and enable or disable SD bus power. 583 * Return zero on success. 584 */ 585 int 586 sdhc_bus_power(sdmmc_chipset_handle_t sch, u_int32_t ocr) 587 { 588 struct sdhc_host *hp = sch; 589 u_int8_t vdd; 590 int s; 591 592 s = splsdmmc(); 593 594 /* If power is disabled, reset the host and return now. */ 595 if (ocr == 0) { 596 HWRITE1(hp, SDHC_POWER_CTL, 0); 597 splx(s); 598 (void)sdhc_host_reset(hp); 599 return 0; 600 } 601 602 /* 603 * Select the maximum voltage according to capabilities. 604 */ 605 ocr &= hp->ocr; 606 if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) 607 vdd = SDHC_VOLTAGE_3_3V; 608 else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) 609 vdd = SDHC_VOLTAGE_3_0V; 610 else if (ISSET(ocr, MMC_OCR_1_65V_1_95V)) 611 vdd = SDHC_VOLTAGE_1_8V; 612 else { 613 /* Unsupported voltage level requested. */ 614 splx(s); 615 return EINVAL; 616 } 617 618 /* 619 * Return if no change to powered bus voltage. 620 */ 621 if (HREAD1(hp, SDHC_POWER_CTL) == 622 ((vdd << SDHC_VOLTAGE_SHIFT) | SDHC_BUS_POWER)) { 623 splx(s); 624 return 0; 625 } 626 627 /* 628 * Disable bus power before voltage change. 629 */ 630 if (!(hp->sc->sc_flags & SDHC_F_NOPWR0)) 631 HWRITE1(hp, SDHC_POWER_CTL, 0); 632 633 /* 634 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 635 * voltage ramp until power rises. 636 */ 637 HWRITE1(hp, SDHC_POWER_CTL, (vdd << SDHC_VOLTAGE_SHIFT) | 638 SDHC_BUS_POWER); 639 sdmmc_delay(10000); 640 641 /* 642 * The host system may not power the bus due to battery low, 643 * etc. In that case, the host controller should clear the 644 * bus power bit. 645 */ 646 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 647 splx(s); 648 return ENXIO; 649 } 650 651 splx(s); 652 return 0; 653 } 654 655 /* 656 * Return the smallest possible base clock frequency divisor value 657 * for the CLOCK_CTL register to produce `freq' (KHz). 658 */ 659 static int 660 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq) 661 { 662 int div; 663 664 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 665 if (hp->clkbase <= freq) 666 return 0; 667 668 for (div = 2; div <= SDHC_SDCLK_DIV_MAX_V3; div += 2) 669 if ((hp->clkbase / div) <= freq) 670 return (div / 2); 671 } else { 672 for (div = 1; div <= SDHC_SDCLK_DIV_MAX; div *= 2) 673 if ((hp->clkbase / div) <= freq) 674 return (div / 2); 675 } 676 677 /* No divisor found. */ 678 return -1; 679 } 680 681 /* 682 * Set or change SDCLK frequency or disable the SD clock. 683 * Return zero on success. 684 */ 685 int 686 sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing) 687 { 688 struct sdhc_host *hp = sch; 689 struct sdhc_softc *sc = hp->sc; 690 int s; 691 int div; 692 int sdclk; 693 int timo; 694 int error = 0; 695 696 s = splsdmmc(); 697 698 if (hp->sc->sc_bus_clock_pre) 699 hp->sc->sc_bus_clock_pre(hp->sc, freq, timing); 700 701 #ifdef DIAGNOSTIC 702 /* Must not stop the clock if commands are in progress. */ 703 if (ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK) && 704 sdhc_card_detect(hp)) 705 printf("sdhc_sdclk_frequency_select: command in progress\n"); 706 #endif 707 708 /* 709 * Stop SD clock before changing the frequency. 710 */ 711 HWRITE2(hp, SDHC_CLOCK_CTL, 0); 712 if (freq == SDMMC_SDCLK_OFF) 713 goto ret; 714 715 if (!ISSET(sc->sc_flags, SDHC_F_NO_HS_BIT)) { 716 if (timing == SDMMC_TIMING_LEGACY) 717 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 718 else 719 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 720 } 721 722 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 723 switch (timing) { 724 case SDMMC_TIMING_MMC_DDR52: 725 HCLR2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_MASK); 726 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_DDR50); 727 break; 728 } 729 } 730 731 /* 732 * Set the minimum base clock frequency divisor. 733 */ 734 if ((div = sdhc_clock_divisor(hp, freq)) < 0) { 735 /* Invalid base clock frequency or `freq' value. */ 736 error = EINVAL; 737 goto ret; 738 } 739 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) 740 sdclk = SDHC_SDCLK_DIV_V3(div); 741 else 742 sdclk = SDHC_SDCLK_DIV(div); 743 HWRITE2(hp, SDHC_CLOCK_CTL, sdclk); 744 745 /* 746 * Start internal clock. Wait 10ms for stabilization. 747 */ 748 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 749 for (timo = 1000; timo > 0; timo--) { 750 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), SDHC_INTCLK_STABLE)) 751 break; 752 sdmmc_delay(10); 753 } 754 if (timo == 0) { 755 error = ETIMEDOUT; 756 goto ret; 757 } 758 759 /* 760 * Enable SD clock. 761 */ 762 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 763 764 if (hp->sc->sc_bus_clock_post) 765 hp->sc->sc_bus_clock_post(hp->sc, freq, timing); 766 767 ret: 768 splx(s); 769 return error; 770 } 771 772 int 773 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 774 { 775 struct sdhc_host *hp = (struct sdhc_host *)sch; 776 int reg; 777 int s; 778 779 if (width != 1 && width != 4 && width != 8) 780 return EINVAL; 781 782 s = splsdmmc(); 783 784 reg = HREAD1(hp, SDHC_HOST_CTL); 785 reg &= ~SDHC_4BIT_MODE; 786 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 787 reg &= ~SDHC_8BIT_MODE; 788 } 789 if (width == 4) { 790 reg |= SDHC_4BIT_MODE; 791 } else if (width == 8) { 792 KASSERT(SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3); 793 reg |= SDHC_8BIT_MODE; 794 } 795 HWRITE1(hp, SDHC_HOST_CTL, reg); 796 797 splx(s); 798 799 return 0; 800 } 801 802 void 803 sdhc_card_intr_mask(sdmmc_chipset_handle_t sch, int enable) 804 { 805 struct sdhc_host *hp = sch; 806 807 if (enable) { 808 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 809 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 810 } else { 811 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 812 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 813 } 814 } 815 816 void 817 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 818 { 819 struct sdhc_host *hp = sch; 820 821 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 822 } 823 824 int 825 sdhc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 826 { 827 struct sdhc_host *hp = sch; 828 829 if (hp->sc->sc_signal_voltage) 830 return hp->sc->sc_signal_voltage(hp->sc, signal_voltage); 831 832 if (SDHC_SPEC_VERSION(hp->version) < SDHC_SPEC_V3) 833 return EINVAL; 834 835 switch (signal_voltage) { 836 case SDMMC_SIGNAL_VOLTAGE_180: 837 HSET2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN); 838 break; 839 case SDMMC_SIGNAL_VOLTAGE_330: 840 HCLR2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN); 841 break; 842 default: 843 return EINVAL; 844 } 845 846 /* Regulator output shall be stable within 5 ms. */ 847 sdmmc_delay(5000); 848 849 /* Host controller clears this bit if 1.8V signalling fails. */ 850 if (signal_voltage == SDMMC_SIGNAL_VOLTAGE_180 && 851 !ISSET(HREAD2(hp, SDHC_HOST_CTL2), SDHC_1_8V_SIGNAL_EN)) 852 return EIO; 853 854 return 0; 855 } 856 857 int 858 sdhc_wait_state(struct sdhc_host *hp, u_int32_t mask, u_int32_t value) 859 { 860 u_int32_t state; 861 int timeout; 862 863 for (timeout = 10; timeout > 0; timeout--) { 864 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) 865 == value) 866 return 0; 867 sdmmc_delay(10000); 868 } 869 DPRINTF(0,("%s: timeout waiting for %x (state=%b)\n", DEVNAME(hp->sc), 870 value, state, SDHC_PRESENT_STATE_BITS)); 871 return ETIMEDOUT; 872 } 873 874 void 875 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 876 { 877 struct sdhc_host *hp = sch; 878 int error; 879 880 /* 881 * Start the MMC command, or mark `cmd' as failed and return. 882 */ 883 error = sdhc_start_command(hp, cmd); 884 if (error != 0) { 885 cmd->c_error = error; 886 SET(cmd->c_flags, SCF_ITSDONE); 887 return; 888 } 889 890 /* 891 * Wait until the command phase is done, or until the command 892 * is marked done for any other reason. 893 */ 894 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, 895 SDHC_COMMAND_TIMEOUT)) { 896 cmd->c_error = ETIMEDOUT; 897 SET(cmd->c_flags, SCF_ITSDONE); 898 return; 899 } 900 901 /* 902 * The host controller removes bits [0:7] from the response 903 * data (CRC) and we pass the data up unchanged to the bus 904 * driver (without padding). 905 */ 906 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 907 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 908 u_char *p = (u_char *)cmd->c_resp; 909 int i; 910 911 for (i = 0; i < 15; i++) 912 *p++ = HREAD1(hp, SDHC_RESPONSE + i); 913 } else 914 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE); 915 } 916 917 /* 918 * If the command has data to transfer in any direction, 919 * execute the transfer now. 920 */ 921 if (cmd->c_error == 0 && cmd->c_data != NULL) 922 sdhc_transfer_data(hp, cmd); 923 924 /* Turn off the LED. */ 925 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 926 927 DPRINTF(1,("%s: cmd %u done (flags=%#x error=%d)\n", 928 DEVNAME(hp->sc), cmd->c_opcode, cmd->c_flags, cmd->c_error)); 929 SET(cmd->c_flags, SCF_ITSDONE); 930 } 931 932 int 933 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 934 { 935 struct sdhc_adma2_descriptor32 *desc32 = (void *)hp->adma2; 936 struct sdhc_adma2_descriptor64 *desc64 = (void *)hp->adma2; 937 struct sdhc_softc *sc = hp->sc; 938 u_int16_t blksize = 0; 939 u_int16_t blkcount = 0; 940 u_int16_t mode; 941 u_int16_t command; 942 int error; 943 int seg; 944 int s; 945 946 DPRINTF(1,("%s: start cmd %u arg=%#x data=%p dlen=%d flags=%#x\n", 947 DEVNAME(hp->sc), cmd->c_opcode, cmd->c_arg, cmd->c_data, 948 cmd->c_datalen, cmd->c_flags)); 949 950 /* 951 * The maximum block length for commands should be the minimum 952 * of the host buffer size and the card buffer size. (1.7.2) 953 */ 954 955 /* Fragment the data into proper blocks. */ 956 if (cmd->c_datalen > 0) { 957 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 958 blkcount = cmd->c_datalen / blksize; 959 if (cmd->c_datalen % blksize > 0) { 960 /* XXX: Split this command. (1.7.4) */ 961 printf("%s: data not a multiple of %d bytes\n", 962 DEVNAME(hp->sc), blksize); 963 return EINVAL; 964 } 965 } 966 967 /* Check limit imposed by 9-bit block count. (1.7.2) */ 968 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 969 printf("%s: too much data\n", DEVNAME(hp->sc)); 970 return EINVAL; 971 } 972 973 /* Prepare transfer mode register value. (2.2.5) */ 974 mode = 0; 975 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 976 mode |= SDHC_READ_MODE; 977 if (blkcount > 0) { 978 mode |= SDHC_BLOCK_COUNT_ENABLE; 979 if (blkcount > 1) { 980 mode |= SDHC_MULTI_BLOCK_MODE; 981 if (cmd->c_opcode != SD_IO_RW_EXTENDED) 982 mode |= SDHC_AUTO_CMD12_ENABLE; 983 } 984 } 985 if (cmd->c_dmamap && cmd->c_datalen > 0 && 986 ISSET(hp->flags, SHF_USE_DMA)) 987 mode |= SDHC_DMA_ENABLE; 988 989 /* 990 * Prepare command register value. (2.2.6) 991 */ 992 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << 993 SDHC_COMMAND_INDEX_SHIFT; 994 995 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 996 command |= SDHC_CRC_CHECK_ENABLE; 997 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 998 command |= SDHC_INDEX_CHECK_ENABLE; 999 if (cmd->c_data != NULL) 1000 command |= SDHC_DATA_PRESENT_SELECT; 1001 1002 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 1003 command |= SDHC_NO_RESPONSE; 1004 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 1005 command |= SDHC_RESP_LEN_136; 1006 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 1007 command |= SDHC_RESP_LEN_48_CHK_BUSY; 1008 else 1009 command |= SDHC_RESP_LEN_48; 1010 1011 /* Wait until command and data inhibit bits are clear. (1.5) */ 1012 if ((error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0)) != 0) 1013 return error; 1014 1015 s = splsdmmc(); 1016 1017 /* Alert the user not to remove the card. */ 1018 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1019 1020 /* Set DMA start address if SHF_USE_DMA is set. */ 1021 if (cmd->c_dmamap && ISSET(hp->flags, SHF_USE_DMA)) { 1022 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 1023 bus_addr_t paddr = 1024 cmd->c_dmamap->dm_segs[seg].ds_addr; 1025 uint16_t len = 1026 cmd->c_dmamap->dm_segs[seg].ds_len == 65536 ? 1027 0 : cmd->c_dmamap->dm_segs[seg].ds_len; 1028 uint16_t attr; 1029 1030 attr = SDHC_ADMA2_VALID | SDHC_ADMA2_ACT_TRANS; 1031 if (seg == cmd->c_dmamap->dm_nsegs - 1) 1032 attr |= SDHC_ADMA2_END; 1033 1034 if (ISSET(hp->flags, SHF_USE_DMA64)) { 1035 desc64[seg].attribute = htole16(attr); 1036 desc64[seg].length = htole16(len); 1037 desc64[seg].address_lo = 1038 htole32((uint64_t)paddr & 0xffffffff); 1039 desc64[seg].address_hi = 1040 htole32((uint64_t)paddr >> 32); 1041 } else { 1042 desc32[seg].attribute = htole16(attr); 1043 desc32[seg].length = htole16(len); 1044 desc32[seg].address = htole32(paddr); 1045 } 1046 } 1047 1048 if (ISSET(hp->flags, SHF_USE_DMA64)) 1049 desc64[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 1050 else 1051 desc32[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 1052 1053 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE, 1054 BUS_DMASYNC_PREWRITE); 1055 1056 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT); 1057 if (ISSET(hp->flags, SHF_USE_DMA64)) 1058 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA64); 1059 else 1060 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA32); 1061 1062 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR, 1063 hp->adma_map->dm_segs[0].ds_addr); 1064 } else 1065 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT); 1066 1067 DPRINTF(1,("%s: cmd=%#x mode=%#x blksize=%d blkcount=%d\n", 1068 DEVNAME(hp->sc), command, mode, blksize, blkcount)); 1069 1070 /* We're starting a new command, reset state. */ 1071 hp->intr_status = 0; 1072 1073 /* 1074 * Start a CPU data transfer. Writing to the high order byte 1075 * of the SDHC_COMMAND register triggers the SD command. (1.5) 1076 */ 1077 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 1078 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 1079 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 1080 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1081 HWRITE2(hp, SDHC_COMMAND, command); 1082 1083 splx(s); 1084 return 0; 1085 } 1086 1087 void 1088 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 1089 { 1090 struct sdhc_softc *sc = hp->sc; 1091 u_char *datap = cmd->c_data; 1092 int i, datalen; 1093 int mask; 1094 int error; 1095 1096 if (cmd->c_dmamap) { 1097 int status; 1098 1099 error = 0; 1100 for (;;) { 1101 status = sdhc_wait_intr(hp, 1102 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 1103 SDHC_DMA_TIMEOUT); 1104 if (status & SDHC_TRANSFER_COMPLETE) 1105 break; 1106 if (!status) { 1107 error = ETIMEDOUT; 1108 break; 1109 } 1110 } 1111 1112 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE, 1113 BUS_DMASYNC_POSTWRITE); 1114 goto done; 1115 } 1116 1117 mask = ISSET(cmd->c_flags, SCF_CMD_READ) ? 1118 SDHC_BUFFER_READ_ENABLE : SDHC_BUFFER_WRITE_ENABLE; 1119 error = 0; 1120 datalen = cmd->c_datalen; 1121 1122 DPRINTF(1,("%s: resp=%#x datalen=%d\n", DEVNAME(hp->sc), 1123 MMC_R1(cmd->c_resp), datalen)); 1124 1125 #ifdef SDHC_DEBUG 1126 /* XXX I forgot why I wanted to know when this happens :-( */ 1127 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 1128 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) 1129 printf("%s: CMD52/53 error response flags %#x\n", 1130 DEVNAME(hp->sc), MMC_R1(cmd->c_resp) & 0xff00); 1131 #endif 1132 1133 while (datalen > 0) { 1134 if (!sdhc_wait_intr(hp, SDHC_BUFFER_READ_READY| 1135 SDHC_BUFFER_WRITE_READY, SDHC_BUFFER_TIMEOUT)) { 1136 error = ETIMEDOUT; 1137 break; 1138 } 1139 1140 if ((error = sdhc_wait_state(hp, mask, mask)) != 0) 1141 break; 1142 1143 i = MIN(datalen, cmd->c_blklen); 1144 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1145 sdhc_read_data(hp, datap, i); 1146 else 1147 sdhc_write_data(hp, datap, i); 1148 1149 datap += i; 1150 datalen -= i; 1151 } 1152 1153 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1154 SDHC_TRANSFER_TIMEOUT)) 1155 error = ETIMEDOUT; 1156 1157 done: 1158 if (error != 0) 1159 cmd->c_error = error; 1160 SET(cmd->c_flags, SCF_ITSDONE); 1161 1162 DPRINTF(1,("%s: data transfer done (error=%d)\n", 1163 DEVNAME(hp->sc), cmd->c_error)); 1164 } 1165 1166 void 1167 sdhc_read_data(struct sdhc_host *hp, u_char *datap, int datalen) 1168 { 1169 while (datalen > 3) { 1170 *(u_int32_t *)datap = HREAD4(hp, SDHC_DATA); 1171 datap += 4; 1172 datalen -= 4; 1173 } 1174 if (datalen > 0) { 1175 u_int32_t rv = HREAD4(hp, SDHC_DATA); 1176 do { 1177 *datap++ = rv & 0xff; 1178 rv = rv >> 8; 1179 } while (--datalen > 0); 1180 } 1181 } 1182 1183 void 1184 sdhc_write_data(struct sdhc_host *hp, u_char *datap, int datalen) 1185 { 1186 while (datalen > 3) { 1187 DPRINTF(3,("%08x\n", *(u_int32_t *)datap)); 1188 HWRITE4(hp, SDHC_DATA, *((u_int32_t *)datap)); 1189 datap += 4; 1190 datalen -= 4; 1191 } 1192 if (datalen > 0) { 1193 u_int32_t rv = *datap++; 1194 if (datalen > 1) 1195 rv |= *datap++ << 8; 1196 if (datalen > 2) 1197 rv |= *datap++ << 16; 1198 DPRINTF(3,("rv %08x\n", rv)); 1199 HWRITE4(hp, SDHC_DATA, rv); 1200 } 1201 } 1202 1203 /* Prepare for another command. */ 1204 int 1205 sdhc_soft_reset(struct sdhc_host *hp, int mask) 1206 { 1207 int timo; 1208 1209 DPRINTF(1,("%s: software reset reg=%#x\n", DEVNAME(hp->sc), mask)); 1210 1211 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1212 for (timo = 10; timo > 0; timo--) { 1213 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1214 break; 1215 sdmmc_delay(10000); 1216 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1217 } 1218 if (timo == 0) { 1219 DPRINTF(1,("%s: timeout reg=%#x\n", DEVNAME(hp->sc), 1220 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1221 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1222 return (ETIMEDOUT); 1223 } 1224 1225 return (0); 1226 } 1227 1228 int 1229 sdhc_wait_intr_cold(struct sdhc_host *hp, int mask, int secs) 1230 { 1231 int status, usecs; 1232 1233 mask |= SDHC_ERROR_INTERRUPT; 1234 usecs = secs * 1000000; 1235 status = hp->intr_status; 1236 while ((status & mask) == 0) { 1237 1238 status = HREAD2(hp, SDHC_NINTR_STATUS); 1239 if (ISSET(status, SDHC_NINTR_STATUS_MASK)) { 1240 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1241 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1242 uint16_t error; 1243 error = HREAD2(hp, SDHC_EINTR_STATUS); 1244 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1245 hp->intr_status |= status; 1246 1247 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1248 SDHC_DATA_TIMEOUT_ERROR)) 1249 break; 1250 } 1251 1252 if (ISSET(status, SDHC_BUFFER_READ_READY | 1253 SDHC_BUFFER_WRITE_READY | SDHC_COMMAND_COMPLETE | 1254 SDHC_TRANSFER_COMPLETE)) { 1255 hp->intr_status |= status; 1256 break; 1257 } 1258 1259 if (ISSET(status, SDHC_CARD_INTERRUPT)) { 1260 HSET2(hp, SDHC_NINTR_STATUS_EN, 1261 SDHC_CARD_INTERRUPT); 1262 } 1263 1264 continue; 1265 } 1266 1267 delay(1); 1268 if (usecs-- == 0) { 1269 status |= SDHC_ERROR_INTERRUPT; 1270 break; 1271 } 1272 } 1273 1274 hp->intr_status &= ~(status & mask); 1275 return (status & mask); 1276 } 1277 1278 int 1279 sdhc_wait_intr(struct sdhc_host *hp, int mask, int secs) 1280 { 1281 int status; 1282 int s; 1283 1284 if (cold) 1285 return (sdhc_wait_intr_cold(hp, mask, secs)); 1286 1287 mask |= SDHC_ERROR_INTERRUPT; 1288 1289 s = splsdmmc(); 1290 status = hp->intr_status & mask; 1291 while (status == 0) { 1292 if (tsleep_nsec(&hp->intr_status, PWAIT, "hcintr", 1293 SEC_TO_NSEC(secs)) == EWOULDBLOCK) { 1294 status |= SDHC_ERROR_INTERRUPT; 1295 break; 1296 } 1297 status = hp->intr_status & mask; 1298 } 1299 hp->intr_status &= ~status; 1300 1301 DPRINTF(2,("%s: intr status %#x error %#x\n", DEVNAME(hp->sc), status, 1302 hp->intr_error_status)); 1303 1304 /* Command timeout has higher priority than command complete. */ 1305 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1306 hp->intr_error_status = 0; 1307 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1308 status = 0; 1309 } 1310 1311 splx(s); 1312 return status; 1313 } 1314 1315 /* 1316 * Established by attachment driver at interrupt priority IPL_SDMMC. 1317 */ 1318 int 1319 sdhc_intr(void *arg) 1320 { 1321 struct sdhc_softc *sc = arg; 1322 int host; 1323 int done = 0; 1324 1325 /* We got an interrupt, but we don't know from which slot. */ 1326 for (host = 0; host < sc->sc_nhosts; host++) { 1327 struct sdhc_host *hp = sc->sc_host[host]; 1328 u_int16_t status; 1329 1330 if (hp == NULL) 1331 continue; 1332 1333 /* Find out which interrupts are pending. */ 1334 status = HREAD2(hp, SDHC_NINTR_STATUS); 1335 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1336 continue; /* no interrupt for us */ 1337 1338 /* Acknowledge the interrupts we are about to handle. */ 1339 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1340 DPRINTF(2,("%s: interrupt status=%b\n", DEVNAME(hp->sc), 1341 status, SDHC_NINTR_STATUS_BITS)); 1342 1343 /* Claim this interrupt. */ 1344 done = 1; 1345 1346 /* 1347 * Service error interrupts. 1348 */ 1349 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1350 u_int16_t error; 1351 1352 /* Acknowledge error interrupts. */ 1353 error = HREAD2(hp, SDHC_EINTR_STATUS); 1354 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1355 DPRINTF(2,("%s: error interrupt, status=%b\n", 1356 DEVNAME(hp->sc), error, SDHC_EINTR_STATUS_BITS)); 1357 1358 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1359 SDHC_DATA_TIMEOUT_ERROR)) { 1360 hp->intr_error_status |= error; 1361 hp->intr_status |= status; 1362 wakeup(&hp->intr_status); 1363 } 1364 } 1365 1366 /* 1367 * Wake up the sdmmc event thread to scan for cards. 1368 */ 1369 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) 1370 sdmmc_needs_discover(hp->sdmmc); 1371 1372 /* 1373 * Wake up the blocking process to service command 1374 * related interrupt(s). 1375 */ 1376 if (ISSET(status, SDHC_BUFFER_READ_READY| 1377 SDHC_BUFFER_WRITE_READY|SDHC_COMMAND_COMPLETE| 1378 SDHC_TRANSFER_COMPLETE)) { 1379 hp->intr_status |= status; 1380 wakeup(&hp->intr_status); 1381 } 1382 1383 /* 1384 * Service SD card interrupts. 1385 */ 1386 if (ISSET(status, SDHC_CARD_INTERRUPT)) { 1387 DPRINTF(0,("%s: card interrupt\n", DEVNAME(hp->sc))); 1388 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1389 sdmmc_card_intr(hp->sdmmc); 1390 } 1391 } 1392 return done; 1393 } 1394 1395 void 1396 sdhc_needs_discover(struct sdhc_softc *sc) 1397 { 1398 int host; 1399 1400 for (host = 0; host < sc->sc_nhosts; host++) 1401 sdmmc_needs_discover(sc->sc_host[host]->sdmmc); 1402 } 1403 1404 #ifdef SDHC_DEBUG 1405 void 1406 sdhc_dump_regs(struct sdhc_host *hp) 1407 { 1408 printf("0x%02x PRESENT_STATE: %b\n", SDHC_PRESENT_STATE, 1409 HREAD4(hp, SDHC_PRESENT_STATE), SDHC_PRESENT_STATE_BITS); 1410 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 1411 HREAD1(hp, SDHC_POWER_CTL)); 1412 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 1413 HREAD2(hp, SDHC_NINTR_STATUS)); 1414 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 1415 HREAD2(hp, SDHC_EINTR_STATUS)); 1416 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 1417 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 1418 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 1419 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 1420 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 1421 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 1422 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 1423 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 1424 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 1425 HREAD4(hp, SDHC_CAPABILITIES)); 1426 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 1427 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 1428 } 1429 #endif 1430 1431 int 1432 sdhc_hibernate_init(sdmmc_chipset_handle_t sch, void *fake_softc) 1433 { 1434 struct sdhc_host *hp, *fhp; 1435 fhp = fake_softc; 1436 hp = sch; 1437 *fhp = *hp; 1438 1439 return (0); 1440 } 1441