1 /* $OpenBSD: sdhc.c,v 1.73 2022/01/19 10:51:04 patrick Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * SD Host Controller driver based on the SD Host Controller Standard 21 * Simplified Specification Version 1.00 (www.sdcard.org). 22 */ 23 24 #include <sys/param.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/malloc.h> 28 #include <sys/proc.h> 29 #include <sys/systm.h> 30 #include <sys/time.h> 31 32 #include <dev/sdmmc/sdhcreg.h> 33 #include <dev/sdmmc/sdhcvar.h> 34 #include <dev/sdmmc/sdmmcchip.h> 35 #include <dev/sdmmc/sdmmcreg.h> 36 #include <dev/sdmmc/sdmmcvar.h> 37 #include <dev/sdmmc/sdmmc_ioreg.h> 38 39 /* Timeouts in seconds */ 40 #define SDHC_COMMAND_TIMEOUT 1 41 #define SDHC_BUFFER_TIMEOUT 1 42 #define SDHC_TRANSFER_TIMEOUT 1 43 #define SDHC_DMA_TIMEOUT 3 44 45 struct sdhc_host { 46 struct sdhc_softc *sc; /* host controller device */ 47 struct device *sdmmc; /* generic SD/MMC device */ 48 bus_space_tag_t iot; /* host register set tag */ 49 bus_space_handle_t ioh; /* host register set handle */ 50 u_int16_t version; /* specification version */ 51 u_int clkbase; /* base clock frequency in KHz */ 52 int maxblklen; /* maximum block length */ 53 int flags; /* flags for this host */ 54 u_int32_t ocr; /* OCR value from capabilities */ 55 u_int8_t regs[14]; /* host controller state */ 56 u_int16_t intr_status; /* soft interrupt status */ 57 u_int16_t intr_error_status; /* soft error status */ 58 59 bus_dmamap_t adma_map; 60 bus_dma_segment_t adma_segs[1]; 61 caddr_t adma2; 62 63 uint16_t block_size; 64 uint16_t block_count; 65 uint16_t transfer_mode; 66 }; 67 68 /* flag values */ 69 #define SHF_USE_DMA 0x0001 70 #define SHF_USE_DMA64 0x0002 71 #define SHF_USE_32BIT_ACCESS 0x0004 72 73 #define HREAD1(hp, reg) \ 74 (sdhc_read_1((hp), (reg))) 75 #define HREAD2(hp, reg) \ 76 (sdhc_read_2((hp), (reg))) 77 #define HREAD4(hp, reg) \ 78 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 79 #define HWRITE1(hp, reg, val) \ 80 sdhc_write_1((hp), (reg), (val)) 81 #define HWRITE2(hp, reg, val) \ 82 sdhc_write_2((hp), (reg), (val)) 83 #define HWRITE4(hp, reg, val) \ 84 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 85 #define HCLR1(hp, reg, bits) \ 86 HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)) 87 #define HCLR2(hp, reg, bits) \ 88 HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)) 89 #define HSET1(hp, reg, bits) \ 90 HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)) 91 #define HSET2(hp, reg, bits) \ 92 HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)) 93 94 int sdhc_host_reset(sdmmc_chipset_handle_t); 95 u_int32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 96 int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 97 int sdhc_card_detect(sdmmc_chipset_handle_t); 98 int sdhc_bus_power(sdmmc_chipset_handle_t, u_int32_t); 99 int sdhc_bus_clock(sdmmc_chipset_handle_t, int, int); 100 int sdhc_bus_width(sdmmc_chipset_handle_t, int); 101 void sdhc_card_intr_mask(sdmmc_chipset_handle_t, int); 102 void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 103 int sdhc_signal_voltage(sdmmc_chipset_handle_t, int); 104 void sdhc_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *); 105 int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 106 int sdhc_wait_state(struct sdhc_host *, u_int32_t, u_int32_t); 107 int sdhc_soft_reset(struct sdhc_host *, int); 108 int sdhc_wait_intr_cold(struct sdhc_host *, int, int); 109 int sdhc_wait_intr(struct sdhc_host *, int, int); 110 void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 111 void sdhc_read_data(struct sdhc_host *, u_char *, int); 112 void sdhc_write_data(struct sdhc_host *, u_char *, int); 113 int sdhc_hibernate_init(sdmmc_chipset_handle_t, void *); 114 115 #ifdef SDHC_DEBUG 116 int sdhcdebug = 0; 117 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 118 void sdhc_dump_regs(struct sdhc_host *); 119 #else 120 #define DPRINTF(n,s) do {} while(0) 121 #endif 122 123 struct sdmmc_chip_functions sdhc_functions = { 124 .host_reset = sdhc_host_reset, 125 .host_ocr = sdhc_host_ocr, 126 .host_maxblklen = sdhc_host_maxblklen, 127 .card_detect = sdhc_card_detect, 128 .bus_power = sdhc_bus_power, 129 .bus_clock = sdhc_bus_clock, 130 .bus_width = sdhc_bus_width, 131 .exec_command = sdhc_exec_command, 132 .card_intr_mask = sdhc_card_intr_mask, 133 .card_intr_ack = sdhc_card_intr_ack, 134 .signal_voltage = sdhc_signal_voltage, 135 .hibernate_init = sdhc_hibernate_init, 136 }; 137 138 struct cfdriver sdhc_cd = { 139 NULL, "sdhc", DV_DULL 140 }; 141 142 /* 143 * Some controllers live on a bus that only allows 32-bit 144 * transactions. In that case we use a RMW cycle for 8-bit and 16-bit 145 * register writes. However that doesn't work for the Transfer Mode 146 * register as this register lives in the same 32-bit word as the 147 * Command register and writing the Command register triggers SD 148 * command generation. We avoid this issue by using a shadow variable 149 * for the Transfer Mode register that we write out when we write the 150 * Command register. 151 * 152 * The Arasan controller controller integrated on the Broadcom SoCs 153 * used in the Raspberry Pi has an interesting bug where writing the 154 * same 32-bit register twice doesn't work. This means that we lose 155 * writes to the Block Sine and/or Block Count register. We work 156 * around that issue by using shadow variables as well. 157 */ 158 159 uint8_t 160 sdhc_read_1(struct sdhc_host *hp, bus_size_t offset) 161 { 162 uint32_t reg; 163 164 if (hp->flags & SHF_USE_32BIT_ACCESS) { 165 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~3); 166 return (reg >> ((offset & 3) * 8)) & 0xff; 167 } 168 169 return bus_space_read_1(hp->iot, hp->ioh, offset); 170 } 171 172 uint16_t 173 sdhc_read_2(struct sdhc_host *hp, bus_size_t offset) 174 { 175 uint32_t reg; 176 177 if (hp->flags & SHF_USE_32BIT_ACCESS) { 178 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~2); 179 return (reg >> ((offset & 2) * 8)) & 0xffff; 180 } 181 182 return bus_space_read_2(hp->iot, hp->ioh, offset); 183 } 184 185 void 186 sdhc_write_1(struct sdhc_host *hp, bus_size_t offset, uint8_t value) 187 { 188 uint32_t reg; 189 190 if (hp->flags & SHF_USE_32BIT_ACCESS) { 191 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~3); 192 reg &= ~(0xff << ((offset & 3) * 8)); 193 reg |= (value << ((offset & 3) * 8)); 194 bus_space_write_4(hp->iot, hp->ioh, offset & ~3, reg); 195 return; 196 } 197 198 bus_space_write_1(hp->iot, hp->ioh, offset, value); 199 } 200 201 void 202 sdhc_write_2(struct sdhc_host *hp, bus_size_t offset, uint16_t value) 203 { 204 uint32_t reg; 205 206 if (hp->flags & SHF_USE_32BIT_ACCESS) { 207 switch (offset) { 208 case SDHC_BLOCK_SIZE: 209 hp->block_size = value; 210 return; 211 case SDHC_BLOCK_COUNT: 212 hp->block_count = value; 213 return; 214 case SDHC_TRANSFER_MODE: 215 hp->transfer_mode = value; 216 return; 217 case SDHC_COMMAND: 218 bus_space_write_4(hp->iot, hp->ioh, SDHC_BLOCK_SIZE, 219 (hp->block_count << 16) | hp->block_size); 220 bus_space_write_4(hp->iot, hp->ioh, SDHC_TRANSFER_MODE, 221 (value << 16) | hp->transfer_mode); 222 return; 223 } 224 225 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~2); 226 reg &= ~(0xffff << ((offset & 2) * 8)); 227 reg |= (value << ((offset & 2) * 8)); 228 bus_space_write_4(hp->iot, hp->ioh, offset & ~2, reg); 229 return; 230 } 231 232 bus_space_write_2(hp->iot, hp->ioh, offset, value); 233 } 234 235 /* 236 * Called by attachment driver. For each SD card slot there is one SD 237 * host controller standard register set. (1.3) 238 */ 239 int 240 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 241 bus_space_handle_t ioh, bus_size_t iosize, int usedma, uint64_t capmask, 242 uint64_t capset) 243 { 244 struct sdmmcbus_attach_args saa; 245 struct sdhc_host *hp; 246 uint32_t caps; 247 int error = 1; 248 int max_clock; 249 250 /* Allocate one more host structure. */ 251 sc->sc_nhosts++; 252 hp = malloc(sizeof(*hp), M_DEVBUF, M_WAITOK | M_ZERO); 253 sc->sc_host[sc->sc_nhosts - 1] = hp; 254 255 if (ISSET(sc->sc_flags, SDHC_F_32BIT_ACCESS)) 256 SET(hp->flags, SHF_USE_32BIT_ACCESS); 257 258 /* Fill in the new host structure. */ 259 hp->sc = sc; 260 hp->iot = iot; 261 hp->ioh = ioh; 262 263 /* Store specification version. */ 264 hp->version = HREAD2(hp, SDHC_HOST_CTL_VERSION); 265 266 /* 267 * Reset the host controller and enable interrupts. 268 */ 269 (void)sdhc_host_reset(hp); 270 271 /* Determine host capabilities. */ 272 caps = HREAD4(hp, SDHC_CAPABILITIES); 273 caps &= ~capmask; 274 caps |= capset; 275 276 /* Use DMA if the host system and the controller support it. */ 277 if (usedma && ISSET(caps, SDHC_ADMA2_SUPP)) { 278 SET(hp->flags, SHF_USE_DMA); 279 if (ISSET(caps, SDHC_64BIT_DMA_SUPP)) 280 SET(hp->flags, SHF_USE_DMA64); 281 } 282 283 /* 284 * Determine the base clock frequency. (2.2.24) 285 */ 286 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 287 /* SDHC 3.0 supports 10-255 MHz. */ 288 max_clock = 255000; 289 if (SDHC_BASE_FREQ_KHZ_V3(caps) != 0) 290 hp->clkbase = SDHC_BASE_FREQ_KHZ_V3(caps); 291 } else { 292 /* SDHC 1.0/2.0 supports only 10-63 MHz. */ 293 max_clock = 63000; 294 if (SDHC_BASE_FREQ_KHZ(caps) != 0) 295 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 296 } 297 if (hp->clkbase == 0) { 298 /* Make sure we can clock down to 400 kHz. */ 299 max_clock = 400 * SDHC_SDCLK_DIV_MAX_V3; 300 hp->clkbase = sc->sc_clkbase; 301 } 302 if (hp->clkbase == 0) { 303 /* The attachment driver must tell us. */ 304 printf("%s: base clock frequency unknown\n", 305 sc->sc_dev.dv_xname); 306 goto err; 307 } else if (hp->clkbase < 10000 || hp->clkbase > max_clock) { 308 printf("%s: base clock frequency out of range: %u MHz\n", 309 sc->sc_dev.dv_xname, hp->clkbase / 1000); 310 goto err; 311 } 312 313 printf("%s: SDHC %d.0, %d MHz base clock\n", DEVNAME(sc), 314 SDHC_SPEC_VERSION(hp->version) + 1, hp->clkbase / 1000); 315 316 /* 317 * XXX Set the data timeout counter value according to 318 * capabilities. (2.2.15) 319 */ 320 321 /* 322 * Determine SD bus voltage levels supported by the controller. 323 */ 324 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)) 325 SET(hp->ocr, MMC_OCR_1_65V_1_95V); 326 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) 327 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 328 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) 329 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 330 331 /* 332 * Determine the maximum block length supported by the host 333 * controller. (2.2.24) 334 */ 335 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 336 case SDHC_MAX_BLK_LEN_512: 337 hp->maxblklen = 512; 338 break; 339 case SDHC_MAX_BLK_LEN_1024: 340 hp->maxblklen = 1024; 341 break; 342 case SDHC_MAX_BLK_LEN_2048: 343 hp->maxblklen = 2048; 344 break; 345 default: 346 hp->maxblklen = 1; 347 break; 348 } 349 350 if (ISSET(hp->flags, SHF_USE_DMA)) { 351 int rseg; 352 353 /* Allocate ADMA2 descriptor memory */ 354 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 355 PAGE_SIZE, hp->adma_segs, 1, &rseg, 356 BUS_DMA_WAITOK | BUS_DMA_ZERO); 357 if (error) 358 goto adma_done; 359 error = bus_dmamem_map(sc->sc_dmat, hp->adma_segs, rseg, 360 PAGE_SIZE, &hp->adma2, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 361 if (error) { 362 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg); 363 goto adma_done; 364 } 365 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 366 0, BUS_DMA_WAITOK, &hp->adma_map); 367 if (error) { 368 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE); 369 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg); 370 goto adma_done; 371 } 372 error = bus_dmamap_load(sc->sc_dmat, hp->adma_map, 373 hp->adma2, PAGE_SIZE, NULL, 374 BUS_DMA_WAITOK | BUS_DMA_WRITE); 375 if (error) { 376 bus_dmamap_destroy(sc->sc_dmat, hp->adma_map); 377 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE); 378 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg); 379 goto adma_done; 380 } 381 382 adma_done: 383 if (error) { 384 printf("%s: can't allocate DMA descriptor table\n", 385 DEVNAME(hp->sc)); 386 CLR(hp->flags, SHF_USE_DMA); 387 } 388 } 389 390 /* 391 * Attach the generic SD/MMC bus driver. (The bus driver must 392 * not invoke any chipset functions before it is attached.) 393 */ 394 bzero(&saa, sizeof(saa)); 395 saa.saa_busname = "sdmmc"; 396 saa.sct = &sdhc_functions; 397 saa.sch = hp; 398 saa.caps = SMC_CAPS_4BIT_MODE; 399 saa.dmat = sc->sc_dmat; 400 if (ISSET(hp->flags, SHF_USE_DMA)) 401 saa.caps |= SMC_CAPS_DMA; 402 403 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 404 saa.caps |= SMC_CAPS_SD_HIGHSPEED; 405 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 406 saa.caps |= SMC_CAPS_MMC_HIGHSPEED; 407 408 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 409 uint32_t caps2 = HREAD4(hp, SDHC_CAPABILITIES2); 410 caps2 &= ~(capmask >> 32); 411 caps2 |= capset >> 32; 412 413 if (ISSET(caps, SDHC_8BIT_MODE_SUPP)) 414 saa.caps |= SMC_CAPS_8BIT_MODE; 415 416 if (ISSET(caps2, SDHC_DDR50_SUPP)) 417 saa.caps |= SMC_CAPS_MMC_DDR52; 418 } 419 420 if (ISSET(sc->sc_flags, SDHC_F_NONREMOVABLE)) 421 saa.caps |= SMC_CAPS_NONREMOVABLE; 422 423 hp->sdmmc = config_found(&sc->sc_dev, &saa, NULL); 424 if (hp->sdmmc == NULL) { 425 error = 0; 426 goto err; 427 } 428 429 return 0; 430 431 err: 432 free(hp, M_DEVBUF, sizeof *hp); 433 sc->sc_host[sc->sc_nhosts - 1] = NULL; 434 sc->sc_nhosts--; 435 return (error); 436 } 437 438 int 439 sdhc_activate(struct device *self, int act) 440 { 441 struct sdhc_softc *sc = (struct sdhc_softc *)self; 442 struct sdhc_host *hp; 443 int n, i, rv = 0; 444 445 switch (act) { 446 case DVACT_SUSPEND: 447 rv = config_activate_children(self, act); 448 449 /* Save the host controller state. */ 450 for (n = 0; n < sc->sc_nhosts; n++) { 451 hp = sc->sc_host[n]; 452 for (i = 0; i < sizeof hp->regs; i++) 453 hp->regs[i] = HREAD1(hp, i); 454 } 455 break; 456 case DVACT_RESUME: 457 /* Restore the host controller state. */ 458 for (n = 0; n < sc->sc_nhosts; n++) { 459 hp = sc->sc_host[n]; 460 (void)sdhc_host_reset(hp); 461 for (i = 0; i < sizeof hp->regs; i++) 462 HWRITE1(hp, i, hp->regs[i]); 463 } 464 rv = config_activate_children(self, act); 465 break; 466 case DVACT_POWERDOWN: 467 rv = config_activate_children(self, act); 468 sdhc_shutdown(self); 469 break; 470 default: 471 rv = config_activate_children(self, act); 472 break; 473 } 474 return (rv); 475 } 476 477 /* 478 * Shutdown hook established by or called from attachment driver. 479 */ 480 void 481 sdhc_shutdown(void *arg) 482 { 483 struct sdhc_softc *sc = arg; 484 struct sdhc_host *hp; 485 int i; 486 487 /* XXX chip locks up if we don't disable it before reboot. */ 488 for (i = 0; i < sc->sc_nhosts; i++) { 489 hp = sc->sc_host[i]; 490 (void)sdhc_host_reset(hp); 491 } 492 } 493 494 /* 495 * Reset the host controller. Called during initialization, when 496 * cards are removed, upon resume, and during error recovery. 497 */ 498 int 499 sdhc_host_reset(sdmmc_chipset_handle_t sch) 500 { 501 struct sdhc_host *hp = sch; 502 u_int16_t imask; 503 int error; 504 int s; 505 506 s = splsdmmc(); 507 508 /* Disable all interrupts. */ 509 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 510 511 /* 512 * Reset the entire host controller and wait up to 100ms for 513 * the controller to clear the reset bit. 514 */ 515 if ((error = sdhc_soft_reset(hp, SDHC_RESET_ALL)) != 0) { 516 splx(s); 517 return (error); 518 } 519 520 /* Set data timeout counter value to max for now. */ 521 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 522 523 /* Enable interrupts. */ 524 imask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 525 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 526 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 527 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 528 529 HWRITE2(hp, SDHC_NINTR_STATUS_EN, imask); 530 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 531 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, imask); 532 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 533 534 splx(s); 535 return 0; 536 } 537 538 u_int32_t 539 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 540 { 541 struct sdhc_host *hp = sch; 542 return hp->ocr; 543 } 544 545 int 546 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 547 { 548 struct sdhc_host *hp = sch; 549 return hp->maxblklen; 550 } 551 552 /* 553 * Return non-zero if the card is currently inserted. 554 */ 555 int 556 sdhc_card_detect(sdmmc_chipset_handle_t sch) 557 { 558 struct sdhc_host *hp = sch; 559 560 if (hp->sc->sc_card_detect) 561 return hp->sc->sc_card_detect(hp->sc); 562 563 return ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED) ? 564 1 : 0; 565 } 566 567 /* 568 * Set or change SD bus voltage and enable or disable SD bus power. 569 * Return zero on success. 570 */ 571 int 572 sdhc_bus_power(sdmmc_chipset_handle_t sch, u_int32_t ocr) 573 { 574 struct sdhc_host *hp = sch; 575 u_int8_t vdd; 576 int s; 577 578 s = splsdmmc(); 579 580 /* 581 * Disable bus power before voltage change. 582 */ 583 if (!(hp->sc->sc_flags & SDHC_F_NOPWR0)) 584 HWRITE1(hp, SDHC_POWER_CTL, 0); 585 586 /* If power is disabled, reset the host and return now. */ 587 if (ocr == 0) { 588 splx(s); 589 (void)sdhc_host_reset(hp); 590 return 0; 591 } 592 593 /* 594 * Select the maximum voltage according to capabilities. 595 */ 596 ocr &= hp->ocr; 597 if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) 598 vdd = SDHC_VOLTAGE_3_3V; 599 else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) 600 vdd = SDHC_VOLTAGE_3_0V; 601 else if (ISSET(ocr, MMC_OCR_1_65V_1_95V)) 602 vdd = SDHC_VOLTAGE_1_8V; 603 else { 604 /* Unsupported voltage level requested. */ 605 splx(s); 606 return EINVAL; 607 } 608 609 /* 610 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 611 * voltage ramp until power rises. 612 */ 613 HWRITE1(hp, SDHC_POWER_CTL, (vdd << SDHC_VOLTAGE_SHIFT) | 614 SDHC_BUS_POWER); 615 sdmmc_delay(10000); 616 617 /* 618 * The host system may not power the bus due to battery low, 619 * etc. In that case, the host controller should clear the 620 * bus power bit. 621 */ 622 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 623 splx(s); 624 return ENXIO; 625 } 626 627 splx(s); 628 return 0; 629 } 630 631 /* 632 * Return the smallest possible base clock frequency divisor value 633 * for the CLOCK_CTL register to produce `freq' (KHz). 634 */ 635 static int 636 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq) 637 { 638 int div; 639 640 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 641 if (hp->clkbase <= freq) 642 return 0; 643 644 for (div = 2; div <= SDHC_SDCLK_DIV_MAX_V3; div += 2) 645 if ((hp->clkbase / div) <= freq) 646 return (div / 2); 647 } else { 648 for (div = 1; div <= SDHC_SDCLK_DIV_MAX; div *= 2) 649 if ((hp->clkbase / div) <= freq) 650 return (div / 2); 651 } 652 653 /* No divisor found. */ 654 return -1; 655 } 656 657 /* 658 * Set or change SDCLK frequency or disable the SD clock. 659 * Return zero on success. 660 */ 661 int 662 sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing) 663 { 664 struct sdhc_host *hp = sch; 665 struct sdhc_softc *sc = hp->sc; 666 int s; 667 int div; 668 int sdclk; 669 int timo; 670 int error = 0; 671 672 s = splsdmmc(); 673 674 if (hp->sc->sc_bus_clock_pre) 675 hp->sc->sc_bus_clock_pre(hp->sc, freq, timing); 676 677 #ifdef DIAGNOSTIC 678 /* Must not stop the clock if commands are in progress. */ 679 if (ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK) && 680 sdhc_card_detect(hp)) 681 printf("sdhc_sdclk_frequency_select: command in progress\n"); 682 #endif 683 684 /* 685 * Stop SD clock before changing the frequency. 686 */ 687 HWRITE2(hp, SDHC_CLOCK_CTL, 0); 688 if (freq == SDMMC_SDCLK_OFF) 689 goto ret; 690 691 if (!ISSET(sc->sc_flags, SDHC_F_NO_HS_BIT)) { 692 if (timing == SDMMC_TIMING_LEGACY) 693 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 694 else 695 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 696 } 697 698 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 699 switch (timing) { 700 case SDMMC_TIMING_MMC_DDR52: 701 HCLR2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_MASK); 702 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_DDR50); 703 break; 704 } 705 } 706 707 /* 708 * Set the minimum base clock frequency divisor. 709 */ 710 if ((div = sdhc_clock_divisor(hp, freq)) < 0) { 711 /* Invalid base clock frequency or `freq' value. */ 712 error = EINVAL; 713 goto ret; 714 } 715 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) 716 sdclk = SDHC_SDCLK_DIV_V3(div); 717 else 718 sdclk = SDHC_SDCLK_DIV(div); 719 HWRITE2(hp, SDHC_CLOCK_CTL, sdclk); 720 721 /* 722 * Start internal clock. Wait 10ms for stabilization. 723 */ 724 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 725 for (timo = 1000; timo > 0; timo--) { 726 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), SDHC_INTCLK_STABLE)) 727 break; 728 sdmmc_delay(10); 729 } 730 if (timo == 0) { 731 error = ETIMEDOUT; 732 goto ret; 733 } 734 735 /* 736 * Enable SD clock. 737 */ 738 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 739 740 if (hp->sc->sc_bus_clock_post) 741 hp->sc->sc_bus_clock_post(hp->sc, freq, timing); 742 743 ret: 744 splx(s); 745 return error; 746 } 747 748 int 749 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 750 { 751 struct sdhc_host *hp = (struct sdhc_host *)sch; 752 int reg; 753 int s; 754 755 if (width != 1 && width != 4 && width != 8) 756 return EINVAL; 757 758 s = splsdmmc(); 759 760 reg = HREAD1(hp, SDHC_HOST_CTL); 761 reg &= ~SDHC_4BIT_MODE; 762 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 763 reg &= ~SDHC_8BIT_MODE; 764 } 765 if (width == 4) { 766 reg |= SDHC_4BIT_MODE; 767 } else if (width == 8) { 768 KASSERT(SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3); 769 reg |= SDHC_8BIT_MODE; 770 } 771 HWRITE1(hp, SDHC_HOST_CTL, reg); 772 773 splx(s); 774 775 return 0; 776 } 777 778 void 779 sdhc_card_intr_mask(sdmmc_chipset_handle_t sch, int enable) 780 { 781 struct sdhc_host *hp = sch; 782 783 if (enable) { 784 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 785 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 786 } else { 787 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 788 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 789 } 790 } 791 792 void 793 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 794 { 795 struct sdhc_host *hp = sch; 796 797 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 798 } 799 800 int 801 sdhc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 802 { 803 struct sdhc_host *hp = sch; 804 805 if (hp->sc->sc_signal_voltage) 806 return hp->sc->sc_signal_voltage(hp->sc, signal_voltage); 807 808 if (SDHC_SPEC_VERSION(hp->version) < SDHC_SPEC_V3) 809 return EINVAL; 810 811 switch (signal_voltage) { 812 case SDMMC_SIGNAL_VOLTAGE_180: 813 HSET2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN); 814 break; 815 case SDMMC_SIGNAL_VOLTAGE_330: 816 HCLR2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN); 817 break; 818 default: 819 return EINVAL; 820 } 821 822 /* Regulator output shall be stable within 5 ms. */ 823 sdmmc_delay(5000); 824 825 /* Host controller clears this bit if 1.8V signalling fails. */ 826 if (signal_voltage == SDMMC_SIGNAL_VOLTAGE_180 && 827 !ISSET(HREAD2(hp, SDHC_HOST_CTL2), SDHC_1_8V_SIGNAL_EN)) 828 return EIO; 829 830 return 0; 831 } 832 833 int 834 sdhc_wait_state(struct sdhc_host *hp, u_int32_t mask, u_int32_t value) 835 { 836 u_int32_t state; 837 int timeout; 838 839 for (timeout = 10; timeout > 0; timeout--) { 840 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) 841 == value) 842 return 0; 843 sdmmc_delay(10000); 844 } 845 DPRINTF(0,("%s: timeout waiting for %x (state=%b)\n", DEVNAME(hp->sc), 846 value, state, SDHC_PRESENT_STATE_BITS)); 847 return ETIMEDOUT; 848 } 849 850 void 851 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 852 { 853 struct sdhc_host *hp = sch; 854 int error; 855 856 /* 857 * Start the MMC command, or mark `cmd' as failed and return. 858 */ 859 error = sdhc_start_command(hp, cmd); 860 if (error != 0) { 861 cmd->c_error = error; 862 SET(cmd->c_flags, SCF_ITSDONE); 863 return; 864 } 865 866 /* 867 * Wait until the command phase is done, or until the command 868 * is marked done for any other reason. 869 */ 870 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, 871 SDHC_COMMAND_TIMEOUT)) { 872 cmd->c_error = ETIMEDOUT; 873 SET(cmd->c_flags, SCF_ITSDONE); 874 return; 875 } 876 877 /* 878 * The host controller removes bits [0:7] from the response 879 * data (CRC) and we pass the data up unchanged to the bus 880 * driver (without padding). 881 */ 882 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 883 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 884 u_char *p = (u_char *)cmd->c_resp; 885 int i; 886 887 for (i = 0; i < 15; i++) 888 *p++ = HREAD1(hp, SDHC_RESPONSE + i); 889 } else 890 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE); 891 } 892 893 /* 894 * If the command has data to transfer in any direction, 895 * execute the transfer now. 896 */ 897 if (cmd->c_error == 0 && cmd->c_data != NULL) 898 sdhc_transfer_data(hp, cmd); 899 900 /* Turn off the LED. */ 901 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 902 903 DPRINTF(1,("%s: cmd %u done (flags=%#x error=%d)\n", 904 DEVNAME(hp->sc), cmd->c_opcode, cmd->c_flags, cmd->c_error)); 905 SET(cmd->c_flags, SCF_ITSDONE); 906 } 907 908 int 909 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 910 { 911 struct sdhc_adma2_descriptor32 *desc32 = (void *)hp->adma2; 912 struct sdhc_adma2_descriptor64 *desc64 = (void *)hp->adma2; 913 struct sdhc_softc *sc = hp->sc; 914 u_int16_t blksize = 0; 915 u_int16_t blkcount = 0; 916 u_int16_t mode; 917 u_int16_t command; 918 int error; 919 int seg; 920 int s; 921 922 DPRINTF(1,("%s: start cmd %u arg=%#x data=%p dlen=%d flags=%#x\n", 923 DEVNAME(hp->sc), cmd->c_opcode, cmd->c_arg, cmd->c_data, 924 cmd->c_datalen, cmd->c_flags)); 925 926 /* 927 * The maximum block length for commands should be the minimum 928 * of the host buffer size and the card buffer size. (1.7.2) 929 */ 930 931 /* Fragment the data into proper blocks. */ 932 if (cmd->c_datalen > 0) { 933 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 934 blkcount = cmd->c_datalen / blksize; 935 if (cmd->c_datalen % blksize > 0) { 936 /* XXX: Split this command. (1.7.4) */ 937 printf("%s: data not a multiple of %d bytes\n", 938 DEVNAME(hp->sc), blksize); 939 return EINVAL; 940 } 941 } 942 943 /* Check limit imposed by 9-bit block count. (1.7.2) */ 944 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 945 printf("%s: too much data\n", DEVNAME(hp->sc)); 946 return EINVAL; 947 } 948 949 /* Prepare transfer mode register value. (2.2.5) */ 950 mode = 0; 951 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 952 mode |= SDHC_READ_MODE; 953 if (blkcount > 0) { 954 mode |= SDHC_BLOCK_COUNT_ENABLE; 955 if (blkcount > 1) { 956 mode |= SDHC_MULTI_BLOCK_MODE; 957 if (cmd->c_opcode != SD_IO_RW_EXTENDED) 958 mode |= SDHC_AUTO_CMD12_ENABLE; 959 } 960 } 961 if (cmd->c_dmamap && cmd->c_datalen > 0 && 962 ISSET(hp->flags, SHF_USE_DMA)) 963 mode |= SDHC_DMA_ENABLE; 964 965 /* 966 * Prepare command register value. (2.2.6) 967 */ 968 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << 969 SDHC_COMMAND_INDEX_SHIFT; 970 971 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 972 command |= SDHC_CRC_CHECK_ENABLE; 973 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 974 command |= SDHC_INDEX_CHECK_ENABLE; 975 if (cmd->c_data != NULL) 976 command |= SDHC_DATA_PRESENT_SELECT; 977 978 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 979 command |= SDHC_NO_RESPONSE; 980 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 981 command |= SDHC_RESP_LEN_136; 982 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 983 command |= SDHC_RESP_LEN_48_CHK_BUSY; 984 else 985 command |= SDHC_RESP_LEN_48; 986 987 /* Wait until command and data inhibit bits are clear. (1.5) */ 988 if ((error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0)) != 0) 989 return error; 990 991 s = splsdmmc(); 992 993 /* Alert the user not to remove the card. */ 994 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 995 996 /* Set DMA start address if SHF_USE_DMA is set. */ 997 if (cmd->c_dmamap && ISSET(hp->flags, SHF_USE_DMA)) { 998 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 999 bus_addr_t paddr = 1000 cmd->c_dmamap->dm_segs[seg].ds_addr; 1001 uint16_t len = 1002 cmd->c_dmamap->dm_segs[seg].ds_len == 65536 ? 1003 0 : cmd->c_dmamap->dm_segs[seg].ds_len; 1004 uint16_t attr; 1005 1006 attr = SDHC_ADMA2_VALID | SDHC_ADMA2_ACT_TRANS; 1007 if (seg == cmd->c_dmamap->dm_nsegs - 1) 1008 attr |= SDHC_ADMA2_END; 1009 1010 if (ISSET(hp->flags, SHF_USE_DMA64)) { 1011 desc64[seg].attribute = htole16(attr); 1012 desc64[seg].length = htole16(len); 1013 desc64[seg].address_lo = 1014 htole32((uint64_t)paddr & 0xffffffff); 1015 desc64[seg].address_hi = 1016 htole32((uint64_t)paddr >> 32); 1017 } else { 1018 desc32[seg].attribute = htole16(attr); 1019 desc32[seg].length = htole16(len); 1020 desc32[seg].address = htole32(paddr); 1021 } 1022 } 1023 1024 if (ISSET(hp->flags, SHF_USE_DMA64)) 1025 desc64[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 1026 else 1027 desc32[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 1028 1029 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE, 1030 BUS_DMASYNC_PREWRITE); 1031 1032 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT); 1033 if (ISSET(hp->flags, SHF_USE_DMA64)) 1034 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA64); 1035 else 1036 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA32); 1037 1038 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR, 1039 hp->adma_map->dm_segs[0].ds_addr); 1040 } else 1041 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT); 1042 1043 DPRINTF(1,("%s: cmd=%#x mode=%#x blksize=%d blkcount=%d\n", 1044 DEVNAME(hp->sc), command, mode, blksize, blkcount)); 1045 1046 /* 1047 * Start a CPU data transfer. Writing to the high order byte 1048 * of the SDHC_COMMAND register triggers the SD command. (1.5) 1049 */ 1050 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 1051 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 1052 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 1053 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1054 HWRITE2(hp, SDHC_COMMAND, command); 1055 1056 splx(s); 1057 return 0; 1058 } 1059 1060 void 1061 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 1062 { 1063 struct sdhc_softc *sc = hp->sc; 1064 u_char *datap = cmd->c_data; 1065 int i, datalen; 1066 int mask; 1067 int error; 1068 1069 if (cmd->c_dmamap) { 1070 int status; 1071 1072 error = 0; 1073 for (;;) { 1074 status = sdhc_wait_intr(hp, 1075 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 1076 SDHC_DMA_TIMEOUT); 1077 if (status & SDHC_TRANSFER_COMPLETE) 1078 break; 1079 if (!status) { 1080 error = ETIMEDOUT; 1081 break; 1082 } 1083 } 1084 1085 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE, 1086 BUS_DMASYNC_POSTWRITE); 1087 goto done; 1088 } 1089 1090 mask = ISSET(cmd->c_flags, SCF_CMD_READ) ? 1091 SDHC_BUFFER_READ_ENABLE : SDHC_BUFFER_WRITE_ENABLE; 1092 error = 0; 1093 datalen = cmd->c_datalen; 1094 1095 DPRINTF(1,("%s: resp=%#x datalen=%d\n", DEVNAME(hp->sc), 1096 MMC_R1(cmd->c_resp), datalen)); 1097 1098 #ifdef SDHC_DEBUG 1099 /* XXX I forgot why I wanted to know when this happens :-( */ 1100 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 1101 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) 1102 printf("%s: CMD52/53 error response flags %#x\n", 1103 DEVNAME(hp->sc), MMC_R1(cmd->c_resp) & 0xff00); 1104 #endif 1105 1106 while (datalen > 0) { 1107 if (!sdhc_wait_intr(hp, SDHC_BUFFER_READ_READY| 1108 SDHC_BUFFER_WRITE_READY, SDHC_BUFFER_TIMEOUT)) { 1109 error = ETIMEDOUT; 1110 break; 1111 } 1112 1113 if ((error = sdhc_wait_state(hp, mask, mask)) != 0) 1114 break; 1115 1116 i = MIN(datalen, cmd->c_blklen); 1117 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1118 sdhc_read_data(hp, datap, i); 1119 else 1120 sdhc_write_data(hp, datap, i); 1121 1122 datap += i; 1123 datalen -= i; 1124 } 1125 1126 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1127 SDHC_TRANSFER_TIMEOUT)) 1128 error = ETIMEDOUT; 1129 1130 done: 1131 if (error != 0) 1132 cmd->c_error = error; 1133 SET(cmd->c_flags, SCF_ITSDONE); 1134 1135 DPRINTF(1,("%s: data transfer done (error=%d)\n", 1136 DEVNAME(hp->sc), cmd->c_error)); 1137 } 1138 1139 void 1140 sdhc_read_data(struct sdhc_host *hp, u_char *datap, int datalen) 1141 { 1142 while (datalen > 3) { 1143 *(u_int32_t *)datap = HREAD4(hp, SDHC_DATA); 1144 datap += 4; 1145 datalen -= 4; 1146 } 1147 if (datalen > 0) { 1148 u_int32_t rv = HREAD4(hp, SDHC_DATA); 1149 do { 1150 *datap++ = rv & 0xff; 1151 rv = rv >> 8; 1152 } while (--datalen > 0); 1153 } 1154 } 1155 1156 void 1157 sdhc_write_data(struct sdhc_host *hp, u_char *datap, int datalen) 1158 { 1159 while (datalen > 3) { 1160 DPRINTF(3,("%08x\n", *(u_int32_t *)datap)); 1161 HWRITE4(hp, SDHC_DATA, *((u_int32_t *)datap)); 1162 datap += 4; 1163 datalen -= 4; 1164 } 1165 if (datalen > 0) { 1166 u_int32_t rv = *datap++; 1167 if (datalen > 1) 1168 rv |= *datap++ << 8; 1169 if (datalen > 2) 1170 rv |= *datap++ << 16; 1171 DPRINTF(3,("rv %08x\n", rv)); 1172 HWRITE4(hp, SDHC_DATA, rv); 1173 } 1174 } 1175 1176 /* Prepare for another command. */ 1177 int 1178 sdhc_soft_reset(struct sdhc_host *hp, int mask) 1179 { 1180 int timo; 1181 1182 DPRINTF(1,("%s: software reset reg=%#x\n", DEVNAME(hp->sc), mask)); 1183 1184 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1185 for (timo = 10; timo > 0; timo--) { 1186 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1187 break; 1188 sdmmc_delay(10000); 1189 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1190 } 1191 if (timo == 0) { 1192 DPRINTF(1,("%s: timeout reg=%#x\n", DEVNAME(hp->sc), 1193 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1194 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1195 return (ETIMEDOUT); 1196 } 1197 1198 return (0); 1199 } 1200 1201 int 1202 sdhc_wait_intr_cold(struct sdhc_host *hp, int mask, int secs) 1203 { 1204 int status, usecs; 1205 1206 mask |= SDHC_ERROR_INTERRUPT; 1207 usecs = secs * 1000000; 1208 status = hp->intr_status; 1209 while ((status & mask) == 0) { 1210 1211 status = HREAD2(hp, SDHC_NINTR_STATUS); 1212 if (ISSET(status, SDHC_NINTR_STATUS_MASK)) { 1213 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1214 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1215 uint16_t error; 1216 error = HREAD2(hp, SDHC_EINTR_STATUS); 1217 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1218 hp->intr_status |= status; 1219 1220 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1221 SDHC_DATA_TIMEOUT_ERROR)) 1222 break; 1223 } 1224 1225 if (ISSET(status, SDHC_BUFFER_READ_READY | 1226 SDHC_BUFFER_WRITE_READY | SDHC_COMMAND_COMPLETE | 1227 SDHC_TRANSFER_COMPLETE)) { 1228 hp->intr_status |= status; 1229 break; 1230 } 1231 1232 if (ISSET(status, SDHC_CARD_INTERRUPT)) { 1233 HSET2(hp, SDHC_NINTR_STATUS_EN, 1234 SDHC_CARD_INTERRUPT); 1235 } 1236 1237 continue; 1238 } 1239 1240 delay(1); 1241 if (usecs-- == 0) { 1242 status |= SDHC_ERROR_INTERRUPT; 1243 break; 1244 } 1245 } 1246 1247 hp->intr_status &= ~(status & mask); 1248 return (status & mask); 1249 } 1250 1251 int 1252 sdhc_wait_intr(struct sdhc_host *hp, int mask, int secs) 1253 { 1254 int status; 1255 int s; 1256 1257 if (cold) 1258 return (sdhc_wait_intr_cold(hp, mask, secs)); 1259 1260 mask |= SDHC_ERROR_INTERRUPT; 1261 1262 s = splsdmmc(); 1263 status = hp->intr_status & mask; 1264 while (status == 0) { 1265 if (tsleep_nsec(&hp->intr_status, PWAIT, "hcintr", 1266 SEC_TO_NSEC(secs)) == EWOULDBLOCK) { 1267 status |= SDHC_ERROR_INTERRUPT; 1268 break; 1269 } 1270 status = hp->intr_status & mask; 1271 } 1272 hp->intr_status &= ~status; 1273 1274 DPRINTF(2,("%s: intr status %#x error %#x\n", DEVNAME(hp->sc), status, 1275 hp->intr_error_status)); 1276 1277 /* Command timeout has higher priority than command complete. */ 1278 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1279 hp->intr_error_status = 0; 1280 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1281 status = 0; 1282 } 1283 1284 splx(s); 1285 return status; 1286 } 1287 1288 /* 1289 * Established by attachment driver at interrupt priority IPL_SDMMC. 1290 */ 1291 int 1292 sdhc_intr(void *arg) 1293 { 1294 struct sdhc_softc *sc = arg; 1295 int host; 1296 int done = 0; 1297 1298 /* We got an interrupt, but we don't know from which slot. */ 1299 for (host = 0; host < sc->sc_nhosts; host++) { 1300 struct sdhc_host *hp = sc->sc_host[host]; 1301 u_int16_t status; 1302 1303 if (hp == NULL) 1304 continue; 1305 1306 /* Find out which interrupts are pending. */ 1307 status = HREAD2(hp, SDHC_NINTR_STATUS); 1308 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1309 continue; /* no interrupt for us */ 1310 1311 /* Acknowledge the interrupts we are about to handle. */ 1312 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1313 DPRINTF(2,("%s: interrupt status=%b\n", DEVNAME(hp->sc), 1314 status, SDHC_NINTR_STATUS_BITS)); 1315 1316 /* Claim this interrupt. */ 1317 done = 1; 1318 1319 /* 1320 * Service error interrupts. 1321 */ 1322 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1323 u_int16_t error; 1324 1325 /* Acknowledge error interrupts. */ 1326 error = HREAD2(hp, SDHC_EINTR_STATUS); 1327 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1328 DPRINTF(2,("%s: error interrupt, status=%b\n", 1329 DEVNAME(hp->sc), error, SDHC_EINTR_STATUS_BITS)); 1330 1331 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1332 SDHC_DATA_TIMEOUT_ERROR)) { 1333 hp->intr_error_status |= error; 1334 hp->intr_status |= status; 1335 wakeup(&hp->intr_status); 1336 } 1337 } 1338 1339 /* 1340 * Wake up the sdmmc event thread to scan for cards. 1341 */ 1342 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) 1343 sdmmc_needs_discover(hp->sdmmc); 1344 1345 /* 1346 * Wake up the blocking process to service command 1347 * related interrupt(s). 1348 */ 1349 if (ISSET(status, SDHC_BUFFER_READ_READY| 1350 SDHC_BUFFER_WRITE_READY|SDHC_COMMAND_COMPLETE| 1351 SDHC_TRANSFER_COMPLETE)) { 1352 hp->intr_status |= status; 1353 wakeup(&hp->intr_status); 1354 } 1355 1356 /* 1357 * Service SD card interrupts. 1358 */ 1359 if (ISSET(status, SDHC_CARD_INTERRUPT)) { 1360 DPRINTF(0,("%s: card interrupt\n", DEVNAME(hp->sc))); 1361 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1362 sdmmc_card_intr(hp->sdmmc); 1363 } 1364 } 1365 return done; 1366 } 1367 1368 void 1369 sdhc_needs_discover(struct sdhc_softc *sc) 1370 { 1371 int host; 1372 1373 for (host = 0; host < sc->sc_nhosts; host++) 1374 sdmmc_needs_discover(sc->sc_host[host]->sdmmc); 1375 } 1376 1377 #ifdef SDHC_DEBUG 1378 void 1379 sdhc_dump_regs(struct sdhc_host *hp) 1380 { 1381 printf("0x%02x PRESENT_STATE: %b\n", SDHC_PRESENT_STATE, 1382 HREAD4(hp, SDHC_PRESENT_STATE), SDHC_PRESENT_STATE_BITS); 1383 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 1384 HREAD1(hp, SDHC_POWER_CTL)); 1385 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 1386 HREAD2(hp, SDHC_NINTR_STATUS)); 1387 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 1388 HREAD2(hp, SDHC_EINTR_STATUS)); 1389 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 1390 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 1391 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 1392 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 1393 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 1394 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 1395 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 1396 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 1397 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 1398 HREAD4(hp, SDHC_CAPABILITIES)); 1399 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 1400 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 1401 } 1402 #endif 1403 1404 int 1405 sdhc_hibernate_init(sdmmc_chipset_handle_t sch, void *fake_softc) 1406 { 1407 struct sdhc_host *hp, *fhp; 1408 fhp = fake_softc; 1409 hp = sch; 1410 *fhp = *hp; 1411 1412 return (0); 1413 } 1414