1 /* $OpenBSD: sdhc.c,v 1.38 2014/07/12 18:48:52 tedu Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * SD Host Controller driver based on the SD Host Controller Standard 21 * Simplified Specification Version 1.00 (www.sdcard.com). 22 */ 23 24 #include <sys/param.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/kthread.h> 28 #include <sys/malloc.h> 29 #include <sys/systm.h> 30 31 #include <dev/sdmmc/sdhcreg.h> 32 #include <dev/sdmmc/sdhcvar.h> 33 #include <dev/sdmmc/sdmmcchip.h> 34 #include <dev/sdmmc/sdmmcreg.h> 35 #include <dev/sdmmc/sdmmcvar.h> 36 37 #define SDHC_COMMAND_TIMEOUT hz 38 #define SDHC_BUFFER_TIMEOUT hz 39 #define SDHC_TRANSFER_TIMEOUT hz 40 41 struct sdhc_host { 42 struct sdhc_softc *sc; /* host controller device */ 43 struct device *sdmmc; /* generic SD/MMC device */ 44 bus_space_tag_t iot; /* host register set tag */ 45 bus_space_handle_t ioh; /* host register set handle */ 46 u_int clkbase; /* base clock frequency in KHz */ 47 int maxblklen; /* maximum block length */ 48 int flags; /* flags for this host */ 49 u_int32_t ocr; /* OCR value from capabilities */ 50 u_int8_t regs[14]; /* host controller state */ 51 u_int16_t intr_status; /* soft interrupt status */ 52 u_int16_t intr_error_status; /* soft error status */ 53 }; 54 55 /* flag values */ 56 #define SHF_USE_DMA 0x0001 57 58 #define HREAD1(hp, reg) \ 59 (bus_space_read_1((hp)->iot, (hp)->ioh, (reg))) 60 #define HREAD2(hp, reg) \ 61 (bus_space_read_2((hp)->iot, (hp)->ioh, (reg))) 62 #define HREAD4(hp, reg) \ 63 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 64 #define HWRITE1(hp, reg, val) \ 65 bus_space_write_1((hp)->iot, (hp)->ioh, (reg), (val)) 66 #define HWRITE2(hp, reg, val) \ 67 bus_space_write_2((hp)->iot, (hp)->ioh, (reg), (val)) 68 #define HWRITE4(hp, reg, val) \ 69 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 70 #define HCLR1(hp, reg, bits) \ 71 HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)) 72 #define HCLR2(hp, reg, bits) \ 73 HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)) 74 #define HSET1(hp, reg, bits) \ 75 HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)) 76 #define HSET2(hp, reg, bits) \ 77 HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)) 78 79 int sdhc_host_reset(sdmmc_chipset_handle_t); 80 u_int32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 81 int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 82 int sdhc_card_detect(sdmmc_chipset_handle_t); 83 int sdhc_bus_power(sdmmc_chipset_handle_t, u_int32_t); 84 int sdhc_bus_clock(sdmmc_chipset_handle_t, int); 85 void sdhc_card_intr_mask(sdmmc_chipset_handle_t, int); 86 void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 87 void sdhc_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *); 88 int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 89 int sdhc_wait_state(struct sdhc_host *, u_int32_t, u_int32_t); 90 int sdhc_soft_reset(struct sdhc_host *, int); 91 int sdhc_wait_intr(struct sdhc_host *, int, int); 92 void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 93 void sdhc_read_data(struct sdhc_host *, u_char *, int); 94 void sdhc_write_data(struct sdhc_host *, u_char *, int); 95 96 #ifdef SDHC_DEBUG 97 int sdhcdebug = 0; 98 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 99 void sdhc_dump_regs(struct sdhc_host *); 100 #else 101 #define DPRINTF(n,s) do {} while(0) 102 #endif 103 104 struct sdmmc_chip_functions sdhc_functions = { 105 /* host controller reset */ 106 sdhc_host_reset, 107 /* host controller capabilities */ 108 sdhc_host_ocr, 109 sdhc_host_maxblklen, 110 /* card detection */ 111 sdhc_card_detect, 112 /* bus power and clock frequency */ 113 sdhc_bus_power, 114 sdhc_bus_clock, 115 /* command execution */ 116 sdhc_exec_command, 117 /* card interrupt */ 118 sdhc_card_intr_mask, 119 sdhc_card_intr_ack 120 }; 121 122 struct cfdriver sdhc_cd = { 123 NULL, "sdhc", DV_DULL 124 }; 125 126 /* 127 * Called by attachment driver. For each SD card slot there is one SD 128 * host controller standard register set. (1.3) 129 */ 130 int 131 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 132 bus_space_handle_t ioh, bus_size_t iosize, int usedma, u_int32_t caps) 133 { 134 struct sdmmcbus_attach_args saa; 135 struct sdhc_host *hp; 136 int error = 1; 137 #ifdef SDHC_DEBUG 138 u_int16_t version; 139 140 version = bus_space_read_2(iot, ioh, SDHC_HOST_CTL_VERSION); 141 printf("%s: SD Host Specification/Vendor Version ", 142 sc->sc_dev.dv_xname); 143 switch(SDHC_SPEC_VERSION(version)) { 144 case 0x00: 145 printf("1.0/%u\n", SDHC_VENDOR_VERSION(version)); 146 break; 147 default: 148 printf(">1.0/%u\n", SDHC_VENDOR_VERSION(version)); 149 break; 150 } 151 #endif 152 153 /* Allocate one more host structure. */ 154 sc->sc_nhosts++; 155 hp = malloc(sizeof(*hp), M_DEVBUF, M_WAITOK | M_ZERO); 156 sc->sc_host[sc->sc_nhosts - 1] = hp; 157 158 /* Fill in the new host structure. */ 159 hp->sc = sc; 160 hp->iot = iot; 161 hp->ioh = ioh; 162 163 /* 164 * Reset the host controller and enable interrupts. 165 */ 166 (void)sdhc_host_reset(hp); 167 168 /* Determine host capabilities. */ 169 if (caps == 0) 170 caps = HREAD4(hp, SDHC_CAPABILITIES); 171 172 /* Use DMA if the host system and the controller support it. */ 173 if (usedma && ISSET(caps, SDHC_DMA_SUPPORT)) 174 SET(hp->flags, SHF_USE_DMA); 175 176 /* 177 * Determine the base clock frequency. (2.2.24) 178 */ 179 if (SDHC_BASE_FREQ_KHZ(caps) != 0) 180 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 181 if (hp->clkbase == 0) { 182 /* The attachment driver must tell us. */ 183 printf("%s: base clock frequency unknown\n", 184 sc->sc_dev.dv_xname); 185 goto err; 186 } else if (hp->clkbase < 10000 || hp->clkbase > 63000) { 187 /* SDHC 1.0 supports only 10-63 MHz. */ 188 printf("%s: base clock frequency out of range: %u MHz\n", 189 sc->sc_dev.dv_xname, hp->clkbase / 1000); 190 goto err; 191 } 192 193 /* 194 * XXX Set the data timeout counter value according to 195 * capabilities. (2.2.15) 196 */ 197 198 /* 199 * Determine SD bus voltage levels supported by the controller. 200 */ 201 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)) 202 SET(hp->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V); 203 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) 204 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 205 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) 206 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 207 208 /* 209 * Determine the maximum block length supported by the host 210 * controller. (2.2.24) 211 */ 212 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 213 case SDHC_MAX_BLK_LEN_512: 214 hp->maxblklen = 512; 215 break; 216 case SDHC_MAX_BLK_LEN_1024: 217 hp->maxblklen = 1024; 218 break; 219 case SDHC_MAX_BLK_LEN_2048: 220 hp->maxblklen = 2048; 221 break; 222 default: 223 hp->maxblklen = 1; 224 break; 225 } 226 227 /* 228 * Attach the generic SD/MMC bus driver. (The bus driver must 229 * not invoke any chipset functions before it is attached.) 230 */ 231 bzero(&saa, sizeof(saa)); 232 saa.saa_busname = "sdmmc"; 233 saa.sct = &sdhc_functions; 234 saa.sch = hp; 235 236 hp->sdmmc = config_found(&sc->sc_dev, &saa, NULL); 237 if (hp->sdmmc == NULL) { 238 error = 0; 239 goto err; 240 } 241 242 return 0; 243 244 err: 245 free(hp, M_DEVBUF, 0); 246 sc->sc_host[sc->sc_nhosts - 1] = NULL; 247 sc->sc_nhosts--; 248 return (error); 249 } 250 251 int 252 sdhc_activate(struct device *self, int act) 253 { 254 struct sdhc_softc *sc = (struct sdhc_softc *)self; 255 struct sdhc_host *hp; 256 int n, i, rv = 0; 257 258 switch (act) { 259 case DVACT_SUSPEND: 260 rv = config_activate_children(self, act); 261 262 /* Save the host controller state. */ 263 for (n = 0; n < sc->sc_nhosts; n++) { 264 hp = sc->sc_host[n]; 265 for (i = 0; i < sizeof hp->regs; i++) 266 hp->regs[i] = HREAD1(hp, i); 267 } 268 break; 269 case DVACT_RESUME: 270 /* Restore the host controller state. */ 271 for (n = 0; n < sc->sc_nhosts; n++) { 272 hp = sc->sc_host[n]; 273 (void)sdhc_host_reset(hp); 274 for (i = 0; i < sizeof hp->regs; i++) 275 HWRITE1(hp, i, hp->regs[i]); 276 } 277 rv = config_activate_children(self, act); 278 break; 279 case DVACT_POWERDOWN: 280 rv = config_activate_children(self, act); 281 sdhc_shutdown(self); 282 break; 283 default: 284 rv = config_activate_children(self, act); 285 break; 286 } 287 return (rv); 288 } 289 290 /* 291 * Shutdown hook established by or called from attachment driver. 292 */ 293 void 294 sdhc_shutdown(void *arg) 295 { 296 struct sdhc_softc *sc = arg; 297 struct sdhc_host *hp; 298 int i; 299 300 /* XXX chip locks up if we don't disable it before reboot. */ 301 for (i = 0; i < sc->sc_nhosts; i++) { 302 hp = sc->sc_host[i]; 303 (void)sdhc_host_reset(hp); 304 } 305 } 306 307 /* 308 * Reset the host controller. Called during initialization, when 309 * cards are removed, upon resume, and during error recovery. 310 */ 311 int 312 sdhc_host_reset(sdmmc_chipset_handle_t sch) 313 { 314 struct sdhc_host *hp = sch; 315 u_int16_t imask; 316 int error; 317 int s; 318 319 s = splsdmmc(); 320 321 /* Disable all interrupts. */ 322 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 323 324 /* 325 * Reset the entire host controller and wait up to 100ms for 326 * the controller to clear the reset bit. 327 */ 328 if ((error = sdhc_soft_reset(hp, SDHC_RESET_ALL)) != 0) { 329 splx(s); 330 return (error); 331 } 332 333 /* Set data timeout counter value to max for now. */ 334 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 335 336 /* Enable interrupts. */ 337 imask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 338 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 339 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 340 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 341 342 HWRITE2(hp, SDHC_NINTR_STATUS_EN, imask); 343 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 344 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, imask); 345 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 346 347 splx(s); 348 return 0; 349 } 350 351 u_int32_t 352 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 353 { 354 struct sdhc_host *hp = sch; 355 return hp->ocr; 356 } 357 358 int 359 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 360 { 361 struct sdhc_host *hp = sch; 362 return hp->maxblklen; 363 } 364 365 /* 366 * Return non-zero if the card is currently inserted. 367 */ 368 int 369 sdhc_card_detect(sdmmc_chipset_handle_t sch) 370 { 371 struct sdhc_host *hp = sch; 372 return ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED) ? 373 1 : 0; 374 } 375 376 /* 377 * Set or change SD bus voltage and enable or disable SD bus power. 378 * Return zero on success. 379 */ 380 int 381 sdhc_bus_power(sdmmc_chipset_handle_t sch, u_int32_t ocr) 382 { 383 struct sdhc_host *hp = sch; 384 u_int8_t vdd; 385 int s; 386 387 s = splsdmmc(); 388 389 /* 390 * Disable bus power before voltage change. 391 */ 392 if (!(hp->sc->sc_flags & SDHC_F_NOPWR0)) 393 HWRITE1(hp, SDHC_POWER_CTL, 0); 394 395 /* If power is disabled, reset the host and return now. */ 396 if (ocr == 0) { 397 splx(s); 398 (void)sdhc_host_reset(hp); 399 return 0; 400 } 401 402 /* 403 * Select the maximum voltage according to capabilities. 404 */ 405 ocr &= hp->ocr; 406 if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) 407 vdd = SDHC_VOLTAGE_3_3V; 408 else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) 409 vdd = SDHC_VOLTAGE_3_0V; 410 else if (ISSET(ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V)) 411 vdd = SDHC_VOLTAGE_1_8V; 412 else { 413 /* Unsupported voltage level requested. */ 414 splx(s); 415 return EINVAL; 416 } 417 418 /* 419 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 420 * voltage ramp until power rises. 421 */ 422 HWRITE1(hp, SDHC_POWER_CTL, (vdd << SDHC_VOLTAGE_SHIFT) | 423 SDHC_BUS_POWER); 424 sdmmc_delay(10000); 425 426 /* 427 * The host system may not power the bus due to battery low, 428 * etc. In that case, the host controller should clear the 429 * bus power bit. 430 */ 431 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 432 splx(s); 433 return ENXIO; 434 } 435 436 splx(s); 437 return 0; 438 } 439 440 /* 441 * Return the smallest possible base clock frequency divisor value 442 * for the CLOCK_CTL register to produce `freq' (KHz). 443 */ 444 static int 445 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq) 446 { 447 int div; 448 449 for (div = 1; div <= 256; div *= 2) 450 if ((hp->clkbase / div) <= freq) 451 return (div / 2); 452 /* No divisor found. */ 453 return -1; 454 } 455 456 /* 457 * Set or change SDCLK frequency or disable the SD clock. 458 * Return zero on success. 459 */ 460 int 461 sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 462 { 463 struct sdhc_host *hp = sch; 464 int s; 465 int div; 466 int timo; 467 int error = 0; 468 469 s = splsdmmc(); 470 471 #ifdef DIAGNOSTIC 472 /* Must not stop the clock if commands are in progress. */ 473 if (ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK) && 474 sdhc_card_detect(hp)) 475 printf("sdhc_sdclk_frequency_select: command in progress\n"); 476 #endif 477 478 /* 479 * Stop SD clock before changing the frequency. 480 */ 481 HWRITE2(hp, SDHC_CLOCK_CTL, 0); 482 if (freq == SDMMC_SDCLK_OFF) 483 goto ret; 484 485 /* 486 * Set the minimum base clock frequency divisor. 487 */ 488 if ((div = sdhc_clock_divisor(hp, freq)) < 0) { 489 /* Invalid base clock frequency or `freq' value. */ 490 error = EINVAL; 491 goto ret; 492 } 493 HWRITE2(hp, SDHC_CLOCK_CTL, div << SDHC_SDCLK_DIV_SHIFT); 494 495 /* 496 * Start internal clock. Wait 10ms for stabilization. 497 */ 498 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 499 for (timo = 1000; timo > 0; timo--) { 500 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), SDHC_INTCLK_STABLE)) 501 break; 502 sdmmc_delay(10); 503 } 504 if (timo == 0) { 505 error = ETIMEDOUT; 506 goto ret; 507 } 508 509 /* 510 * Enable SD clock. 511 */ 512 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 513 514 ret: 515 splx(s); 516 return error; 517 } 518 519 void 520 sdhc_card_intr_mask(sdmmc_chipset_handle_t sch, int enable) 521 { 522 struct sdhc_host *hp = sch; 523 524 if (enable) { 525 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 526 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 527 } else { 528 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 529 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 530 } 531 } 532 533 void 534 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 535 { 536 struct sdhc_host *hp = sch; 537 538 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 539 } 540 541 int 542 sdhc_wait_state(struct sdhc_host *hp, u_int32_t mask, u_int32_t value) 543 { 544 u_int32_t state; 545 int timeout; 546 547 for (timeout = 10; timeout > 0; timeout--) { 548 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) 549 == value) 550 return 0; 551 sdmmc_delay(10000); 552 } 553 DPRINTF(0,("%s: timeout waiting for %x (state=%b)\n", DEVNAME(hp->sc), 554 value, state, SDHC_PRESENT_STATE_BITS)); 555 return ETIMEDOUT; 556 } 557 558 void 559 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 560 { 561 struct sdhc_host *hp = sch; 562 int error; 563 564 /* 565 * Start the MMC command, or mark `cmd' as failed and return. 566 */ 567 error = sdhc_start_command(hp, cmd); 568 if (error != 0) { 569 cmd->c_error = error; 570 SET(cmd->c_flags, SCF_ITSDONE); 571 return; 572 } 573 574 /* 575 * Wait until the command phase is done, or until the command 576 * is marked done for any other reason. 577 */ 578 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, 579 SDHC_COMMAND_TIMEOUT)) { 580 cmd->c_error = ETIMEDOUT; 581 SET(cmd->c_flags, SCF_ITSDONE); 582 return; 583 } 584 585 /* 586 * The host controller removes bits [0:7] from the response 587 * data (CRC) and we pass the data up unchanged to the bus 588 * driver (without padding). 589 */ 590 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 591 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 592 u_char *p = (u_char *)cmd->c_resp; 593 int i; 594 595 for (i = 0; i < 15; i++) 596 *p++ = HREAD1(hp, SDHC_RESPONSE + i); 597 } else 598 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE); 599 } 600 601 /* 602 * If the command has data to transfer in any direction, 603 * execute the transfer now. 604 */ 605 if (cmd->c_error == 0 && cmd->c_data != NULL) 606 sdhc_transfer_data(hp, cmd); 607 608 /* Turn off the LED. */ 609 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 610 611 DPRINTF(1,("%s: cmd %u done (flags=%#x error=%d)\n", 612 DEVNAME(hp->sc), cmd->c_opcode, cmd->c_flags, cmd->c_error)); 613 SET(cmd->c_flags, SCF_ITSDONE); 614 } 615 616 int 617 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 618 { 619 u_int16_t blksize = 0; 620 u_int16_t blkcount = 0; 621 u_int16_t mode; 622 u_int16_t command; 623 int error; 624 int s; 625 626 DPRINTF(1,("%s: start cmd %u arg=%#x data=%#x dlen=%d flags=%#x " 627 "proc=\"%s\"\n", DEVNAME(hp->sc), cmd->c_opcode, cmd->c_arg, 628 cmd->c_data, cmd->c_datalen, cmd->c_flags, curproc ? 629 curproc->p_comm : "")); 630 631 /* 632 * The maximum block length for commands should be the minimum 633 * of the host buffer size and the card buffer size. (1.7.2) 634 */ 635 636 /* Fragment the data into proper blocks. */ 637 if (cmd->c_datalen > 0) { 638 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 639 blkcount = cmd->c_datalen / blksize; 640 if (cmd->c_datalen % blksize > 0) { 641 /* XXX: Split this command. (1.7.4) */ 642 printf("%s: data not a multiple of %d bytes\n", 643 DEVNAME(hp->sc), blksize); 644 return EINVAL; 645 } 646 } 647 648 /* Check limit imposed by 9-bit block count. (1.7.2) */ 649 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 650 printf("%s: too much data\n", DEVNAME(hp->sc)); 651 return EINVAL; 652 } 653 654 /* Prepare transfer mode register value. (2.2.5) */ 655 mode = 0; 656 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 657 mode |= SDHC_READ_MODE; 658 if (blkcount > 0) { 659 mode |= SDHC_BLOCK_COUNT_ENABLE; 660 if (blkcount > 1) { 661 mode |= SDHC_MULTI_BLOCK_MODE; 662 /* XXX only for memory commands? */ 663 mode |= SDHC_AUTO_CMD12_ENABLE; 664 } 665 } 666 #ifdef notyet 667 if (ISSET(hp->flags, SHF_USE_DMA)) 668 mode |= SDHC_DMA_ENABLE; 669 #endif 670 671 /* 672 * Prepare command register value. (2.2.6) 673 */ 674 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << 675 SDHC_COMMAND_INDEX_SHIFT; 676 677 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 678 command |= SDHC_CRC_CHECK_ENABLE; 679 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 680 command |= SDHC_INDEX_CHECK_ENABLE; 681 if (cmd->c_data != NULL) 682 command |= SDHC_DATA_PRESENT_SELECT; 683 684 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 685 command |= SDHC_NO_RESPONSE; 686 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 687 command |= SDHC_RESP_LEN_136; 688 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 689 command |= SDHC_RESP_LEN_48_CHK_BUSY; 690 else 691 command |= SDHC_RESP_LEN_48; 692 693 /* Wait until command and data inhibit bits are clear. (1.5) */ 694 if ((error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0)) != 0) 695 return error; 696 697 s = splsdmmc(); 698 699 /* Alert the user not to remove the card. */ 700 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 701 702 /* XXX: Set DMA start address if SHF_USE_DMA is set. */ 703 704 DPRINTF(1,("%s: cmd=%#x mode=%#x blksize=%d blkcount=%d\n", 705 DEVNAME(hp->sc), command, mode, blksize, blkcount)); 706 707 /* 708 * Start a CPU data transfer. Writing to the high order byte 709 * of the SDHC_COMMAND register triggers the SD command. (1.5) 710 */ 711 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 712 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 713 if (blkcount > 1) 714 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 715 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 716 HWRITE2(hp, SDHC_COMMAND, command); 717 718 splx(s); 719 return 0; 720 } 721 722 void 723 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 724 { 725 u_char *datap = cmd->c_data; 726 int i, datalen; 727 int mask; 728 int error; 729 730 mask = ISSET(cmd->c_flags, SCF_CMD_READ) ? 731 SDHC_BUFFER_READ_ENABLE : SDHC_BUFFER_WRITE_ENABLE; 732 error = 0; 733 datalen = cmd->c_datalen; 734 735 DPRINTF(1,("%s: resp=%#x datalen=%d\n", DEVNAME(hp->sc), 736 MMC_R1(cmd->c_resp), datalen)); 737 738 #ifdef SDHC_DEBUG 739 /* XXX I forgot why I wanted to know when this happens :-( */ 740 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 741 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) 742 printf("%s: CMD52/53 error response flags %#x\n", 743 DEVNAME(hp->sc), MMC_R1(cmd->c_resp) & 0xff00); 744 #endif 745 746 while (datalen > 0) { 747 if (!sdhc_wait_intr(hp, SDHC_BUFFER_READ_READY| 748 SDHC_BUFFER_WRITE_READY, SDHC_BUFFER_TIMEOUT)) { 749 error = ETIMEDOUT; 750 break; 751 } 752 753 if ((error = sdhc_wait_state(hp, mask, mask)) != 0) 754 break; 755 756 i = MIN(datalen, cmd->c_blklen); 757 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 758 sdhc_read_data(hp, datap, i); 759 else 760 sdhc_write_data(hp, datap, i); 761 762 datap += i; 763 datalen -= i; 764 } 765 766 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 767 SDHC_TRANSFER_TIMEOUT)) 768 error = ETIMEDOUT; 769 770 if (error != 0) 771 cmd->c_error = error; 772 SET(cmd->c_flags, SCF_ITSDONE); 773 774 DPRINTF(1,("%s: data transfer done (error=%d)\n", 775 DEVNAME(hp->sc), cmd->c_error)); 776 } 777 778 void 779 sdhc_read_data(struct sdhc_host *hp, u_char *datap, int datalen) 780 { 781 while (datalen > 3) { 782 *(u_int32_t *)datap = HREAD4(hp, SDHC_DATA); 783 datap += 4; 784 datalen -= 4; 785 } 786 if (datalen > 0) { 787 u_int32_t rv = HREAD4(hp, SDHC_DATA); 788 do { 789 *datap++ = rv & 0xff; 790 rv = rv >> 8; 791 } while (--datalen > 0); 792 } 793 } 794 795 void 796 sdhc_write_data(struct sdhc_host *hp, u_char *datap, int datalen) 797 { 798 while (datalen > 3) { 799 DPRINTF(3,("%08x\n", *(u_int32_t *)datap)); 800 HWRITE4(hp, SDHC_DATA, *((u_int32_t *)datap)); 801 datap += 4; 802 datalen -= 4; 803 } 804 if (datalen > 0) { 805 u_int32_t rv = *datap++; 806 if (datalen > 1) 807 rv |= *datap++ << 8; 808 if (datalen > 2) 809 rv |= *datap++ << 16; 810 DPRINTF(3,("rv %08x\n", rv)); 811 HWRITE4(hp, SDHC_DATA, rv); 812 } 813 } 814 815 /* Prepare for another command. */ 816 int 817 sdhc_soft_reset(struct sdhc_host *hp, int mask) 818 { 819 int timo; 820 821 DPRINTF(1,("%s: software reset reg=%#x\n", DEVNAME(hp->sc), mask)); 822 823 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 824 for (timo = 10; timo > 0; timo--) { 825 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 826 break; 827 sdmmc_delay(10000); 828 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 829 } 830 if (timo == 0) { 831 DPRINTF(1,("%s: timeout reg=%#x\n", DEVNAME(hp->sc), 832 HREAD1(hp, SDHC_SOFTWARE_RESET))); 833 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 834 return (ETIMEDOUT); 835 } 836 837 return (0); 838 } 839 840 int 841 sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo) 842 { 843 int status; 844 int s; 845 846 mask |= SDHC_ERROR_INTERRUPT; 847 848 s = splsdmmc(); 849 status = hp->intr_status & mask; 850 while (status == 0) { 851 if (tsleep(&hp->intr_status, PWAIT, "hcintr", timo) 852 == EWOULDBLOCK) { 853 status |= SDHC_ERROR_INTERRUPT; 854 break; 855 } 856 status = hp->intr_status & mask; 857 } 858 hp->intr_status &= ~status; 859 860 DPRINTF(2,("%s: intr status %#x error %#x\n", DEVNAME(hp->sc), status, 861 hp->intr_error_status)); 862 863 /* Command timeout has higher priority than command complete. */ 864 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 865 hp->intr_error_status = 0; 866 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 867 status = 0; 868 } 869 870 splx(s); 871 return status; 872 } 873 874 /* 875 * Established by attachment driver at interrupt priority IPL_SDMMC. 876 */ 877 int 878 sdhc_intr(void *arg) 879 { 880 struct sdhc_softc *sc = arg; 881 int host; 882 int done = 0; 883 884 /* We got an interrupt, but we don't know from which slot. */ 885 for (host = 0; host < sc->sc_nhosts; host++) { 886 struct sdhc_host *hp = sc->sc_host[host]; 887 u_int16_t status; 888 889 if (hp == NULL) 890 continue; 891 892 /* Find out which interrupts are pending. */ 893 status = HREAD2(hp, SDHC_NINTR_STATUS); 894 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 895 continue; /* no interrupt for us */ 896 897 /* Acknowledge the interrupts we are about to handle. */ 898 HWRITE2(hp, SDHC_NINTR_STATUS, status); 899 DPRINTF(2,("%s: interrupt status=%b\n", DEVNAME(hp->sc), 900 status, SDHC_NINTR_STATUS_BITS)); 901 902 /* Claim this interrupt. */ 903 done = 1; 904 905 /* 906 * Service error interrupts. 907 */ 908 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 909 u_int16_t error; 910 911 /* Acknowledge error interrupts. */ 912 error = HREAD2(hp, SDHC_EINTR_STATUS); 913 HWRITE2(hp, SDHC_EINTR_STATUS, error); 914 DPRINTF(2,("%s: error interrupt, status=%b\n", 915 DEVNAME(hp->sc), error, SDHC_EINTR_STATUS_BITS)); 916 917 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 918 SDHC_DATA_TIMEOUT_ERROR)) { 919 hp->intr_error_status |= error; 920 hp->intr_status |= status; 921 wakeup(&hp->intr_status); 922 } 923 } 924 925 /* 926 * Wake up the sdmmc event thread to scan for cards. 927 */ 928 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) 929 sdmmc_needs_discover(hp->sdmmc); 930 931 /* 932 * Wake up the blocking process to service command 933 * related interrupt(s). 934 */ 935 if (ISSET(status, SDHC_BUFFER_READ_READY| 936 SDHC_BUFFER_WRITE_READY|SDHC_COMMAND_COMPLETE| 937 SDHC_TRANSFER_COMPLETE)) { 938 hp->intr_status |= status; 939 wakeup(&hp->intr_status); 940 } 941 942 /* 943 * Service SD card interrupts. 944 */ 945 if (ISSET(status, SDHC_CARD_INTERRUPT)) { 946 DPRINTF(0,("%s: card interrupt\n", DEVNAME(hp->sc))); 947 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 948 sdmmc_card_intr(hp->sdmmc); 949 } 950 } 951 return done; 952 } 953 954 #ifdef SDHC_DEBUG 955 void 956 sdhc_dump_regs(struct sdhc_host *hp) 957 { 958 printf("0x%02x PRESENT_STATE: %b\n", SDHC_PRESENT_STATE, 959 HREAD4(hp, SDHC_PRESENT_STATE), SDHC_PRESENT_STATE_BITS); 960 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 961 HREAD1(hp, SDHC_POWER_CTL)); 962 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 963 HREAD2(hp, SDHC_NINTR_STATUS)); 964 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 965 HREAD2(hp, SDHC_EINTR_STATUS)); 966 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 967 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 968 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 969 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 970 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 971 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 972 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 973 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 974 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 975 HREAD4(hp, SDHC_CAPABILITIES)); 976 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 977 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 978 } 979 #endif 980