1 /* $OpenBSD: sdhc.c,v 1.68 2020/06/14 18:37:16 patrick Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * SD Host Controller driver based on the SD Host Controller Standard 21 * Simplified Specification Version 1.00 (www.sdcard.com). 22 */ 23 24 #include <sys/param.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/malloc.h> 28 #include <sys/proc.h> 29 #include <sys/systm.h> 30 #include <sys/time.h> 31 32 #include <dev/sdmmc/sdhcreg.h> 33 #include <dev/sdmmc/sdhcvar.h> 34 #include <dev/sdmmc/sdmmcchip.h> 35 #include <dev/sdmmc/sdmmcreg.h> 36 #include <dev/sdmmc/sdmmcvar.h> 37 #include <dev/sdmmc/sdmmc_ioreg.h> 38 39 /* Timeouts in seconds */ 40 #define SDHC_COMMAND_TIMEOUT 1 41 #define SDHC_BUFFER_TIMEOUT 1 42 #define SDHC_TRANSFER_TIMEOUT 1 43 #define SDHC_DMA_TIMEOUT 3 44 45 struct sdhc_host { 46 struct sdhc_softc *sc; /* host controller device */ 47 struct device *sdmmc; /* generic SD/MMC device */ 48 bus_space_tag_t iot; /* host register set tag */ 49 bus_space_handle_t ioh; /* host register set handle */ 50 u_int16_t version; /* specification version */ 51 u_int clkbase; /* base clock frequency in KHz */ 52 int maxblklen; /* maximum block length */ 53 int flags; /* flags for this host */ 54 u_int32_t ocr; /* OCR value from capabilities */ 55 u_int8_t regs[14]; /* host controller state */ 56 u_int16_t intr_status; /* soft interrupt status */ 57 u_int16_t intr_error_status; /* soft error status */ 58 59 bus_dmamap_t adma_map; 60 bus_dma_segment_t adma_segs[1]; 61 caddr_t adma2; 62 63 uint16_t block_size; 64 uint16_t block_count; 65 uint16_t transfer_mode; 66 }; 67 68 /* flag values */ 69 #define SHF_USE_DMA 0x0001 70 #define SHF_USE_DMA64 0x0002 71 #define SHF_USE_32BIT_ACCESS 0x0004 72 73 #define HREAD1(hp, reg) \ 74 (sdhc_read_1((hp), (reg))) 75 #define HREAD2(hp, reg) \ 76 (sdhc_read_2((hp), (reg))) 77 #define HREAD4(hp, reg) \ 78 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 79 #define HWRITE1(hp, reg, val) \ 80 sdhc_write_1((hp), (reg), (val)) 81 #define HWRITE2(hp, reg, val) \ 82 sdhc_write_2((hp), (reg), (val)) 83 #define HWRITE4(hp, reg, val) \ 84 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 85 #define HCLR1(hp, reg, bits) \ 86 HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)) 87 #define HCLR2(hp, reg, bits) \ 88 HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)) 89 #define HSET1(hp, reg, bits) \ 90 HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)) 91 #define HSET2(hp, reg, bits) \ 92 HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)) 93 94 int sdhc_host_reset(sdmmc_chipset_handle_t); 95 u_int32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 96 int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 97 int sdhc_card_detect(sdmmc_chipset_handle_t); 98 int sdhc_bus_power(sdmmc_chipset_handle_t, u_int32_t); 99 int sdhc_bus_clock(sdmmc_chipset_handle_t, int, int); 100 int sdhc_bus_width(sdmmc_chipset_handle_t, int); 101 void sdhc_card_intr_mask(sdmmc_chipset_handle_t, int); 102 void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 103 int sdhc_signal_voltage(sdmmc_chipset_handle_t, int); 104 void sdhc_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *); 105 int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 106 int sdhc_wait_state(struct sdhc_host *, u_int32_t, u_int32_t); 107 int sdhc_soft_reset(struct sdhc_host *, int); 108 int sdhc_wait_intr_cold(struct sdhc_host *, int, int); 109 int sdhc_wait_intr(struct sdhc_host *, int, int); 110 void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 111 void sdhc_read_data(struct sdhc_host *, u_char *, int); 112 void sdhc_write_data(struct sdhc_host *, u_char *, int); 113 int sdhc_hibernate_init(sdmmc_chipset_handle_t, void *); 114 115 #ifdef SDHC_DEBUG 116 int sdhcdebug = 0; 117 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 118 void sdhc_dump_regs(struct sdhc_host *); 119 #else 120 #define DPRINTF(n,s) do {} while(0) 121 #endif 122 123 struct sdmmc_chip_functions sdhc_functions = { 124 /* host controller reset */ 125 sdhc_host_reset, 126 /* host controller capabilities */ 127 sdhc_host_ocr, 128 sdhc_host_maxblklen, 129 /* card detection */ 130 sdhc_card_detect, 131 /* bus power and clock frequency */ 132 sdhc_bus_power, 133 sdhc_bus_clock, 134 sdhc_bus_width, 135 /* command execution */ 136 sdhc_exec_command, 137 /* card interrupt */ 138 sdhc_card_intr_mask, 139 sdhc_card_intr_ack, 140 /* UHS functions */ 141 sdhc_signal_voltage, 142 /* hibernate */ 143 sdhc_hibernate_init, 144 }; 145 146 struct cfdriver sdhc_cd = { 147 NULL, "sdhc", DV_DULL 148 }; 149 150 /* 151 * Some controllers live on a bus that only allows 32-bit 152 * transactions. In that case we use a RMW cycle for 8-bit and 16-bit 153 * register writes. However that doesn't work for the Transfer Mode 154 * register as this register lives in the same 32-bit word as the 155 * Command register and writing the Command register triggers SD 156 * command generation. We avoid this issue by using a shadow variable 157 * for the Transfer Mode register that we write out when we write the 158 * Command register. 159 * 160 * The Arasan controller controller integrated on the Broadcom SoCs 161 * used in the Raspberry Pi has an interesting bug where writing the 162 * same 32-bit register twice doesn't work. This means that we lose 163 * writes to the Block Sine and/or Block Count register. We work 164 * around that issue by using shadow variables as well. 165 */ 166 167 uint8_t 168 sdhc_read_1(struct sdhc_host *hp, bus_size_t offset) 169 { 170 uint32_t reg; 171 172 if (hp->flags & SHF_USE_32BIT_ACCESS) { 173 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~3); 174 return (reg >> ((offset & 3) * 8)) & 0xff; 175 } 176 177 return bus_space_read_1(hp->iot, hp->ioh, offset); 178 } 179 180 uint16_t 181 sdhc_read_2(struct sdhc_host *hp, bus_size_t offset) 182 { 183 uint32_t reg; 184 185 if (hp->flags & SHF_USE_32BIT_ACCESS) { 186 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~2); 187 return (reg >> ((offset & 2) * 8)) & 0xffff; 188 } 189 190 return bus_space_read_2(hp->iot, hp->ioh, offset); 191 } 192 193 void 194 sdhc_write_1(struct sdhc_host *hp, bus_size_t offset, uint8_t value) 195 { 196 uint32_t reg; 197 198 if (hp->flags & SHF_USE_32BIT_ACCESS) { 199 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~3); 200 reg &= ~(0xff << ((offset & 3) * 8)); 201 reg |= (value << ((offset & 3) * 8)); 202 bus_space_write_4(hp->iot, hp->ioh, offset & ~3, reg); 203 return; 204 } 205 206 bus_space_write_1(hp->iot, hp->ioh, offset, value); 207 } 208 209 void 210 sdhc_write_2(struct sdhc_host *hp, bus_size_t offset, uint16_t value) 211 { 212 uint32_t reg; 213 214 if (hp->flags & SHF_USE_32BIT_ACCESS) { 215 switch (offset) { 216 case SDHC_BLOCK_SIZE: 217 hp->block_size = value; 218 return; 219 case SDHC_BLOCK_COUNT: 220 hp->block_count = value; 221 return; 222 case SDHC_TRANSFER_MODE: 223 hp->transfer_mode = value; 224 return; 225 case SDHC_COMMAND: 226 bus_space_write_4(hp->iot, hp->ioh, SDHC_BLOCK_SIZE, 227 (hp->block_count << 16) | hp->block_size); 228 bus_space_write_4(hp->iot, hp->ioh, SDHC_TRANSFER_MODE, 229 (value << 16) | hp->transfer_mode); 230 return; 231 } 232 233 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~2); 234 reg &= ~(0xffff << ((offset & 2) * 8)); 235 reg |= (value << ((offset & 2) * 8)); 236 bus_space_write_4(hp->iot, hp->ioh, offset & ~2, reg); 237 return; 238 } 239 240 bus_space_write_2(hp->iot, hp->ioh, offset, value); 241 } 242 243 /* 244 * Called by attachment driver. For each SD card slot there is one SD 245 * host controller standard register set. (1.3) 246 */ 247 int 248 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 249 bus_space_handle_t ioh, bus_size_t iosize, int usedma, u_int32_t caps) 250 { 251 struct sdmmcbus_attach_args saa; 252 struct sdhc_host *hp; 253 int error = 1; 254 int max_clock; 255 256 /* Allocate one more host structure. */ 257 sc->sc_nhosts++; 258 hp = malloc(sizeof(*hp), M_DEVBUF, M_WAITOK | M_ZERO); 259 sc->sc_host[sc->sc_nhosts - 1] = hp; 260 261 if (ISSET(sc->sc_flags, SDHC_F_32BIT_ACCESS)) 262 SET(hp->flags, SHF_USE_32BIT_ACCESS); 263 264 /* Fill in the new host structure. */ 265 hp->sc = sc; 266 hp->iot = iot; 267 hp->ioh = ioh; 268 269 /* Store specification version. */ 270 hp->version = HREAD2(hp, SDHC_HOST_CTL_VERSION); 271 272 /* 273 * Reset the host controller and enable interrupts. 274 */ 275 (void)sdhc_host_reset(hp); 276 277 /* Determine host capabilities. */ 278 if (caps == 0) 279 caps = HREAD4(hp, SDHC_CAPABILITIES); 280 281 /* Use DMA if the host system and the controller support it. */ 282 if (usedma && ISSET(caps, SDHC_ADMA2_SUPP)) { 283 SET(hp->flags, SHF_USE_DMA); 284 if (ISSET(caps, SDHC_64BIT_DMA_SUPP)) 285 SET(hp->flags, SHF_USE_DMA64); 286 } 287 288 /* 289 * Determine the base clock frequency. (2.2.24) 290 */ 291 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 292 /* SDHC 3.0 supports 10-255 MHz. */ 293 max_clock = 255000; 294 if (SDHC_BASE_FREQ_KHZ_V3(caps) != 0) 295 hp->clkbase = SDHC_BASE_FREQ_KHZ_V3(caps); 296 } else { 297 /* SDHC 1.0/2.0 supports only 10-63 MHz. */ 298 max_clock = 63000; 299 if (SDHC_BASE_FREQ_KHZ(caps) != 0) 300 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 301 } 302 if (hp->clkbase == 0) { 303 /* Make sure we can clock down to 400 kHz. */ 304 max_clock = 400 * SDHC_SDCLK_DIV_MAX_V3; 305 hp->clkbase = sc->sc_clkbase; 306 } 307 if (hp->clkbase == 0) { 308 /* The attachment driver must tell us. */ 309 printf("%s: base clock frequency unknown\n", 310 sc->sc_dev.dv_xname); 311 goto err; 312 } else if (hp->clkbase < 10000 || hp->clkbase > max_clock) { 313 printf("%s: base clock frequency out of range: %u MHz\n", 314 sc->sc_dev.dv_xname, hp->clkbase / 1000); 315 goto err; 316 } 317 318 printf("%s: SDHC %d.0, %d MHz base clock\n", DEVNAME(sc), 319 SDHC_SPEC_VERSION(hp->version) + 1, hp->clkbase / 1000); 320 321 /* 322 * XXX Set the data timeout counter value according to 323 * capabilities. (2.2.15) 324 */ 325 326 /* 327 * Determine SD bus voltage levels supported by the controller. 328 */ 329 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)) 330 SET(hp->ocr, MMC_OCR_1_65V_1_95V); 331 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) 332 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 333 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) 334 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 335 336 /* 337 * Determine the maximum block length supported by the host 338 * controller. (2.2.24) 339 */ 340 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 341 case SDHC_MAX_BLK_LEN_512: 342 hp->maxblklen = 512; 343 break; 344 case SDHC_MAX_BLK_LEN_1024: 345 hp->maxblklen = 1024; 346 break; 347 case SDHC_MAX_BLK_LEN_2048: 348 hp->maxblklen = 2048; 349 break; 350 default: 351 hp->maxblklen = 1; 352 break; 353 } 354 355 if (ISSET(hp->flags, SHF_USE_DMA)) { 356 int rseg; 357 358 /* Allocate ADMA2 descriptor memory */ 359 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 360 PAGE_SIZE, hp->adma_segs, 1, &rseg, 361 BUS_DMA_WAITOK | BUS_DMA_ZERO); 362 if (error) 363 goto adma_done; 364 error = bus_dmamem_map(sc->sc_dmat, hp->adma_segs, rseg, 365 PAGE_SIZE, &hp->adma2, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 366 if (error) { 367 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg); 368 goto adma_done; 369 } 370 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 371 0, BUS_DMA_WAITOK, &hp->adma_map); 372 if (error) { 373 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE); 374 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg); 375 goto adma_done; 376 } 377 error = bus_dmamap_load(sc->sc_dmat, hp->adma_map, 378 hp->adma2, PAGE_SIZE, NULL, 379 BUS_DMA_WAITOK | BUS_DMA_WRITE); 380 if (error) { 381 bus_dmamap_destroy(sc->sc_dmat, hp->adma_map); 382 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE); 383 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg); 384 goto adma_done; 385 } 386 387 adma_done: 388 if (error) { 389 printf("%s: can't allocate DMA descriptor table\n", 390 DEVNAME(hp->sc)); 391 CLR(hp->flags, SHF_USE_DMA); 392 } 393 } 394 395 /* 396 * Attach the generic SD/MMC bus driver. (The bus driver must 397 * not invoke any chipset functions before it is attached.) 398 */ 399 bzero(&saa, sizeof(saa)); 400 saa.saa_busname = "sdmmc"; 401 saa.sct = &sdhc_functions; 402 saa.sch = hp; 403 saa.caps = SMC_CAPS_4BIT_MODE; 404 saa.dmat = sc->sc_dmat; 405 if (ISSET(hp->flags, SHF_USE_DMA)) 406 saa.caps |= SMC_CAPS_DMA; 407 408 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 409 saa.caps |= SMC_CAPS_SD_HIGHSPEED; 410 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 411 saa.caps |= SMC_CAPS_MMC_HIGHSPEED; 412 413 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 414 uint32_t caps2 = HREAD4(hp, SDHC_CAPABILITIES2); 415 416 if (ISSET(caps, SDHC_8BIT_MODE_SUPP)) 417 saa.caps |= SMC_CAPS_8BIT_MODE; 418 419 if (ISSET(caps2, SDHC_DDR50_SUPP)) 420 saa.caps |= SMC_CAPS_MMC_DDR52; 421 } 422 423 if (ISSET(sc->sc_flags, SDHC_F_NODDR50)) 424 saa.caps &= ~SMC_CAPS_MMC_DDR52; 425 426 if (ISSET(sc->sc_flags, SDHC_F_NONREMOVABLE)) 427 saa.caps |= SMC_CAPS_NONREMOVABLE; 428 429 hp->sdmmc = config_found(&sc->sc_dev, &saa, NULL); 430 if (hp->sdmmc == NULL) { 431 error = 0; 432 goto err; 433 } 434 435 return 0; 436 437 err: 438 free(hp, M_DEVBUF, sizeof *hp); 439 sc->sc_host[sc->sc_nhosts - 1] = NULL; 440 sc->sc_nhosts--; 441 return (error); 442 } 443 444 int 445 sdhc_activate(struct device *self, int act) 446 { 447 struct sdhc_softc *sc = (struct sdhc_softc *)self; 448 struct sdhc_host *hp; 449 int n, i, rv = 0; 450 451 switch (act) { 452 case DVACT_SUSPEND: 453 rv = config_activate_children(self, act); 454 455 /* Save the host controller state. */ 456 for (n = 0; n < sc->sc_nhosts; n++) { 457 hp = sc->sc_host[n]; 458 for (i = 0; i < sizeof hp->regs; i++) 459 hp->regs[i] = HREAD1(hp, i); 460 } 461 break; 462 case DVACT_RESUME: 463 /* Restore the host controller state. */ 464 for (n = 0; n < sc->sc_nhosts; n++) { 465 hp = sc->sc_host[n]; 466 (void)sdhc_host_reset(hp); 467 for (i = 0; i < sizeof hp->regs; i++) 468 HWRITE1(hp, i, hp->regs[i]); 469 } 470 rv = config_activate_children(self, act); 471 break; 472 case DVACT_POWERDOWN: 473 rv = config_activate_children(self, act); 474 sdhc_shutdown(self); 475 break; 476 default: 477 rv = config_activate_children(self, act); 478 break; 479 } 480 return (rv); 481 } 482 483 /* 484 * Shutdown hook established by or called from attachment driver. 485 */ 486 void 487 sdhc_shutdown(void *arg) 488 { 489 struct sdhc_softc *sc = arg; 490 struct sdhc_host *hp; 491 int i; 492 493 /* XXX chip locks up if we don't disable it before reboot. */ 494 for (i = 0; i < sc->sc_nhosts; i++) { 495 hp = sc->sc_host[i]; 496 (void)sdhc_host_reset(hp); 497 } 498 } 499 500 /* 501 * Reset the host controller. Called during initialization, when 502 * cards are removed, upon resume, and during error recovery. 503 */ 504 int 505 sdhc_host_reset(sdmmc_chipset_handle_t sch) 506 { 507 struct sdhc_host *hp = sch; 508 u_int16_t imask; 509 int error; 510 int s; 511 512 s = splsdmmc(); 513 514 /* Disable all interrupts. */ 515 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 516 517 /* 518 * Reset the entire host controller and wait up to 100ms for 519 * the controller to clear the reset bit. 520 */ 521 if ((error = sdhc_soft_reset(hp, SDHC_RESET_ALL)) != 0) { 522 splx(s); 523 return (error); 524 } 525 526 /* Set data timeout counter value to max for now. */ 527 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 528 529 /* Enable interrupts. */ 530 imask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 531 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 532 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 533 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 534 535 HWRITE2(hp, SDHC_NINTR_STATUS_EN, imask); 536 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 537 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, imask); 538 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 539 540 splx(s); 541 return 0; 542 } 543 544 u_int32_t 545 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 546 { 547 struct sdhc_host *hp = sch; 548 return hp->ocr; 549 } 550 551 int 552 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 553 { 554 struct sdhc_host *hp = sch; 555 return hp->maxblklen; 556 } 557 558 /* 559 * Return non-zero if the card is currently inserted. 560 */ 561 int 562 sdhc_card_detect(sdmmc_chipset_handle_t sch) 563 { 564 struct sdhc_host *hp = sch; 565 566 if (hp->sc->sc_card_detect) 567 return hp->sc->sc_card_detect(hp->sc); 568 569 return ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED) ? 570 1 : 0; 571 } 572 573 /* 574 * Set or change SD bus voltage and enable or disable SD bus power. 575 * Return zero on success. 576 */ 577 int 578 sdhc_bus_power(sdmmc_chipset_handle_t sch, u_int32_t ocr) 579 { 580 struct sdhc_host *hp = sch; 581 u_int8_t vdd; 582 int s; 583 584 s = splsdmmc(); 585 586 /* 587 * Disable bus power before voltage change. 588 */ 589 if (!(hp->sc->sc_flags & SDHC_F_NOPWR0)) 590 HWRITE1(hp, SDHC_POWER_CTL, 0); 591 592 /* If power is disabled, reset the host and return now. */ 593 if (ocr == 0) { 594 splx(s); 595 (void)sdhc_host_reset(hp); 596 return 0; 597 } 598 599 /* 600 * Select the maximum voltage according to capabilities. 601 */ 602 ocr &= hp->ocr; 603 if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) 604 vdd = SDHC_VOLTAGE_3_3V; 605 else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) 606 vdd = SDHC_VOLTAGE_3_0V; 607 else if (ISSET(ocr, MMC_OCR_1_65V_1_95V)) 608 vdd = SDHC_VOLTAGE_1_8V; 609 else { 610 /* Unsupported voltage level requested. */ 611 splx(s); 612 return EINVAL; 613 } 614 615 /* 616 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 617 * voltage ramp until power rises. 618 */ 619 HWRITE1(hp, SDHC_POWER_CTL, (vdd << SDHC_VOLTAGE_SHIFT) | 620 SDHC_BUS_POWER); 621 sdmmc_delay(10000); 622 623 /* 624 * The host system may not power the bus due to battery low, 625 * etc. In that case, the host controller should clear the 626 * bus power bit. 627 */ 628 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 629 splx(s); 630 return ENXIO; 631 } 632 633 splx(s); 634 return 0; 635 } 636 637 /* 638 * Return the smallest possible base clock frequency divisor value 639 * for the CLOCK_CTL register to produce `freq' (KHz). 640 */ 641 static int 642 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq) 643 { 644 int max_div = SDHC_SDCLK_DIV_MAX; 645 int div; 646 647 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) 648 max_div = SDHC_SDCLK_DIV_MAX_V3; 649 650 for (div = 1; div <= max_div; div *= 2) 651 if ((hp->clkbase / div) <= freq) 652 return (div / 2); 653 /* No divisor found. */ 654 return -1; 655 } 656 657 /* 658 * Set or change SDCLK frequency or disable the SD clock. 659 * Return zero on success. 660 */ 661 int 662 sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing) 663 { 664 struct sdhc_host *hp = sch; 665 int s; 666 int div; 667 int sdclk; 668 int timo; 669 int error = 0; 670 671 s = splsdmmc(); 672 673 if (hp->sc->sc_bus_clock_pre) 674 hp->sc->sc_bus_clock_pre(hp->sc, freq, timing); 675 676 #ifdef DIAGNOSTIC 677 /* Must not stop the clock if commands are in progress. */ 678 if (ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK) && 679 sdhc_card_detect(hp)) 680 printf("sdhc_sdclk_frequency_select: command in progress\n"); 681 #endif 682 683 /* 684 * Stop SD clock before changing the frequency. 685 */ 686 HWRITE2(hp, SDHC_CLOCK_CTL, 0); 687 if (freq == SDMMC_SDCLK_OFF) 688 goto ret; 689 690 if (timing == SDMMC_TIMING_LEGACY) 691 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 692 else 693 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 694 695 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 696 switch (timing) { 697 case SDMMC_TIMING_MMC_DDR52: 698 HCLR2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_MASK); 699 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_DDR50); 700 break; 701 } 702 } 703 704 /* 705 * Set the minimum base clock frequency divisor. 706 */ 707 if ((div = sdhc_clock_divisor(hp, freq)) < 0) { 708 /* Invalid base clock frequency or `freq' value. */ 709 error = EINVAL; 710 goto ret; 711 } 712 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) 713 sdclk = SDHC_SDCLK_DIV_V3(div); 714 else 715 sdclk = SDHC_SDCLK_DIV(div); 716 HWRITE2(hp, SDHC_CLOCK_CTL, sdclk); 717 718 /* 719 * Start internal clock. Wait 10ms for stabilization. 720 */ 721 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 722 for (timo = 1000; timo > 0; timo--) { 723 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), SDHC_INTCLK_STABLE)) 724 break; 725 sdmmc_delay(10); 726 } 727 if (timo == 0) { 728 error = ETIMEDOUT; 729 goto ret; 730 } 731 732 /* 733 * Enable SD clock. 734 */ 735 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 736 737 if (hp->sc->sc_bus_clock_post) 738 hp->sc->sc_bus_clock_post(hp->sc, freq, timing); 739 740 ret: 741 splx(s); 742 return error; 743 } 744 745 int 746 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 747 { 748 struct sdhc_host *hp = (struct sdhc_host *)sch; 749 int reg; 750 int s; 751 752 if (width != 1 && width != 4 && width != 8) 753 return EINVAL; 754 755 s = splsdmmc(); 756 757 reg = HREAD1(hp, SDHC_HOST_CTL); 758 reg &= ~SDHC_4BIT_MODE; 759 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 760 reg &= ~SDHC_8BIT_MODE; 761 } 762 if (width == 4) { 763 reg |= SDHC_4BIT_MODE; 764 } else if (width == 8) { 765 KASSERT(SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3); 766 reg |= SDHC_8BIT_MODE; 767 } 768 HWRITE1(hp, SDHC_HOST_CTL, reg); 769 770 splx(s); 771 772 return 0; 773 } 774 775 void 776 sdhc_card_intr_mask(sdmmc_chipset_handle_t sch, int enable) 777 { 778 struct sdhc_host *hp = sch; 779 780 if (enable) { 781 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 782 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 783 } else { 784 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 785 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 786 } 787 } 788 789 void 790 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 791 { 792 struct sdhc_host *hp = sch; 793 794 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 795 } 796 797 int 798 sdhc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 799 { 800 struct sdhc_host *hp = sch; 801 802 if (hp->sc->sc_signal_voltage) 803 return hp->sc->sc_signal_voltage(hp->sc, signal_voltage); 804 805 if (SDHC_SPEC_VERSION(hp->version) < SDHC_SPEC_V3) 806 return EINVAL; 807 808 switch (signal_voltage) { 809 case SDMMC_SIGNAL_VOLTAGE_180: 810 HSET2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN); 811 break; 812 case SDMMC_SIGNAL_VOLTAGE_330: 813 HCLR2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN); 814 break; 815 default: 816 return EINVAL; 817 } 818 819 /* Regulator output shall be stable within 5 ms. */ 820 sdmmc_delay(5000); 821 822 /* Host controller clears this bit if 1.8V signalling fails. */ 823 if (signal_voltage == SDMMC_SIGNAL_VOLTAGE_180 && 824 !ISSET(HREAD2(hp, SDHC_HOST_CTL2), SDHC_1_8V_SIGNAL_EN)) 825 return EIO; 826 827 return 0; 828 } 829 830 int 831 sdhc_wait_state(struct sdhc_host *hp, u_int32_t mask, u_int32_t value) 832 { 833 u_int32_t state; 834 int timeout; 835 836 for (timeout = 10; timeout > 0; timeout--) { 837 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) 838 == value) 839 return 0; 840 sdmmc_delay(10000); 841 } 842 DPRINTF(0,("%s: timeout waiting for %x (state=%b)\n", DEVNAME(hp->sc), 843 value, state, SDHC_PRESENT_STATE_BITS)); 844 return ETIMEDOUT; 845 } 846 847 void 848 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 849 { 850 struct sdhc_host *hp = sch; 851 int error; 852 853 /* 854 * Start the MMC command, or mark `cmd' as failed and return. 855 */ 856 error = sdhc_start_command(hp, cmd); 857 if (error != 0) { 858 cmd->c_error = error; 859 SET(cmd->c_flags, SCF_ITSDONE); 860 return; 861 } 862 863 /* 864 * Wait until the command phase is done, or until the command 865 * is marked done for any other reason. 866 */ 867 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, 868 SDHC_COMMAND_TIMEOUT)) { 869 cmd->c_error = ETIMEDOUT; 870 SET(cmd->c_flags, SCF_ITSDONE); 871 return; 872 } 873 874 /* 875 * The host controller removes bits [0:7] from the response 876 * data (CRC) and we pass the data up unchanged to the bus 877 * driver (without padding). 878 */ 879 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 880 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 881 u_char *p = (u_char *)cmd->c_resp; 882 int i; 883 884 for (i = 0; i < 15; i++) 885 *p++ = HREAD1(hp, SDHC_RESPONSE + i); 886 } else 887 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE); 888 } 889 890 /* 891 * If the command has data to transfer in any direction, 892 * execute the transfer now. 893 */ 894 if (cmd->c_error == 0 && cmd->c_data != NULL) 895 sdhc_transfer_data(hp, cmd); 896 897 /* Turn off the LED. */ 898 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 899 900 DPRINTF(1,("%s: cmd %u done (flags=%#x error=%d)\n", 901 DEVNAME(hp->sc), cmd->c_opcode, cmd->c_flags, cmd->c_error)); 902 SET(cmd->c_flags, SCF_ITSDONE); 903 } 904 905 int 906 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 907 { 908 struct sdhc_adma2_descriptor32 *desc32 = (void *)hp->adma2; 909 struct sdhc_adma2_descriptor64 *desc64 = (void *)hp->adma2; 910 struct sdhc_softc *sc = hp->sc; 911 u_int16_t blksize = 0; 912 u_int16_t blkcount = 0; 913 u_int16_t mode; 914 u_int16_t command; 915 int error; 916 int seg; 917 int s; 918 919 DPRINTF(1,("%s: start cmd %u arg=%#x data=%p dlen=%d flags=%#x\n", 920 DEVNAME(hp->sc), cmd->c_opcode, cmd->c_arg, cmd->c_data, 921 cmd->c_datalen, cmd->c_flags)); 922 923 /* 924 * The maximum block length for commands should be the minimum 925 * of the host buffer size and the card buffer size. (1.7.2) 926 */ 927 928 /* Fragment the data into proper blocks. */ 929 if (cmd->c_datalen > 0) { 930 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 931 blkcount = cmd->c_datalen / blksize; 932 if (cmd->c_datalen % blksize > 0) { 933 /* XXX: Split this command. (1.7.4) */ 934 printf("%s: data not a multiple of %d bytes\n", 935 DEVNAME(hp->sc), blksize); 936 return EINVAL; 937 } 938 } 939 940 /* Check limit imposed by 9-bit block count. (1.7.2) */ 941 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 942 printf("%s: too much data\n", DEVNAME(hp->sc)); 943 return EINVAL; 944 } 945 946 /* Prepare transfer mode register value. (2.2.5) */ 947 mode = 0; 948 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 949 mode |= SDHC_READ_MODE; 950 if (blkcount > 0) { 951 mode |= SDHC_BLOCK_COUNT_ENABLE; 952 if (blkcount > 1) { 953 mode |= SDHC_MULTI_BLOCK_MODE; 954 if (cmd->c_opcode != SD_IO_RW_EXTENDED) 955 mode |= SDHC_AUTO_CMD12_ENABLE; 956 } 957 } 958 if (cmd->c_dmamap && cmd->c_datalen > 0 && 959 ISSET(hp->flags, SHF_USE_DMA)) 960 mode |= SDHC_DMA_ENABLE; 961 962 /* 963 * Prepare command register value. (2.2.6) 964 */ 965 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << 966 SDHC_COMMAND_INDEX_SHIFT; 967 968 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 969 command |= SDHC_CRC_CHECK_ENABLE; 970 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 971 command |= SDHC_INDEX_CHECK_ENABLE; 972 if (cmd->c_data != NULL) 973 command |= SDHC_DATA_PRESENT_SELECT; 974 975 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 976 command |= SDHC_NO_RESPONSE; 977 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 978 command |= SDHC_RESP_LEN_136; 979 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 980 command |= SDHC_RESP_LEN_48_CHK_BUSY; 981 else 982 command |= SDHC_RESP_LEN_48; 983 984 /* Wait until command and data inhibit bits are clear. (1.5) */ 985 if ((error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0)) != 0) 986 return error; 987 988 s = splsdmmc(); 989 990 /* Alert the user not to remove the card. */ 991 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 992 993 /* Set DMA start address if SHF_USE_DMA is set. */ 994 if (cmd->c_dmamap && ISSET(hp->flags, SHF_USE_DMA)) { 995 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 996 bus_addr_t paddr = 997 cmd->c_dmamap->dm_segs[seg].ds_addr; 998 uint16_t len = 999 cmd->c_dmamap->dm_segs[seg].ds_len == 65536 ? 1000 0 : cmd->c_dmamap->dm_segs[seg].ds_len; 1001 uint16_t attr; 1002 1003 attr = SDHC_ADMA2_VALID | SDHC_ADMA2_ACT_TRANS; 1004 if (seg == cmd->c_dmamap->dm_nsegs - 1) 1005 attr |= SDHC_ADMA2_END; 1006 1007 if (ISSET(hp->flags, SHF_USE_DMA64)) { 1008 desc64[seg].attribute = htole16(attr); 1009 desc64[seg].length = htole16(len); 1010 desc64[seg].address_lo = 1011 htole32((uint64_t)paddr & 0xffffffff); 1012 desc64[seg].address_hi = 1013 htole32((uint64_t)paddr >> 32); 1014 } else { 1015 desc32[seg].attribute = htole16(attr); 1016 desc32[seg].length = htole16(len); 1017 desc32[seg].address = htole32(paddr); 1018 } 1019 } 1020 1021 if (ISSET(hp->flags, SHF_USE_DMA64)) 1022 desc64[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 1023 else 1024 desc32[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 1025 1026 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE, 1027 BUS_DMASYNC_PREWRITE); 1028 1029 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT); 1030 if (ISSET(hp->flags, SHF_USE_DMA64)) 1031 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA64); 1032 else 1033 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA32); 1034 1035 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR, 1036 hp->adma_map->dm_segs[0].ds_addr); 1037 } else 1038 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT); 1039 1040 DPRINTF(1,("%s: cmd=%#x mode=%#x blksize=%d blkcount=%d\n", 1041 DEVNAME(hp->sc), command, mode, blksize, blkcount)); 1042 1043 /* 1044 * Start a CPU data transfer. Writing to the high order byte 1045 * of the SDHC_COMMAND register triggers the SD command. (1.5) 1046 */ 1047 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 1048 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 1049 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 1050 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1051 HWRITE2(hp, SDHC_COMMAND, command); 1052 1053 splx(s); 1054 return 0; 1055 } 1056 1057 void 1058 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 1059 { 1060 struct sdhc_softc *sc = hp->sc; 1061 u_char *datap = cmd->c_data; 1062 int i, datalen; 1063 int mask; 1064 int error; 1065 1066 if (cmd->c_dmamap) { 1067 int status; 1068 1069 error = 0; 1070 for (;;) { 1071 status = sdhc_wait_intr(hp, 1072 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 1073 SDHC_DMA_TIMEOUT); 1074 if (status & SDHC_TRANSFER_COMPLETE) 1075 break; 1076 if (!status) { 1077 error = ETIMEDOUT; 1078 break; 1079 } 1080 } 1081 1082 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE, 1083 BUS_DMASYNC_POSTWRITE); 1084 goto done; 1085 } 1086 1087 mask = ISSET(cmd->c_flags, SCF_CMD_READ) ? 1088 SDHC_BUFFER_READ_ENABLE : SDHC_BUFFER_WRITE_ENABLE; 1089 error = 0; 1090 datalen = cmd->c_datalen; 1091 1092 DPRINTF(1,("%s: resp=%#x datalen=%d\n", DEVNAME(hp->sc), 1093 MMC_R1(cmd->c_resp), datalen)); 1094 1095 #ifdef SDHC_DEBUG 1096 /* XXX I forgot why I wanted to know when this happens :-( */ 1097 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 1098 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) 1099 printf("%s: CMD52/53 error response flags %#x\n", 1100 DEVNAME(hp->sc), MMC_R1(cmd->c_resp) & 0xff00); 1101 #endif 1102 1103 while (datalen > 0) { 1104 if (!sdhc_wait_intr(hp, SDHC_BUFFER_READ_READY| 1105 SDHC_BUFFER_WRITE_READY, SDHC_BUFFER_TIMEOUT)) { 1106 error = ETIMEDOUT; 1107 break; 1108 } 1109 1110 if ((error = sdhc_wait_state(hp, mask, mask)) != 0) 1111 break; 1112 1113 i = MIN(datalen, cmd->c_blklen); 1114 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1115 sdhc_read_data(hp, datap, i); 1116 else 1117 sdhc_write_data(hp, datap, i); 1118 1119 datap += i; 1120 datalen -= i; 1121 } 1122 1123 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1124 SDHC_TRANSFER_TIMEOUT)) 1125 error = ETIMEDOUT; 1126 1127 done: 1128 if (error != 0) 1129 cmd->c_error = error; 1130 SET(cmd->c_flags, SCF_ITSDONE); 1131 1132 DPRINTF(1,("%s: data transfer done (error=%d)\n", 1133 DEVNAME(hp->sc), cmd->c_error)); 1134 } 1135 1136 void 1137 sdhc_read_data(struct sdhc_host *hp, u_char *datap, int datalen) 1138 { 1139 while (datalen > 3) { 1140 *(u_int32_t *)datap = HREAD4(hp, SDHC_DATA); 1141 datap += 4; 1142 datalen -= 4; 1143 } 1144 if (datalen > 0) { 1145 u_int32_t rv = HREAD4(hp, SDHC_DATA); 1146 do { 1147 *datap++ = rv & 0xff; 1148 rv = rv >> 8; 1149 } while (--datalen > 0); 1150 } 1151 } 1152 1153 void 1154 sdhc_write_data(struct sdhc_host *hp, u_char *datap, int datalen) 1155 { 1156 while (datalen > 3) { 1157 DPRINTF(3,("%08x\n", *(u_int32_t *)datap)); 1158 HWRITE4(hp, SDHC_DATA, *((u_int32_t *)datap)); 1159 datap += 4; 1160 datalen -= 4; 1161 } 1162 if (datalen > 0) { 1163 u_int32_t rv = *datap++; 1164 if (datalen > 1) 1165 rv |= *datap++ << 8; 1166 if (datalen > 2) 1167 rv |= *datap++ << 16; 1168 DPRINTF(3,("rv %08x\n", rv)); 1169 HWRITE4(hp, SDHC_DATA, rv); 1170 } 1171 } 1172 1173 /* Prepare for another command. */ 1174 int 1175 sdhc_soft_reset(struct sdhc_host *hp, int mask) 1176 { 1177 int timo; 1178 1179 DPRINTF(1,("%s: software reset reg=%#x\n", DEVNAME(hp->sc), mask)); 1180 1181 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1182 for (timo = 10; timo > 0; timo--) { 1183 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1184 break; 1185 sdmmc_delay(10000); 1186 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1187 } 1188 if (timo == 0) { 1189 DPRINTF(1,("%s: timeout reg=%#x\n", DEVNAME(hp->sc), 1190 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1191 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1192 return (ETIMEDOUT); 1193 } 1194 1195 return (0); 1196 } 1197 1198 int 1199 sdhc_wait_intr_cold(struct sdhc_host *hp, int mask, int secs) 1200 { 1201 int status, usecs; 1202 1203 mask |= SDHC_ERROR_INTERRUPT; 1204 usecs = secs * 1000000; 1205 status = hp->intr_status; 1206 while ((status & mask) == 0) { 1207 1208 status = HREAD2(hp, SDHC_NINTR_STATUS); 1209 if (ISSET(status, SDHC_NINTR_STATUS_MASK)) { 1210 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1211 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1212 uint16_t error; 1213 error = HREAD2(hp, SDHC_EINTR_STATUS); 1214 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1215 hp->intr_status |= status; 1216 1217 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1218 SDHC_DATA_TIMEOUT_ERROR)) 1219 break; 1220 } 1221 1222 if (ISSET(status, SDHC_BUFFER_READ_READY | 1223 SDHC_BUFFER_WRITE_READY | SDHC_COMMAND_COMPLETE | 1224 SDHC_TRANSFER_COMPLETE)) { 1225 hp->intr_status |= status; 1226 break; 1227 } 1228 1229 if (ISSET(status, SDHC_CARD_INTERRUPT)) { 1230 HSET2(hp, SDHC_NINTR_STATUS_EN, 1231 SDHC_CARD_INTERRUPT); 1232 } 1233 1234 continue; 1235 } 1236 1237 delay(1); 1238 if (usecs-- == 0) { 1239 status |= SDHC_ERROR_INTERRUPT; 1240 break; 1241 } 1242 } 1243 1244 hp->intr_status &= ~(status & mask); 1245 return (status & mask); 1246 } 1247 1248 int 1249 sdhc_wait_intr(struct sdhc_host *hp, int mask, int secs) 1250 { 1251 int status; 1252 int s; 1253 1254 if (cold) 1255 return (sdhc_wait_intr_cold(hp, mask, secs)); 1256 1257 mask |= SDHC_ERROR_INTERRUPT; 1258 1259 s = splsdmmc(); 1260 status = hp->intr_status & mask; 1261 while (status == 0) { 1262 if (tsleep_nsec(&hp->intr_status, PWAIT, "hcintr", 1263 SEC_TO_NSEC(secs)) == EWOULDBLOCK) { 1264 status |= SDHC_ERROR_INTERRUPT; 1265 break; 1266 } 1267 status = hp->intr_status & mask; 1268 } 1269 hp->intr_status &= ~status; 1270 1271 DPRINTF(2,("%s: intr status %#x error %#x\n", DEVNAME(hp->sc), status, 1272 hp->intr_error_status)); 1273 1274 /* Command timeout has higher priority than command complete. */ 1275 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1276 hp->intr_error_status = 0; 1277 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1278 status = 0; 1279 } 1280 1281 splx(s); 1282 return status; 1283 } 1284 1285 /* 1286 * Established by attachment driver at interrupt priority IPL_SDMMC. 1287 */ 1288 int 1289 sdhc_intr(void *arg) 1290 { 1291 struct sdhc_softc *sc = arg; 1292 int host; 1293 int done = 0; 1294 1295 /* We got an interrupt, but we don't know from which slot. */ 1296 for (host = 0; host < sc->sc_nhosts; host++) { 1297 struct sdhc_host *hp = sc->sc_host[host]; 1298 u_int16_t status; 1299 1300 if (hp == NULL) 1301 continue; 1302 1303 /* Find out which interrupts are pending. */ 1304 status = HREAD2(hp, SDHC_NINTR_STATUS); 1305 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1306 continue; /* no interrupt for us */ 1307 1308 /* Acknowledge the interrupts we are about to handle. */ 1309 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1310 DPRINTF(2,("%s: interrupt status=%b\n", DEVNAME(hp->sc), 1311 status, SDHC_NINTR_STATUS_BITS)); 1312 1313 /* Claim this interrupt. */ 1314 done = 1; 1315 1316 /* 1317 * Service error interrupts. 1318 */ 1319 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1320 u_int16_t error; 1321 1322 /* Acknowledge error interrupts. */ 1323 error = HREAD2(hp, SDHC_EINTR_STATUS); 1324 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1325 DPRINTF(2,("%s: error interrupt, status=%b\n", 1326 DEVNAME(hp->sc), error, SDHC_EINTR_STATUS_BITS)); 1327 1328 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1329 SDHC_DATA_TIMEOUT_ERROR)) { 1330 hp->intr_error_status |= error; 1331 hp->intr_status |= status; 1332 wakeup(&hp->intr_status); 1333 } 1334 } 1335 1336 /* 1337 * Wake up the sdmmc event thread to scan for cards. 1338 */ 1339 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) 1340 sdmmc_needs_discover(hp->sdmmc); 1341 1342 /* 1343 * Wake up the blocking process to service command 1344 * related interrupt(s). 1345 */ 1346 if (ISSET(status, SDHC_BUFFER_READ_READY| 1347 SDHC_BUFFER_WRITE_READY|SDHC_COMMAND_COMPLETE| 1348 SDHC_TRANSFER_COMPLETE)) { 1349 hp->intr_status |= status; 1350 wakeup(&hp->intr_status); 1351 } 1352 1353 /* 1354 * Service SD card interrupts. 1355 */ 1356 if (ISSET(status, SDHC_CARD_INTERRUPT)) { 1357 DPRINTF(0,("%s: card interrupt\n", DEVNAME(hp->sc))); 1358 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1359 sdmmc_card_intr(hp->sdmmc); 1360 } 1361 } 1362 return done; 1363 } 1364 1365 void 1366 sdhc_needs_discover(struct sdhc_softc *sc) 1367 { 1368 int host; 1369 1370 for (host = 0; host < sc->sc_nhosts; host++) 1371 sdmmc_needs_discover(sc->sc_host[host]->sdmmc); 1372 } 1373 1374 #ifdef SDHC_DEBUG 1375 void 1376 sdhc_dump_regs(struct sdhc_host *hp) 1377 { 1378 printf("0x%02x PRESENT_STATE: %b\n", SDHC_PRESENT_STATE, 1379 HREAD4(hp, SDHC_PRESENT_STATE), SDHC_PRESENT_STATE_BITS); 1380 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 1381 HREAD1(hp, SDHC_POWER_CTL)); 1382 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 1383 HREAD2(hp, SDHC_NINTR_STATUS)); 1384 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 1385 HREAD2(hp, SDHC_EINTR_STATUS)); 1386 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 1387 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 1388 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 1389 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 1390 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 1391 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 1392 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 1393 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 1394 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 1395 HREAD4(hp, SDHC_CAPABILITIES)); 1396 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 1397 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 1398 } 1399 #endif 1400 1401 int 1402 sdhc_hibernate_init(sdmmc_chipset_handle_t sch, void *fake_softc) 1403 { 1404 struct sdhc_host *hp, *fhp; 1405 fhp = fake_softc; 1406 hp = sch; 1407 *fhp = *hp; 1408 1409 return (0); 1410 } 1411