1 /* $OpenBSD: sdhc.c,v 1.52 2016/05/15 22:21:55 kettenis Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * SD Host Controller driver based on the SD Host Controller Standard 21 * Simplified Specification Version 1.00 (www.sdcard.com). 22 */ 23 24 #include <sys/param.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/malloc.h> 28 #include <sys/systm.h> 29 30 #include <dev/sdmmc/sdhcreg.h> 31 #include <dev/sdmmc/sdhcvar.h> 32 #include <dev/sdmmc/sdmmcchip.h> 33 #include <dev/sdmmc/sdmmcreg.h> 34 #include <dev/sdmmc/sdmmcvar.h> 35 36 #define SDHC_COMMAND_TIMEOUT hz 37 #define SDHC_BUFFER_TIMEOUT hz 38 #define SDHC_TRANSFER_TIMEOUT hz 39 #define SDHC_DMA_TIMEOUT (hz*3) 40 41 struct sdhc_host { 42 struct sdhc_softc *sc; /* host controller device */ 43 struct device *sdmmc; /* generic SD/MMC device */ 44 bus_space_tag_t iot; /* host register set tag */ 45 bus_space_handle_t ioh; /* host register set handle */ 46 u_int16_t version; /* specification version */ 47 u_int clkbase; /* base clock frequency in KHz */ 48 int maxblklen; /* maximum block length */ 49 int flags; /* flags for this host */ 50 u_int32_t ocr; /* OCR value from capabilities */ 51 u_int8_t regs[14]; /* host controller state */ 52 u_int16_t intr_status; /* soft interrupt status */ 53 u_int16_t intr_error_status; /* soft error status */ 54 55 bus_dmamap_t adma_map; 56 bus_dma_segment_t adma_segs[1]; 57 caddr_t adma2; 58 }; 59 60 /* flag values */ 61 #define SHF_USE_DMA 0x0001 62 63 #define HREAD1(hp, reg) \ 64 (bus_space_read_1((hp)->iot, (hp)->ioh, (reg))) 65 #define HREAD2(hp, reg) \ 66 (bus_space_read_2((hp)->iot, (hp)->ioh, (reg))) 67 #define HREAD4(hp, reg) \ 68 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 69 #define HWRITE1(hp, reg, val) \ 70 bus_space_write_1((hp)->iot, (hp)->ioh, (reg), (val)) 71 #define HWRITE2(hp, reg, val) \ 72 bus_space_write_2((hp)->iot, (hp)->ioh, (reg), (val)) 73 #define HWRITE4(hp, reg, val) \ 74 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 75 #define HCLR1(hp, reg, bits) \ 76 HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)) 77 #define HCLR2(hp, reg, bits) \ 78 HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)) 79 #define HSET1(hp, reg, bits) \ 80 HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)) 81 #define HSET2(hp, reg, bits) \ 82 HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)) 83 84 int sdhc_host_reset(sdmmc_chipset_handle_t); 85 u_int32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 86 int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 87 int sdhc_card_detect(sdmmc_chipset_handle_t); 88 int sdhc_bus_power(sdmmc_chipset_handle_t, u_int32_t); 89 int sdhc_bus_clock(sdmmc_chipset_handle_t, int, int); 90 int sdhc_bus_width(sdmmc_chipset_handle_t, int); 91 void sdhc_card_intr_mask(sdmmc_chipset_handle_t, int); 92 void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 93 int sdhc_signal_voltage(sdmmc_chipset_handle_t, int); 94 void sdhc_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *); 95 int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 96 int sdhc_wait_state(struct sdhc_host *, u_int32_t, u_int32_t); 97 int sdhc_soft_reset(struct sdhc_host *, int); 98 int sdhc_wait_intr(struct sdhc_host *, int, int); 99 void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 100 void sdhc_read_data(struct sdhc_host *, u_char *, int); 101 void sdhc_write_data(struct sdhc_host *, u_char *, int); 102 103 #ifdef SDHC_DEBUG 104 int sdhcdebug = 0; 105 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 106 void sdhc_dump_regs(struct sdhc_host *); 107 #else 108 #define DPRINTF(n,s) do {} while(0) 109 #endif 110 111 struct sdmmc_chip_functions sdhc_functions = { 112 /* host controller reset */ 113 sdhc_host_reset, 114 /* host controller capabilities */ 115 sdhc_host_ocr, 116 sdhc_host_maxblklen, 117 /* card detection */ 118 sdhc_card_detect, 119 /* bus power and clock frequency */ 120 sdhc_bus_power, 121 sdhc_bus_clock, 122 sdhc_bus_width, 123 /* command execution */ 124 sdhc_exec_command, 125 /* card interrupt */ 126 sdhc_card_intr_mask, 127 sdhc_card_intr_ack, 128 /* UHS functions */ 129 sdhc_signal_voltage 130 }; 131 132 struct cfdriver sdhc_cd = { 133 NULL, "sdhc", DV_DULL 134 }; 135 136 /* 137 * Called by attachment driver. For each SD card slot there is one SD 138 * host controller standard register set. (1.3) 139 */ 140 int 141 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 142 bus_space_handle_t ioh, bus_size_t iosize, int usedma, u_int32_t caps) 143 { 144 struct sdmmcbus_attach_args saa; 145 struct sdhc_host *hp; 146 int error = 1; 147 int max_clock; 148 #ifdef SDHC_DEBUG 149 u_int16_t version; 150 151 version = bus_space_read_2(iot, ioh, SDHC_HOST_CTL_VERSION); 152 printf("%s: SD Host Specification/Vendor Version ", 153 sc->sc_dev.dv_xname); 154 switch(SDHC_SPEC_VERSION(version)) { 155 case 0x00: 156 printf("1.0/%u\n", SDHC_VENDOR_VERSION(version)); 157 break; 158 default: 159 printf(">1.0/%u\n", SDHC_VENDOR_VERSION(version)); 160 break; 161 } 162 #endif 163 164 /* Allocate one more host structure. */ 165 sc->sc_nhosts++; 166 hp = malloc(sizeof(*hp), M_DEVBUF, M_WAITOK | M_ZERO); 167 sc->sc_host[sc->sc_nhosts - 1] = hp; 168 169 /* Fill in the new host structure. */ 170 hp->sc = sc; 171 hp->iot = iot; 172 hp->ioh = ioh; 173 174 /* Store specification version. */ 175 hp->version = bus_space_read_2(iot, ioh, SDHC_HOST_CTL_VERSION); 176 177 /* 178 * Reset the host controller and enable interrupts. 179 */ 180 (void)sdhc_host_reset(hp); 181 182 /* Determine host capabilities. */ 183 if (caps == 0) 184 caps = HREAD4(hp, SDHC_CAPABILITIES); 185 186 /* Use DMA if the host system and the controller support it. */ 187 if (usedma && ISSET(caps, SDHC_ADMA2_SUPP)) 188 SET(hp->flags, SHF_USE_DMA); 189 190 /* 191 * Determine the base clock frequency. (2.2.24) 192 */ 193 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 194 /* SDHC 3.0 supports 10-255 MHz. */ 195 max_clock = 255000; 196 if (SDHC_BASE_FREQ_KHZ_V3(caps) != 0) 197 hp->clkbase = SDHC_BASE_FREQ_KHZ_V3(caps); 198 } else { 199 /* SDHC 1.0/2.0 supports only 10-63 MHz. */ 200 max_clock = 63000; 201 if (SDHC_BASE_FREQ_KHZ(caps) != 0) 202 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 203 } 204 if (hp->clkbase == 0) { 205 /* The attachment driver must tell us. */ 206 printf("%s: base clock frequency unknown\n", 207 sc->sc_dev.dv_xname); 208 goto err; 209 } else if (hp->clkbase < 10000 || hp->clkbase > max_clock) { 210 printf("%s: base clock frequency out of range: %u MHz\n", 211 sc->sc_dev.dv_xname, hp->clkbase / 1000); 212 goto err; 213 } 214 215 printf("%s: SDHC %d.0, %d MHz base clock\n", DEVNAME(sc), 216 SDHC_SPEC_VERSION(hp->version) + 1, hp->clkbase / 1000); 217 218 /* 219 * XXX Set the data timeout counter value according to 220 * capabilities. (2.2.15) 221 */ 222 223 /* 224 * Determine SD bus voltage levels supported by the controller. 225 */ 226 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)) 227 SET(hp->ocr, MMC_OCR_1_65V_1_95V); 228 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) 229 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 230 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) 231 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 232 233 /* 234 * Determine the maximum block length supported by the host 235 * controller. (2.2.24) 236 */ 237 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 238 case SDHC_MAX_BLK_LEN_512: 239 hp->maxblklen = 512; 240 break; 241 case SDHC_MAX_BLK_LEN_1024: 242 hp->maxblklen = 1024; 243 break; 244 case SDHC_MAX_BLK_LEN_2048: 245 hp->maxblklen = 2048; 246 break; 247 default: 248 hp->maxblklen = 1; 249 break; 250 } 251 252 if (ISSET(hp->flags, SHF_USE_DMA)) { 253 int rseg; 254 255 /* Allocate ADMA2 descriptor memory */ 256 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 257 PAGE_SIZE, hp->adma_segs, 1, &rseg, 258 BUS_DMA_WAITOK | BUS_DMA_ZERO); 259 if (error) 260 goto adma_done; 261 error = bus_dmamem_map(sc->sc_dmat, hp->adma_segs, rseg, 262 PAGE_SIZE, &hp->adma2, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 263 if (error) { 264 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg); 265 goto adma_done; 266 } 267 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 268 0, BUS_DMA_WAITOK, &hp->adma_map); 269 if (error) { 270 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE); 271 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg); 272 goto adma_done; 273 } 274 error = bus_dmamap_load(sc->sc_dmat, hp->adma_map, 275 hp->adma2, PAGE_SIZE, NULL, 276 BUS_DMA_WAITOK | BUS_DMA_WRITE); 277 if (error) { 278 bus_dmamap_destroy(sc->sc_dmat, hp->adma_map); 279 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE); 280 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg); 281 goto adma_done; 282 } 283 284 adma_done: 285 if (error) { 286 printf("%s: can't allocate DMA descriptor table\n", 287 DEVNAME(hp->sc)); 288 CLR(hp->flags, SHF_USE_DMA); 289 } 290 } 291 292 /* 293 * Attach the generic SD/MMC bus driver. (The bus driver must 294 * not invoke any chipset functions before it is attached.) 295 */ 296 bzero(&saa, sizeof(saa)); 297 saa.saa_busname = "sdmmc"; 298 saa.sct = &sdhc_functions; 299 saa.sch = hp; 300 saa.caps = SMC_CAPS_4BIT_MODE; 301 saa.dmat = sc->sc_dmat; 302 if (ISSET(hp->flags, SHF_USE_DMA)) 303 saa.caps |= SMC_CAPS_DMA; 304 305 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 306 saa.caps |= SMC_CAPS_SD_HIGHSPEED; 307 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 308 saa.caps |= SMC_CAPS_MMC_HIGHSPEED; 309 310 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 311 uint32_t caps2 = HREAD4(hp, SDHC_CAPABILITIES2); 312 313 if (ISSET(caps, SDHC_8BIT_MODE_SUPP)) 314 saa.caps |= SMC_CAPS_8BIT_MODE; 315 316 if (ISSET(caps2, SDHC_DDR50_SUPP)) 317 saa.caps |= SMC_CAPS_MMC_DDR52; 318 } 319 320 hp->sdmmc = config_found(&sc->sc_dev, &saa, NULL); 321 if (hp->sdmmc == NULL) { 322 error = 0; 323 goto err; 324 } 325 326 return 0; 327 328 err: 329 free(hp, M_DEVBUF, 0); 330 sc->sc_host[sc->sc_nhosts - 1] = NULL; 331 sc->sc_nhosts--; 332 return (error); 333 } 334 335 int 336 sdhc_activate(struct device *self, int act) 337 { 338 struct sdhc_softc *sc = (struct sdhc_softc *)self; 339 struct sdhc_host *hp; 340 int n, i, rv = 0; 341 342 switch (act) { 343 case DVACT_SUSPEND: 344 rv = config_activate_children(self, act); 345 346 /* Save the host controller state. */ 347 for (n = 0; n < sc->sc_nhosts; n++) { 348 hp = sc->sc_host[n]; 349 for (i = 0; i < sizeof hp->regs; i++) 350 hp->regs[i] = HREAD1(hp, i); 351 } 352 break; 353 case DVACT_RESUME: 354 /* Restore the host controller state. */ 355 for (n = 0; n < sc->sc_nhosts; n++) { 356 hp = sc->sc_host[n]; 357 (void)sdhc_host_reset(hp); 358 for (i = 0; i < sizeof hp->regs; i++) 359 HWRITE1(hp, i, hp->regs[i]); 360 } 361 rv = config_activate_children(self, act); 362 break; 363 case DVACT_POWERDOWN: 364 rv = config_activate_children(self, act); 365 sdhc_shutdown(self); 366 break; 367 default: 368 rv = config_activate_children(self, act); 369 break; 370 } 371 return (rv); 372 } 373 374 /* 375 * Shutdown hook established by or called from attachment driver. 376 */ 377 void 378 sdhc_shutdown(void *arg) 379 { 380 struct sdhc_softc *sc = arg; 381 struct sdhc_host *hp; 382 int i; 383 384 /* XXX chip locks up if we don't disable it before reboot. */ 385 for (i = 0; i < sc->sc_nhosts; i++) { 386 hp = sc->sc_host[i]; 387 (void)sdhc_host_reset(hp); 388 } 389 } 390 391 /* 392 * Reset the host controller. Called during initialization, when 393 * cards are removed, upon resume, and during error recovery. 394 */ 395 int 396 sdhc_host_reset(sdmmc_chipset_handle_t sch) 397 { 398 struct sdhc_host *hp = sch; 399 u_int16_t imask; 400 int error; 401 int s; 402 403 s = splsdmmc(); 404 405 /* Disable all interrupts. */ 406 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 407 408 /* 409 * Reset the entire host controller and wait up to 100ms for 410 * the controller to clear the reset bit. 411 */ 412 if ((error = sdhc_soft_reset(hp, SDHC_RESET_ALL)) != 0) { 413 splx(s); 414 return (error); 415 } 416 417 /* Set data timeout counter value to max for now. */ 418 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 419 420 /* Enable interrupts. */ 421 imask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 422 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 423 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 424 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 425 426 HWRITE2(hp, SDHC_NINTR_STATUS_EN, imask); 427 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 428 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, imask); 429 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 430 431 splx(s); 432 return 0; 433 } 434 435 u_int32_t 436 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 437 { 438 struct sdhc_host *hp = sch; 439 return hp->ocr; 440 } 441 442 int 443 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 444 { 445 struct sdhc_host *hp = sch; 446 return hp->maxblklen; 447 } 448 449 /* 450 * Return non-zero if the card is currently inserted. 451 */ 452 int 453 sdhc_card_detect(sdmmc_chipset_handle_t sch) 454 { 455 struct sdhc_host *hp = sch; 456 457 if (hp->sc->sc_card_detect) 458 return hp->sc->sc_card_detect(hp->sc); 459 460 return ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED) ? 461 1 : 0; 462 } 463 464 /* 465 * Set or change SD bus voltage and enable or disable SD bus power. 466 * Return zero on success. 467 */ 468 int 469 sdhc_bus_power(sdmmc_chipset_handle_t sch, u_int32_t ocr) 470 { 471 struct sdhc_host *hp = sch; 472 u_int8_t vdd; 473 int s; 474 475 s = splsdmmc(); 476 477 /* 478 * Disable bus power before voltage change. 479 */ 480 if (!(hp->sc->sc_flags & SDHC_F_NOPWR0)) 481 HWRITE1(hp, SDHC_POWER_CTL, 0); 482 483 /* If power is disabled, reset the host and return now. */ 484 if (ocr == 0) { 485 splx(s); 486 (void)sdhc_host_reset(hp); 487 return 0; 488 } 489 490 /* 491 * Select the maximum voltage according to capabilities. 492 */ 493 ocr &= hp->ocr; 494 if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) 495 vdd = SDHC_VOLTAGE_3_3V; 496 else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) 497 vdd = SDHC_VOLTAGE_3_0V; 498 else if (ISSET(ocr, MMC_OCR_1_65V_1_95V)) 499 vdd = SDHC_VOLTAGE_1_8V; 500 else { 501 /* Unsupported voltage level requested. */ 502 splx(s); 503 return EINVAL; 504 } 505 506 /* 507 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 508 * voltage ramp until power rises. 509 */ 510 HWRITE1(hp, SDHC_POWER_CTL, (vdd << SDHC_VOLTAGE_SHIFT) | 511 SDHC_BUS_POWER); 512 sdmmc_delay(10000); 513 514 /* 515 * The host system may not power the bus due to battery low, 516 * etc. In that case, the host controller should clear the 517 * bus power bit. 518 */ 519 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 520 splx(s); 521 return ENXIO; 522 } 523 524 splx(s); 525 return 0; 526 } 527 528 /* 529 * Return the smallest possible base clock frequency divisor value 530 * for the CLOCK_CTL register to produce `freq' (KHz). 531 */ 532 static int 533 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq) 534 { 535 int max_div = 256; 536 int div; 537 538 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) 539 max_div = 2046; 540 541 for (div = 1; div <= max_div; div *= 2) 542 if ((hp->clkbase / div) <= freq) 543 return (div / 2); 544 /* No divisor found. */ 545 return -1; 546 } 547 548 /* 549 * Set or change SDCLK frequency or disable the SD clock. 550 * Return zero on success. 551 */ 552 int 553 sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing) 554 { 555 struct sdhc_host *hp = sch; 556 int s; 557 int div; 558 int sdclk; 559 int timo; 560 int error = 0; 561 562 s = splsdmmc(); 563 564 #ifdef DIAGNOSTIC 565 /* Must not stop the clock if commands are in progress. */ 566 if (ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK) && 567 sdhc_card_detect(hp)) 568 printf("sdhc_sdclk_frequency_select: command in progress\n"); 569 #endif 570 571 /* 572 * Stop SD clock before changing the frequency. 573 */ 574 HWRITE2(hp, SDHC_CLOCK_CTL, 0); 575 if (freq == SDMMC_SDCLK_OFF) 576 goto ret; 577 578 if (timing == SDMMC_TIMING_LEGACY) 579 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 580 else 581 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 582 583 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 584 switch (timing) { 585 case SDMMC_TIMING_MMC_DDR52: 586 HCLR2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_MASK); 587 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_DDR50); 588 break; 589 } 590 } 591 592 /* 593 * Set the minimum base clock frequency divisor. 594 */ 595 if ((div = sdhc_clock_divisor(hp, freq)) < 0) { 596 /* Invalid base clock frequency or `freq' value. */ 597 error = EINVAL; 598 goto ret; 599 } 600 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) 601 sdclk = SDHC_SDCLK_DIV_V3(div); 602 else 603 sdclk = SDHC_SDCLK_DIV(div); 604 HWRITE2(hp, SDHC_CLOCK_CTL, sdclk); 605 606 /* 607 * Start internal clock. Wait 10ms for stabilization. 608 */ 609 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 610 for (timo = 1000; timo > 0; timo--) { 611 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), SDHC_INTCLK_STABLE)) 612 break; 613 sdmmc_delay(10); 614 } 615 if (timo == 0) { 616 error = ETIMEDOUT; 617 goto ret; 618 } 619 620 /* 621 * Enable SD clock. 622 */ 623 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 624 625 ret: 626 splx(s); 627 return error; 628 } 629 630 int 631 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 632 { 633 struct sdhc_host *hp = (struct sdhc_host *)sch; 634 int reg; 635 int s; 636 637 if (width != 1 && width != 4 && width != 8) 638 return EINVAL; 639 640 s = splsdmmc(); 641 642 reg = HREAD1(hp, SDHC_HOST_CTL); 643 reg &= ~SDHC_4BIT_MODE; 644 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 645 reg &= ~SDHC_8BIT_MODE; 646 } 647 if (width == 4) { 648 reg |= SDHC_4BIT_MODE; 649 } else if (width == 8) { 650 KASSERT(SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3); 651 reg |= SDHC_8BIT_MODE; 652 } 653 HWRITE1(hp, SDHC_HOST_CTL, reg); 654 655 splx(s); 656 657 return 0; 658 } 659 660 void 661 sdhc_card_intr_mask(sdmmc_chipset_handle_t sch, int enable) 662 { 663 struct sdhc_host *hp = sch; 664 665 if (enable) { 666 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 667 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 668 } else { 669 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 670 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 671 } 672 } 673 674 void 675 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 676 { 677 struct sdhc_host *hp = sch; 678 679 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 680 } 681 682 int 683 sdhc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 684 { 685 struct sdhc_host *hp = sch; 686 687 if (SDHC_SPEC_VERSION(hp->version) < SDHC_SPEC_V3) 688 return EINVAL; 689 690 switch (signal_voltage) { 691 case SDMMC_SIGNAL_VOLTAGE_180: 692 HSET2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN); 693 break; 694 case SDMMC_SIGNAL_VOLTAGE_330: 695 HCLR2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN); 696 break; 697 default: 698 return EINVAL; 699 } 700 701 /* Regulator output shall be stable within 5 ms. */ 702 sdmmc_delay(5000); 703 704 /* Host controller clears this bit if 1.8V signalling fails. */ 705 if (signal_voltage == SDMMC_SIGNAL_VOLTAGE_180 && 706 !ISSET(HREAD4(hp, SDHC_HOST_CTL2), SDHC_1_8V_SIGNAL_EN)) 707 return EIO; 708 709 return 0; 710 } 711 712 int 713 sdhc_wait_state(struct sdhc_host *hp, u_int32_t mask, u_int32_t value) 714 { 715 u_int32_t state; 716 int timeout; 717 718 for (timeout = 10; timeout > 0; timeout--) { 719 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) 720 == value) 721 return 0; 722 sdmmc_delay(10000); 723 } 724 DPRINTF(0,("%s: timeout waiting for %x (state=%b)\n", DEVNAME(hp->sc), 725 value, state, SDHC_PRESENT_STATE_BITS)); 726 return ETIMEDOUT; 727 } 728 729 void 730 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 731 { 732 struct sdhc_host *hp = sch; 733 int error; 734 735 /* 736 * Start the MMC command, or mark `cmd' as failed and return. 737 */ 738 error = sdhc_start_command(hp, cmd); 739 if (error != 0) { 740 cmd->c_error = error; 741 SET(cmd->c_flags, SCF_ITSDONE); 742 return; 743 } 744 745 /* 746 * Wait until the command phase is done, or until the command 747 * is marked done for any other reason. 748 */ 749 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, 750 SDHC_COMMAND_TIMEOUT)) { 751 cmd->c_error = ETIMEDOUT; 752 SET(cmd->c_flags, SCF_ITSDONE); 753 return; 754 } 755 756 /* 757 * The host controller removes bits [0:7] from the response 758 * data (CRC) and we pass the data up unchanged to the bus 759 * driver (without padding). 760 */ 761 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 762 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 763 u_char *p = (u_char *)cmd->c_resp; 764 int i; 765 766 for (i = 0; i < 15; i++) 767 *p++ = HREAD1(hp, SDHC_RESPONSE + i); 768 } else 769 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE); 770 } 771 772 /* 773 * If the command has data to transfer in any direction, 774 * execute the transfer now. 775 */ 776 if (cmd->c_error == 0 && cmd->c_data != NULL) 777 sdhc_transfer_data(hp, cmd); 778 779 /* Turn off the LED. */ 780 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 781 782 DPRINTF(1,("%s: cmd %u done (flags=%#x error=%d)\n", 783 DEVNAME(hp->sc), cmd->c_opcode, cmd->c_flags, cmd->c_error)); 784 SET(cmd->c_flags, SCF_ITSDONE); 785 } 786 787 int 788 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 789 { 790 struct sdhc_adma2_descriptor32 *desc = (void *)hp->adma2; 791 struct sdhc_softc *sc = hp->sc; 792 u_int16_t blksize = 0; 793 u_int16_t blkcount = 0; 794 u_int16_t mode; 795 u_int16_t command; 796 int error; 797 int seg; 798 int s; 799 800 DPRINTF(1,("%s: start cmd %u arg=%#x data=%#x dlen=%d flags=%#x " 801 "proc=\"%s\"\n", DEVNAME(hp->sc), cmd->c_opcode, cmd->c_arg, 802 cmd->c_data, cmd->c_datalen, cmd->c_flags, curproc ? 803 curproc->p_comm : "")); 804 805 /* 806 * The maximum block length for commands should be the minimum 807 * of the host buffer size and the card buffer size. (1.7.2) 808 */ 809 810 /* Fragment the data into proper blocks. */ 811 if (cmd->c_datalen > 0) { 812 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 813 blkcount = cmd->c_datalen / blksize; 814 if (cmd->c_datalen % blksize > 0) { 815 /* XXX: Split this command. (1.7.4) */ 816 printf("%s: data not a multiple of %d bytes\n", 817 DEVNAME(hp->sc), blksize); 818 return EINVAL; 819 } 820 } 821 822 /* Check limit imposed by 9-bit block count. (1.7.2) */ 823 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 824 printf("%s: too much data\n", DEVNAME(hp->sc)); 825 return EINVAL; 826 } 827 828 /* Prepare transfer mode register value. (2.2.5) */ 829 mode = 0; 830 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 831 mode |= SDHC_READ_MODE; 832 if (blkcount > 0) { 833 mode |= SDHC_BLOCK_COUNT_ENABLE; 834 if (blkcount > 1) { 835 mode |= SDHC_MULTI_BLOCK_MODE; 836 /* XXX only for memory commands? */ 837 mode |= SDHC_AUTO_CMD12_ENABLE; 838 } 839 } 840 if (cmd->c_dmamap && cmd->c_datalen > 0 && 841 ISSET(hp->flags, SHF_USE_DMA)) 842 mode |= SDHC_DMA_ENABLE; 843 844 /* 845 * Prepare command register value. (2.2.6) 846 */ 847 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << 848 SDHC_COMMAND_INDEX_SHIFT; 849 850 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 851 command |= SDHC_CRC_CHECK_ENABLE; 852 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 853 command |= SDHC_INDEX_CHECK_ENABLE; 854 if (cmd->c_data != NULL) 855 command |= SDHC_DATA_PRESENT_SELECT; 856 857 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 858 command |= SDHC_NO_RESPONSE; 859 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 860 command |= SDHC_RESP_LEN_136; 861 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 862 command |= SDHC_RESP_LEN_48_CHK_BUSY; 863 else 864 command |= SDHC_RESP_LEN_48; 865 866 /* Wait until command and data inhibit bits are clear. (1.5) */ 867 if ((error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0)) != 0) 868 return error; 869 870 s = splsdmmc(); 871 872 /* Alert the user not to remove the card. */ 873 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 874 875 /* Set DMA start address if SHF_USE_DMA is set. */ 876 if (cmd->c_dmamap && ISSET(hp->flags, SHF_USE_DMA)) { 877 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 878 bus_addr_t paddr = 879 cmd->c_dmamap->dm_segs[seg].ds_addr; 880 uint16_t len = 881 cmd->c_dmamap->dm_segs[seg].ds_len == 65536 ? 882 0 : cmd->c_dmamap->dm_segs[seg].ds_len; 883 uint16_t attr; 884 885 attr = SDHC_ADMA2_VALID | SDHC_ADMA2_ACT_TRANS; 886 if (seg == cmd->c_dmamap->dm_nsegs - 1) 887 attr |= SDHC_ADMA2_END; 888 889 desc[seg].attribute = htole16(attr); 890 desc[seg].length = htole16(len); 891 desc[seg].address = htole32(paddr); 892 } 893 894 desc[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 895 896 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE, 897 BUS_DMASYNC_PREWRITE); 898 899 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT); 900 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA2); 901 902 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR, 903 hp->adma_map->dm_segs[0].ds_addr); 904 } 905 906 DPRINTF(1,("%s: cmd=%#x mode=%#x blksize=%d blkcount=%d\n", 907 DEVNAME(hp->sc), command, mode, blksize, blkcount)); 908 909 /* 910 * Start a CPU data transfer. Writing to the high order byte 911 * of the SDHC_COMMAND register triggers the SD command. (1.5) 912 */ 913 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 914 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 915 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 916 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 917 HWRITE2(hp, SDHC_COMMAND, command); 918 919 splx(s); 920 return 0; 921 } 922 923 void 924 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 925 { 926 struct sdhc_softc *sc = hp->sc; 927 u_char *datap = cmd->c_data; 928 int i, datalen; 929 int mask; 930 int error; 931 932 if (cmd->c_dmamap) { 933 int status; 934 935 error = 0; 936 for (;;) { 937 status = sdhc_wait_intr(hp, 938 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 939 SDHC_DMA_TIMEOUT); 940 if (status & SDHC_TRANSFER_COMPLETE) 941 break; 942 if (!status) { 943 error = ETIMEDOUT; 944 break; 945 } 946 } 947 948 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE, 949 BUS_DMASYNC_POSTWRITE); 950 goto done; 951 } 952 953 mask = ISSET(cmd->c_flags, SCF_CMD_READ) ? 954 SDHC_BUFFER_READ_ENABLE : SDHC_BUFFER_WRITE_ENABLE; 955 error = 0; 956 datalen = cmd->c_datalen; 957 958 DPRINTF(1,("%s: resp=%#x datalen=%d\n", DEVNAME(hp->sc), 959 MMC_R1(cmd->c_resp), datalen)); 960 961 #ifdef SDHC_DEBUG 962 /* XXX I forgot why I wanted to know when this happens :-( */ 963 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 964 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) 965 printf("%s: CMD52/53 error response flags %#x\n", 966 DEVNAME(hp->sc), MMC_R1(cmd->c_resp) & 0xff00); 967 #endif 968 969 while (datalen > 0) { 970 if (!sdhc_wait_intr(hp, SDHC_BUFFER_READ_READY| 971 SDHC_BUFFER_WRITE_READY, SDHC_BUFFER_TIMEOUT)) { 972 error = ETIMEDOUT; 973 break; 974 } 975 976 if ((error = sdhc_wait_state(hp, mask, mask)) != 0) 977 break; 978 979 i = MIN(datalen, cmd->c_blklen); 980 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 981 sdhc_read_data(hp, datap, i); 982 else 983 sdhc_write_data(hp, datap, i); 984 985 datap += i; 986 datalen -= i; 987 } 988 989 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 990 SDHC_TRANSFER_TIMEOUT)) 991 error = ETIMEDOUT; 992 993 done: 994 if (error != 0) 995 cmd->c_error = error; 996 SET(cmd->c_flags, SCF_ITSDONE); 997 998 DPRINTF(1,("%s: data transfer done (error=%d)\n", 999 DEVNAME(hp->sc), cmd->c_error)); 1000 } 1001 1002 void 1003 sdhc_read_data(struct sdhc_host *hp, u_char *datap, int datalen) 1004 { 1005 while (datalen > 3) { 1006 *(u_int32_t *)datap = HREAD4(hp, SDHC_DATA); 1007 datap += 4; 1008 datalen -= 4; 1009 } 1010 if (datalen > 0) { 1011 u_int32_t rv = HREAD4(hp, SDHC_DATA); 1012 do { 1013 *datap++ = rv & 0xff; 1014 rv = rv >> 8; 1015 } while (--datalen > 0); 1016 } 1017 } 1018 1019 void 1020 sdhc_write_data(struct sdhc_host *hp, u_char *datap, int datalen) 1021 { 1022 while (datalen > 3) { 1023 DPRINTF(3,("%08x\n", *(u_int32_t *)datap)); 1024 HWRITE4(hp, SDHC_DATA, *((u_int32_t *)datap)); 1025 datap += 4; 1026 datalen -= 4; 1027 } 1028 if (datalen > 0) { 1029 u_int32_t rv = *datap++; 1030 if (datalen > 1) 1031 rv |= *datap++ << 8; 1032 if (datalen > 2) 1033 rv |= *datap++ << 16; 1034 DPRINTF(3,("rv %08x\n", rv)); 1035 HWRITE4(hp, SDHC_DATA, rv); 1036 } 1037 } 1038 1039 /* Prepare for another command. */ 1040 int 1041 sdhc_soft_reset(struct sdhc_host *hp, int mask) 1042 { 1043 int timo; 1044 1045 DPRINTF(1,("%s: software reset reg=%#x\n", DEVNAME(hp->sc), mask)); 1046 1047 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1048 for (timo = 10; timo > 0; timo--) { 1049 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1050 break; 1051 sdmmc_delay(10000); 1052 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1053 } 1054 if (timo == 0) { 1055 DPRINTF(1,("%s: timeout reg=%#x\n", DEVNAME(hp->sc), 1056 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1057 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1058 return (ETIMEDOUT); 1059 } 1060 1061 return (0); 1062 } 1063 1064 int 1065 sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo) 1066 { 1067 int status; 1068 int s; 1069 1070 mask |= SDHC_ERROR_INTERRUPT; 1071 1072 s = splsdmmc(); 1073 status = hp->intr_status & mask; 1074 while (status == 0) { 1075 if (tsleep(&hp->intr_status, PWAIT, "hcintr", timo) 1076 == EWOULDBLOCK) { 1077 status |= SDHC_ERROR_INTERRUPT; 1078 break; 1079 } 1080 status = hp->intr_status & mask; 1081 } 1082 hp->intr_status &= ~status; 1083 1084 DPRINTF(2,("%s: intr status %#x error %#x\n", DEVNAME(hp->sc), status, 1085 hp->intr_error_status)); 1086 1087 /* Command timeout has higher priority than command complete. */ 1088 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1089 hp->intr_error_status = 0; 1090 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1091 status = 0; 1092 } 1093 1094 splx(s); 1095 return status; 1096 } 1097 1098 /* 1099 * Established by attachment driver at interrupt priority IPL_SDMMC. 1100 */ 1101 int 1102 sdhc_intr(void *arg) 1103 { 1104 struct sdhc_softc *sc = arg; 1105 int host; 1106 int done = 0; 1107 1108 /* We got an interrupt, but we don't know from which slot. */ 1109 for (host = 0; host < sc->sc_nhosts; host++) { 1110 struct sdhc_host *hp = sc->sc_host[host]; 1111 u_int16_t status; 1112 1113 if (hp == NULL) 1114 continue; 1115 1116 /* Find out which interrupts are pending. */ 1117 status = HREAD2(hp, SDHC_NINTR_STATUS); 1118 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1119 continue; /* no interrupt for us */ 1120 1121 /* Acknowledge the interrupts we are about to handle. */ 1122 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1123 DPRINTF(2,("%s: interrupt status=%b\n", DEVNAME(hp->sc), 1124 status, SDHC_NINTR_STATUS_BITS)); 1125 1126 /* Claim this interrupt. */ 1127 done = 1; 1128 1129 /* 1130 * Service error interrupts. 1131 */ 1132 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1133 u_int16_t error; 1134 1135 /* Acknowledge error interrupts. */ 1136 error = HREAD2(hp, SDHC_EINTR_STATUS); 1137 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1138 DPRINTF(2,("%s: error interrupt, status=%b\n", 1139 DEVNAME(hp->sc), error, SDHC_EINTR_STATUS_BITS)); 1140 1141 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1142 SDHC_DATA_TIMEOUT_ERROR)) { 1143 hp->intr_error_status |= error; 1144 hp->intr_status |= status; 1145 wakeup(&hp->intr_status); 1146 } 1147 } 1148 1149 /* 1150 * Wake up the sdmmc event thread to scan for cards. 1151 */ 1152 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) 1153 sdmmc_needs_discover(hp->sdmmc); 1154 1155 /* 1156 * Wake up the blocking process to service command 1157 * related interrupt(s). 1158 */ 1159 if (ISSET(status, SDHC_BUFFER_READ_READY| 1160 SDHC_BUFFER_WRITE_READY|SDHC_COMMAND_COMPLETE| 1161 SDHC_TRANSFER_COMPLETE)) { 1162 hp->intr_status |= status; 1163 wakeup(&hp->intr_status); 1164 } 1165 1166 /* 1167 * Service SD card interrupts. 1168 */ 1169 if (ISSET(status, SDHC_CARD_INTERRUPT)) { 1170 DPRINTF(0,("%s: card interrupt\n", DEVNAME(hp->sc))); 1171 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1172 sdmmc_card_intr(hp->sdmmc); 1173 } 1174 } 1175 return done; 1176 } 1177 1178 void 1179 sdhc_needs_discover(struct sdhc_softc *sc) 1180 { 1181 int host; 1182 1183 for (host = 0; host < sc->sc_nhosts; host++) 1184 sdmmc_needs_discover(sc->sc_host[host]->sdmmc); 1185 } 1186 1187 #ifdef SDHC_DEBUG 1188 void 1189 sdhc_dump_regs(struct sdhc_host *hp) 1190 { 1191 printf("0x%02x PRESENT_STATE: %b\n", SDHC_PRESENT_STATE, 1192 HREAD4(hp, SDHC_PRESENT_STATE), SDHC_PRESENT_STATE_BITS); 1193 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 1194 HREAD1(hp, SDHC_POWER_CTL)); 1195 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 1196 HREAD2(hp, SDHC_NINTR_STATUS)); 1197 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 1198 HREAD2(hp, SDHC_EINTR_STATUS)); 1199 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 1200 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 1201 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 1202 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 1203 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 1204 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 1205 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 1206 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 1207 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 1208 HREAD4(hp, SDHC_CAPABILITIES)); 1209 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 1210 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 1211 } 1212 #endif 1213