1 /* $OpenBSD: pci.c,v 1.49 2006/12/14 17:36:12 kettenis Exp $ */ 2 /* $NetBSD: pci.c,v 1.31 1997/06/06 23:48:04 thorpej Exp $ */ 3 4 /* 5 * Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <sys/malloc.h> 42 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcidevs.h> 46 47 int pcimatch(struct device *, void *, void *); 48 void pciattach(struct device *, struct device *, void *); 49 void pcipower(int, void *); 50 51 #define NMAPREG ((PCI_MAPREG_END - PCI_MAPREG_START) / \ 52 sizeof(pcireg_t)) 53 struct pci_dev { 54 LIST_ENTRY(pci_dev) pd_next; 55 struct device *pd_dev; 56 pcitag_t pd_tag; /* pci register tag */ 57 pcireg_t pd_csr; 58 pcireg_t pd_bhlc; 59 pcireg_t pd_int; 60 pcireg_t pd_map[NMAPREG]; 61 }; 62 63 #ifdef APERTURE 64 extern int allowaperture; 65 #endif 66 67 struct cfattach pci_ca = { 68 sizeof(struct pci_softc), pcimatch, pciattach 69 }; 70 71 struct cfdriver pci_cd = { 72 NULL, "pci", DV_DULL 73 }; 74 75 int pci_ndomains; 76 77 int pciprint(void *, const char *); 78 int pcisubmatch(struct device *, void *, void *); 79 80 #ifdef PCI_MACHDEP_ENUMERATE_BUS 81 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 82 #else 83 int pci_enumerate_bus(struct pci_softc *, 84 int (*)(struct pci_attach_args *), struct pci_attach_args *); 85 #endif 86 87 /* 88 * Important note about PCI-ISA bridges: 89 * 90 * Callbacks are used to configure these devices so that ISA/EISA bridges 91 * can attach their child busses after PCI configuration is done. 92 * 93 * This works because: 94 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 95 * (2) any ISA/EISA bridges must be attached to primary PCI 96 * busses (i.e. bus zero). 97 * 98 * That boils down to: there can only be one of these outstanding 99 * at a time, it is cleared when configuring PCI bus 0 before any 100 * subdevices have been found, and it is run after all subdevices 101 * of PCI bus 0 have been found. 102 * 103 * This is needed because there are some (legacy) PCI devices which 104 * can show up as ISA/EISA devices as well (the prime example of which 105 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 106 * and the bridge is seen before the video board is, the board can show 107 * up as an ISA device, and that can (bogusly) complicate the PCI device's 108 * attach code, or make the PCI device not be properly attached at all. 109 * 110 * We use the generic config_defer() facility to achieve this. 111 */ 112 113 int 114 pcimatch(struct device *parent, void *match, void *aux) 115 { 116 struct cfdata *cf = match; 117 struct pcibus_attach_args *pba = aux; 118 119 if (strcmp(pba->pba_busname, cf->cf_driver->cd_name)) 120 return (0); 121 122 /* Check the locators */ 123 if (cf->pcibuscf_bus != PCIBUS_UNK_BUS && 124 cf->pcibuscf_bus != pba->pba_bus) 125 return (0); 126 127 /* sanity */ 128 if (pba->pba_bus < 0 || pba->pba_bus > 255) 129 return (0); 130 131 /* 132 * XXX check other (hardware?) indicators 133 */ 134 135 return (1); 136 } 137 138 void 139 pciattach(struct device *parent, struct device *self, void *aux) 140 { 141 struct pcibus_attach_args *pba = aux; 142 struct pci_softc *sc = (struct pci_softc *)self; 143 144 pci_attach_hook(parent, self, pba); 145 146 printf("\n"); 147 148 LIST_INIT(&sc->sc_devs); 149 sc->sc_powerhook = powerhook_establish(pcipower, sc); 150 151 sc->sc_iot = pba->pba_iot; 152 sc->sc_memt = pba->pba_memt; 153 sc->sc_dmat = pba->pba_dmat; 154 sc->sc_pc = pba->pba_pc; 155 sc->sc_domain = pba->pba_domain; 156 sc->sc_bus = pba->pba_bus; 157 sc->sc_bridgetag = pba->pba_bridgetag; 158 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 159 sc->sc_intrswiz = pba->pba_intrswiz; 160 sc->sc_intrtag = pba->pba_intrtag; 161 pci_enumerate_bus(sc, NULL, NULL); 162 } 163 164 /* save and restore the pci config space */ 165 void 166 pcipower(int why, void *arg) 167 { 168 struct pci_softc *sc = (struct pci_softc *)arg; 169 struct pci_dev *pd; 170 pcireg_t reg; 171 int i; 172 173 LIST_FOREACH(pd, &sc->sc_devs, pd_next) { 174 if (why != PWR_RESUME) { 175 for (i = 0; i < NMAPREG; i++) 176 pd->pd_map[i] = pci_conf_read(sc->sc_pc, 177 pd->pd_tag, PCI_MAPREG_START + (i * 4)); 178 pd->pd_csr = pci_conf_read(sc->sc_pc, pd->pd_tag, 179 PCI_COMMAND_STATUS_REG); 180 pd->pd_bhlc = pci_conf_read(sc->sc_pc, pd->pd_tag, 181 PCI_BHLC_REG); 182 pd->pd_int = pci_conf_read(sc->sc_pc, pd->pd_tag, 183 PCI_INTERRUPT_REG); 184 } else { 185 for (i = 0; i < NMAPREG; i++) 186 pci_conf_write(sc->sc_pc, pd->pd_tag, 187 PCI_MAPREG_START + (i * 4), 188 pd->pd_map[i]); 189 reg = pci_conf_read(sc->sc_pc, pd->pd_tag, 190 PCI_COMMAND_STATUS_REG); 191 pci_conf_write(sc->sc_pc, pd->pd_tag, 192 PCI_COMMAND_STATUS_REG, 193 (reg & 0xffff0000) | (pd->pd_csr & 0x0000ffff)); 194 pci_conf_write(sc->sc_pc, pd->pd_tag, PCI_BHLC_REG, 195 pd->pd_bhlc); 196 pci_conf_write(sc->sc_pc, pd->pd_tag, PCI_INTERRUPT_REG, 197 pd->pd_int); 198 } 199 } 200 } 201 202 int 203 pciprint(void *aux, const char *pnp) 204 { 205 struct pci_attach_args *pa = aux; 206 char devinfo[256]; 207 208 if (pnp) { 209 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, 210 sizeof devinfo); 211 printf("%s at %s", devinfo, pnp); 212 } 213 printf(" dev %d function %d", pa->pa_device, pa->pa_function); 214 if (!pnp) { 215 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, 216 sizeof devinfo); 217 printf(" %s", devinfo); 218 } 219 220 return (UNCONF); 221 } 222 223 int 224 pcisubmatch(struct device *parent, void *match, void *aux) 225 { 226 struct cfdata *cf = match; 227 struct pci_attach_args *pa = aux; 228 229 if (cf->pcicf_dev != PCI_UNK_DEV && 230 cf->pcicf_dev != pa->pa_device) 231 return (0); 232 if (cf->pcicf_function != PCI_UNK_FUNCTION && 233 cf->pcicf_function != pa->pa_function) 234 return (0); 235 236 return ((*cf->cf_attach->ca_match)(parent, match, aux)); 237 } 238 239 int 240 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 241 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 242 { 243 pci_chipset_tag_t pc = sc->sc_pc; 244 struct pci_attach_args pa; 245 struct pci_dev *pd; 246 struct device *dev; 247 pcireg_t id, csr, class, intr, bhlcr; 248 int ret, pin, bus, device, function; 249 250 pci_decompose_tag(pc, tag, &bus, &device, &function); 251 252 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 253 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 254 return (0); 255 256 id = pci_conf_read(pc, tag, PCI_ID_REG); 257 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 258 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 259 260 /* Invalid vendor ID value? */ 261 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 262 return (0); 263 /* XXX Not invalid, but we've done this ~forever. */ 264 if (PCI_VENDOR(id) == 0) 265 return (0); 266 267 pa.pa_iot = sc->sc_iot; 268 pa.pa_memt = sc->sc_memt; 269 pa.pa_dmat = sc->sc_dmat; 270 pa.pa_pc = pc; 271 pa.pa_domain = sc->sc_domain; 272 pa.pa_bus = bus; 273 pa.pa_device = device; 274 pa.pa_function = function; 275 pa.pa_tag = tag; 276 pa.pa_id = id; 277 pa.pa_class = class; 278 pa.pa_bridgetag = sc->sc_bridgetag; 279 280 /* This is a simplification of the NetBSD code. 281 We don't support turning off I/O or memory 282 on broken hardware. <csapuntz@stanford.edu> */ 283 pa.pa_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 284 285 #ifdef __i386__ 286 /* 287 * on i386 we really need to know the device tag 288 * and not the pci bridge tag, in intr_map 289 * to be able to program the device and the 290 * pci interrupt router. 291 */ 292 pa.pa_intrtag = tag; 293 pa.pa_intrswiz = 0; 294 #else 295 if (sc->sc_bridgetag == NULL) { 296 pa.pa_intrswiz = 0; 297 pa.pa_intrtag = tag; 298 } else { 299 pa.pa_intrswiz = sc->sc_intrswiz + device; 300 pa.pa_intrtag = sc->sc_intrtag; 301 } 302 #endif 303 304 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 305 306 pin = PCI_INTERRUPT_PIN(intr); 307 pa.pa_rawintrpin = pin; 308 if (pin == PCI_INTERRUPT_PIN_NONE) { 309 /* no interrupt */ 310 pa.pa_intrpin = 0; 311 } else { 312 /* 313 * swizzle it based on the number of busses we're 314 * behind and our device number. 315 */ 316 pa.pa_intrpin = /* XXX */ 317 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 318 } 319 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 320 321 if (match != NULL) { 322 ret = (*match)(&pa); 323 if (ret != 0 && pap != NULL) 324 *pap = pa; 325 } else { 326 if ((dev = config_found_sm(&sc->sc_dev, &pa, pciprint, 327 pcisubmatch))) { 328 pcireg_t reg; 329 330 /* skip header type != 0 */ 331 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 332 if (PCI_HDRTYPE_TYPE(reg) != 0) 333 return(0); 334 if (pci_get_capability(pc, tag, 335 PCI_CAP_PWRMGMT, NULL, NULL) == 0) 336 return(0); 337 if (!(pd = malloc(sizeof *pd, M_DEVBUF, 338 M_NOWAIT))) 339 return(0); 340 pd->pd_tag = tag; 341 pd->pd_dev = dev; 342 LIST_INSERT_HEAD(&sc->sc_devs, pd, pd_next); 343 } 344 } 345 346 return (ret); 347 } 348 349 int 350 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 351 int *offset, pcireg_t *value) 352 { 353 pcireg_t reg; 354 unsigned int ofs; 355 356 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 357 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 358 return (0); 359 360 /* Determine the Capability List Pointer register to start with. */ 361 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 362 switch (PCI_HDRTYPE_TYPE(reg)) { 363 case 0: /* standard device header */ 364 ofs = PCI_CAPLISTPTR_REG; 365 break; 366 case 2: /* PCI-CardBus Bridge header */ 367 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 368 break; 369 default: 370 return (0); 371 } 372 373 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 374 while (ofs != 0) { 375 #ifdef DIAGNOSTIC 376 if ((ofs & 3) || (ofs < 0x40)) 377 panic("pci_get_capability"); 378 #endif 379 reg = pci_conf_read(pc, tag, ofs); 380 if (PCI_CAPLIST_CAP(reg) == capid) { 381 if (offset) 382 *offset = ofs; 383 if (value) 384 *value = reg; 385 return (1); 386 } 387 ofs = PCI_CAPLIST_NEXT(reg); 388 } 389 390 return (0); 391 } 392 393 int 394 pci_find_device(struct pci_attach_args *pa, 395 int (*match)(struct pci_attach_args *)) 396 { 397 extern struct cfdriver pci_cd; 398 struct device *pcidev; 399 int i; 400 401 for (i = 0; i < pci_cd.cd_ndevs; i++) { 402 pcidev = pci_cd.cd_devs[i]; 403 if (pcidev != NULL && 404 pci_enumerate_bus((struct pci_softc *)pcidev, 405 match, pa) != 0) 406 return (1); 407 } 408 return (0); 409 } 410 411 #ifndef PCI_MACHDEP_ENUMERATE_BUS 412 /* 413 * Generic PCI bus enumeration routine. Used unless machine-dependent 414 * code needs to provide something else. 415 */ 416 int 417 pci_enumerate_bus(struct pci_softc *sc, 418 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 419 { 420 pci_chipset_tag_t pc = sc->sc_pc; 421 int device, function, nfunctions, ret; 422 const struct pci_quirkdata *qd; 423 pcireg_t id, bhlcr; 424 pcitag_t tag; 425 426 for (device = 0; device < sc->sc_maxndevs; device++) { 427 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 428 429 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 430 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 431 continue; 432 433 id = pci_conf_read(pc, tag, PCI_ID_REG); 434 435 /* Invalid vendor ID value? */ 436 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 437 continue; 438 /* XXX Not invalid, but we've done this ~forever. */ 439 if (PCI_VENDOR(id) == 0) 440 continue; 441 442 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 443 444 if (qd != NULL && 445 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 446 nfunctions = 8; 447 else if (qd != NULL && 448 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 449 nfunctions = 1; 450 else 451 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 452 453 for (function = 0; function < nfunctions; function++) { 454 tag = pci_make_tag(pc, sc->sc_bus, device, function); 455 ret = pci_probe_device(sc, tag, match, pap); 456 if (match != NULL && ret != 0) 457 return (ret); 458 } 459 } 460 461 return (0); 462 } 463 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 464 465 int 466 pci_matchbyid(struct pci_attach_args *pa, const struct pci_matchid *ids, 467 int nent) 468 { 469 const struct pci_matchid *pm; 470 int i; 471 472 for (i = 0, pm = ids; i < nent; i++, pm++) 473 if (PCI_VENDOR(pa->pa_id) == pm->pm_vid && 474 PCI_PRODUCT(pa->pa_id) == pm->pm_pid) 475 return (1); 476 return (0); 477 } 478 479 #ifdef USER_PCICONF 480 /* 481 * This is the user interface to PCI configuration space. 482 */ 483 484 #include <sys/pciio.h> 485 #include <sys/fcntl.h> 486 487 #ifdef DEBUG 488 #define PCIDEBUG(x) printf x 489 #else 490 #define PCIDEBUG(x) 491 #endif 492 493 494 int pciopen(dev_t dev, int oflags, int devtype, struct proc *p); 495 int pciclose(dev_t dev, int flag, int devtype, struct proc *p); 496 int pciioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p); 497 498 int 499 pciopen(dev_t dev, int oflags, int devtype, struct proc *p) 500 { 501 PCIDEBUG(("pciopen ndevs: %d\n" , pci_cd.cd_ndevs)); 502 503 if (minor(dev) >= pci_ndomains) { 504 return ENXIO; 505 } 506 507 #ifndef APERTURE 508 if ((oflags & FWRITE) && securelevel > 0) { 509 return EPERM; 510 } 511 #else 512 if ((oflags & FWRITE) && securelevel > 0 && allowaperture == 0) { 513 return EPERM; 514 } 515 #endif 516 return (0); 517 } 518 519 int 520 pciclose(dev_t dev, int flag, int devtype, struct proc *p) 521 { 522 PCIDEBUG(("pciclose\n")); 523 return (0); 524 } 525 526 int 527 pciioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 528 { 529 struct pci_io *io; 530 int i, error; 531 pcitag_t tag; 532 struct pci_softc *pci = NULL; 533 pci_chipset_tag_t pc; 534 535 io = (struct pci_io *)data; 536 537 PCIDEBUG(("pciioctl cmd %s", cmd == PCIOCREAD ? "pciocread" 538 : cmd == PCIOCWRITE ? "pciocwrite" : "unknown")); 539 PCIDEBUG((" bus %d dev %d func %d reg %x\n", io->pi_sel.pc_bus, 540 io->pi_sel.pc_dev, io->pi_sel.pc_func, io->pi_reg)); 541 542 for (i = 0; i < pci_cd.cd_ndevs; i++) { 543 pci = pci_cd.cd_devs[i]; 544 if (pci != NULL && pci->sc_domain == minor(dev) && 545 pci->sc_bus == io->pi_sel.pc_bus) 546 break; 547 } 548 if (pci != NULL && pci->sc_bus == io->pi_sel.pc_bus) { 549 pc = pci->sc_pc; 550 } else { 551 error = ENXIO; 552 goto done; 553 } 554 /* Check bounds */ 555 if (pci->sc_bus >= 256 || 556 io->pi_sel.pc_dev >= pci_bus_maxdevs(pc, pci->sc_bus) || 557 io->pi_sel.pc_func >= 8) { 558 error = EINVAL; 559 goto done; 560 } 561 562 tag = pci_make_tag(pc, io->pi_sel.pc_bus, io->pi_sel.pc_dev, 563 io->pi_sel.pc_func); 564 565 switch(cmd) { 566 case PCIOCGETCONF: 567 error = ENODEV; 568 break; 569 570 case PCIOCREAD: 571 switch(io->pi_width) { 572 case 4: 573 /* Make sure the register is properly aligned */ 574 if (io->pi_reg & 0x3) 575 return EINVAL; 576 io->pi_data = pci_conf_read(pc, tag, io->pi_reg); 577 error = 0; 578 break; 579 default: 580 error = ENODEV; 581 break; 582 } 583 break; 584 585 case PCIOCWRITE: 586 if (!(flag & FWRITE)) 587 return EPERM; 588 589 switch(io->pi_width) { 590 case 4: 591 /* Make sure the register is properly aligned */ 592 if (io->pi_reg & 0x3) 593 return EINVAL; 594 pci_conf_write(pc, tag, io->pi_reg, io->pi_data); 595 error = 0; 596 break; 597 default: 598 error = ENODEV; 599 break; 600 } 601 break; 602 603 default: 604 error = ENOTTY; 605 break; 606 } 607 done: 608 return (error); 609 } 610 611 #endif 612