1 /* $OpenBSD: radeon_i2c.c,v 1.3 2014/02/15 12:40:08 jsg Exp $ */ 2 /* 3 * Copyright 2007-8 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 */ 27 28 #include <dev/pci/drm/drmP.h> 29 #include <dev/pci/drm/drm_edid.h> 30 #include <dev/pci/drm/radeon_drm.h> 31 #include "radeon.h" 32 #include "atom.h" 33 34 #include <dev/i2c/i2cvar.h> 35 #include <dev/i2c/i2c_bitbang.h> 36 37 #ifdef notyet 38 extern int radeon_atom_hw_i2c_xfer(struct i2c_controller *i2c_adap, 39 struct i2c_msg *msgs, int num); 40 #endif 41 extern u32 radeon_atom_hw_i2c_func(struct i2c_controller *adap); 42 43 int pre_xfer(void *); 44 void post_xfer(void *); 45 int get_clock(void *); 46 int get_data(void *); 47 void set_clock(void *, int); 48 void set_data(void *, int); 49 u32 radeon_get_i2c_prescale(struct radeon_device *); 50 51 /** 52 * radeon_ddc_probe 53 * 54 */ 55 bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux) 56 { 57 u8 out = 0x0; 58 u8 buf[8]; 59 int ret; 60 61 /* on hw with routers, select right port */ 62 if (radeon_connector->router.ddc_valid) 63 radeon_router_select_ddc_port(radeon_connector); 64 65 if (use_aux) { 66 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 67 iic_acquire_bus(&dig->dp_i2c_bus->adapter, 0); 68 ret = iic_exec(&dig->dp_i2c_bus->adapter, I2C_OP_READ_WITH_STOP, DDC_ADDR, &out, 1, buf, 8, 0); 69 iic_release_bus(&dig->dp_i2c_bus->adapter, 0); 70 } else { 71 iic_acquire_bus(&radeon_connector->ddc_bus->adapter, 0); 72 ret = iic_exec(&radeon_connector->ddc_bus->adapter, I2C_OP_READ_WITH_STOP, DDC_ADDR, &out, 1, buf, 8, 0); 73 iic_release_bus(&radeon_connector->ddc_bus->adapter, 0); 74 } 75 76 if (ret) 77 /* Couldn't find an accessible DDC on this connector */ 78 return false; 79 /* Probe also for valid EDID header 80 * EDID header starts with: 81 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 82 * Only the first 6 bytes must be valid as 83 * drm_edid_block_valid() can fix the last 2 bytes */ 84 if (drm_edid_header_is_valid(buf) < 6) { 85 /* Couldn't find an accessible EDID on this 86 * connector */ 87 return false; 88 } 89 return true; 90 } 91 92 /* bit banging i2c */ 93 94 int 95 pre_xfer(void *cookie) 96 { 97 struct radeon_i2c_chan *i2c = cookie; 98 struct radeon_device *rdev = i2c->dev->dev_private; 99 struct radeon_i2c_bus_rec *rec = &i2c->rec; 100 uint32_t temp; 101 102 /* RV410 appears to have a bug where the hw i2c in reset 103 * holds the i2c port in a bad state - switch hw i2c away before 104 * doing DDC - do this for all r200s/r300s/r400s for safety sake 105 */ 106 if (rec->hw_capable) { 107 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) { 108 u32 reg; 109 110 if (rdev->family >= CHIP_RV350) 111 reg = RADEON_GPIO_MONID; 112 else if ((rdev->family == CHIP_R300) || 113 (rdev->family == CHIP_R350)) 114 reg = RADEON_GPIO_DVI_DDC; 115 else 116 reg = RADEON_GPIO_CRT2_DDC; 117 118 rw_enter_write(&rdev->dc_hw_i2c_rwlock); 119 if (rec->a_clk_reg == reg) { 120 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 121 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1))); 122 } else { 123 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 124 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3))); 125 } 126 rw_exit_write(&rdev->dc_hw_i2c_rwlock); 127 } 128 } 129 130 /* switch the pads to ddc mode */ 131 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) { 132 temp = RREG32(rec->mask_clk_reg); 133 temp &= ~(1 << 16); 134 WREG32(rec->mask_clk_reg, temp); 135 } 136 137 /* clear the output pin values */ 138 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; 139 WREG32(rec->a_clk_reg, temp); 140 141 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; 142 WREG32(rec->a_data_reg, temp); 143 144 /* set the pins to input */ 145 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 146 WREG32(rec->en_clk_reg, temp); 147 148 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 149 WREG32(rec->en_data_reg, temp); 150 151 /* mask the gpio pins for software use */ 152 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; 153 WREG32(rec->mask_clk_reg, temp); 154 temp = RREG32(rec->mask_clk_reg); 155 156 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; 157 WREG32(rec->mask_data_reg, temp); 158 temp = RREG32(rec->mask_data_reg); 159 160 return 0; 161 } 162 163 void 164 post_xfer(void *cookie) 165 { 166 struct radeon_i2c_chan *i2c = cookie; 167 struct radeon_device *rdev = i2c->dev->dev_private; 168 struct radeon_i2c_bus_rec *rec = &i2c->rec; 169 uint32_t temp; 170 171 /* unmask the gpio pins for software use */ 172 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; 173 WREG32(rec->mask_clk_reg, temp); 174 temp = RREG32(rec->mask_clk_reg); 175 176 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask; 177 WREG32(rec->mask_data_reg, temp); 178 temp = RREG32(rec->mask_data_reg); 179 } 180 181 int 182 get_clock(void *i2c_priv) 183 { 184 struct radeon_i2c_chan *i2c = i2c_priv; 185 struct radeon_device *rdev = i2c->dev->dev_private; 186 struct radeon_i2c_bus_rec *rec = &i2c->rec; 187 uint32_t val; 188 189 /* read the value off the pin */ 190 val = RREG32(rec->y_clk_reg); 191 val &= rec->y_clk_mask; 192 193 return (val != 0); 194 } 195 196 197 int 198 get_data(void *i2c_priv) 199 { 200 struct radeon_i2c_chan *i2c = i2c_priv; 201 struct radeon_device *rdev = i2c->dev->dev_private; 202 struct radeon_i2c_bus_rec *rec = &i2c->rec; 203 uint32_t val; 204 205 /* read the value off the pin */ 206 val = RREG32(rec->y_data_reg); 207 val &= rec->y_data_mask; 208 209 return (val != 0); 210 } 211 212 void 213 set_clock(void *i2c_priv, int clock) 214 { 215 struct radeon_i2c_chan *i2c = i2c_priv; 216 struct radeon_device *rdev = i2c->dev->dev_private; 217 struct radeon_i2c_bus_rec *rec = &i2c->rec; 218 uint32_t val; 219 220 /* set pin direction */ 221 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 222 val |= clock ? 0 : rec->en_clk_mask; 223 WREG32(rec->en_clk_reg, val); 224 } 225 226 void 227 set_data(void *i2c_priv, int data) 228 { 229 struct radeon_i2c_chan *i2c = i2c_priv; 230 struct radeon_device *rdev = i2c->dev->dev_private; 231 struct radeon_i2c_bus_rec *rec = &i2c->rec; 232 uint32_t val; 233 234 /* set pin direction */ 235 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 236 val |= data ? 0 : rec->en_data_mask; 237 WREG32(rec->en_data_reg, val); 238 } 239 240 void radeon_bb_set_bits(void *, uint32_t); 241 void radeon_bb_set_dir(void *, uint32_t); 242 uint32_t radeon_bb_read_bits(void *); 243 244 int radeon_acquire_bus(void *, int); 245 void radeon_release_bus(void *, int); 246 int radeon_send_start(void *, int); 247 int radeon_send_stop(void *, int); 248 int radeon_initiate_xfer(void *, i2c_addr_t, int); 249 int radeon_read_byte(void *, u_int8_t *, int); 250 int radeon_write_byte(void *, u_int8_t, int); 251 252 #define RADEON_BB_SDA (1 << I2C_BIT_SDA) 253 #define RADEON_BB_SCL (1 << I2C_BIT_SCL) 254 255 struct i2c_bitbang_ops radeon_bbops = { 256 radeon_bb_set_bits, 257 radeon_bb_set_dir, 258 radeon_bb_read_bits, 259 { RADEON_BB_SDA, RADEON_BB_SCL, 0, 0 } 260 }; 261 262 void 263 radeon_bb_set_bits(void *cookie, uint32_t bits) 264 { 265 set_clock(cookie, bits & RADEON_BB_SCL); 266 set_data(cookie, bits & RADEON_BB_SDA); 267 } 268 269 void 270 radeon_bb_set_dir(void *cookie, uint32_t bits) 271 { 272 } 273 274 uint32_t 275 radeon_bb_read_bits(void *cookie) 276 { 277 uint32_t bits = 0; 278 279 if (get_clock(cookie)) 280 bits |= RADEON_BB_SCL; 281 if (get_data(cookie)) 282 bits |= RADEON_BB_SDA; 283 284 return bits; 285 } 286 287 int 288 radeon_acquire_bus(void *cookie, int flags) 289 { 290 pre_xfer(cookie); 291 return (0); 292 } 293 294 void 295 radeon_release_bus(void *cookie, int flags) 296 { 297 post_xfer(cookie); 298 } 299 300 int 301 radeon_send_start(void *cookie, int flags) 302 { 303 return (i2c_bitbang_send_start(cookie, flags, &radeon_bbops)); 304 } 305 306 int 307 radeon_send_stop(void *cookie, int flags) 308 { 309 return (i2c_bitbang_send_stop(cookie, flags, &radeon_bbops)); 310 } 311 312 int 313 radeon_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 314 { 315 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, &radeon_bbops)); 316 } 317 318 int 319 radeon_read_byte(void *cookie, u_int8_t *bytep, int flags) 320 { 321 return (i2c_bitbang_read_byte(cookie, bytep, flags, &radeon_bbops)); 322 } 323 324 int 325 radeon_write_byte(void *cookie, u_int8_t byte, int flags) 326 { 327 return (i2c_bitbang_write_byte(cookie, byte, flags, &radeon_bbops)); 328 } 329 330 /* hw i2c */ 331 332 u32 333 radeon_get_i2c_prescale(struct radeon_device *rdev) 334 { 335 u32 sclk = rdev->pm.current_sclk; 336 u32 prescale = 0; 337 u32 nm; 338 u8 n, m, loop; 339 int i2c_clock; 340 341 switch (rdev->family) { 342 case CHIP_R100: 343 case CHIP_RV100: 344 case CHIP_RS100: 345 case CHIP_RV200: 346 case CHIP_RS200: 347 case CHIP_R200: 348 case CHIP_RV250: 349 case CHIP_RS300: 350 case CHIP_RV280: 351 case CHIP_R300: 352 case CHIP_R350: 353 case CHIP_RV350: 354 i2c_clock = 60; 355 nm = (sclk * 10) / (i2c_clock * 4); 356 for (loop = 1; loop < 255; loop++) { 357 if ((nm / loop) < loop) 358 break; 359 } 360 n = loop - 1; 361 m = loop - 2; 362 prescale = m | (n << 8); 363 break; 364 case CHIP_RV380: 365 case CHIP_RS400: 366 case CHIP_RS480: 367 case CHIP_R420: 368 case CHIP_R423: 369 case CHIP_RV410: 370 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 371 break; 372 case CHIP_RS600: 373 case CHIP_RS690: 374 case CHIP_RS740: 375 /* todo */ 376 break; 377 case CHIP_RV515: 378 case CHIP_R520: 379 case CHIP_RV530: 380 case CHIP_RV560: 381 case CHIP_RV570: 382 case CHIP_R580: 383 i2c_clock = 50; 384 if (rdev->family == CHIP_R520) 385 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock)); 386 else 387 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 388 break; 389 case CHIP_R600: 390 case CHIP_RV610: 391 case CHIP_RV630: 392 case CHIP_RV670: 393 /* todo */ 394 break; 395 case CHIP_RV620: 396 case CHIP_RV635: 397 case CHIP_RS780: 398 case CHIP_RS880: 399 case CHIP_RV770: 400 case CHIP_RV730: 401 case CHIP_RV710: 402 case CHIP_RV740: 403 /* todo */ 404 break; 405 case CHIP_CEDAR: 406 case CHIP_REDWOOD: 407 case CHIP_JUNIPER: 408 case CHIP_CYPRESS: 409 case CHIP_HEMLOCK: 410 /* todo */ 411 break; 412 default: 413 DRM_ERROR("i2c: unhandled radeon chip\n"); 414 break; 415 } 416 return prescale; 417 } 418 419 420 /* hw i2c engine for r1xx-4xx hardware 421 * hw can buffer up to 15 bytes 422 */ 423 #ifdef notyet 424 static int r100_hw_i2c_xfer(struct i2c_controller *i2c_adap, 425 struct i2c_msg *msgs, int num) 426 { 427 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 428 struct radeon_device *rdev = i2c->dev->dev_private; 429 struct radeon_i2c_bus_rec *rec = &i2c->rec; 430 struct i2c_msg *p; 431 int i, j, k, ret = num; 432 u32 prescale; 433 u32 i2c_cntl_0, i2c_cntl_1, i2c_data; 434 u32 tmp, reg; 435 436 rw_enter_write(&rdev->dc_hw_i2c_rwlock); 437 /* take the pm lock since we need a constant sclk */ 438 rw_enter_write(&rdev->pm.rwlock); 439 440 prescale = radeon_get_i2c_prescale(rdev); 441 442 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) | 443 RADEON_I2C_DRIVE_EN | 444 RADEON_I2C_START | 445 RADEON_I2C_STOP | 446 RADEON_I2C_GO); 447 448 if (rdev->is_atom_bios) { 449 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 450 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 451 } 452 453 if (rec->mm_i2c) { 454 i2c_cntl_0 = RADEON_I2C_CNTL_0; 455 i2c_cntl_1 = RADEON_I2C_CNTL_1; 456 i2c_data = RADEON_I2C_DATA; 457 } else { 458 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0; 459 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1; 460 i2c_data = RADEON_DVI_I2C_DATA; 461 462 switch (rdev->family) { 463 case CHIP_R100: 464 case CHIP_RV100: 465 case CHIP_RS100: 466 case CHIP_RV200: 467 case CHIP_RS200: 468 case CHIP_RS300: 469 switch (rec->mask_clk_reg) { 470 case RADEON_GPIO_DVI_DDC: 471 /* no gpio select bit */ 472 break; 473 default: 474 DRM_ERROR("gpio not supported with hw i2c\n"); 475 ret = -EINVAL; 476 goto done; 477 } 478 break; 479 case CHIP_R200: 480 /* only bit 4 on r200 */ 481 switch (rec->mask_clk_reg) { 482 case RADEON_GPIO_DVI_DDC: 483 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 484 break; 485 case RADEON_GPIO_MONID: 486 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 487 break; 488 default: 489 DRM_ERROR("gpio not supported with hw i2c\n"); 490 ret = -EINVAL; 491 goto done; 492 } 493 break; 494 case CHIP_RV250: 495 case CHIP_RV280: 496 /* bits 3 and 4 */ 497 switch (rec->mask_clk_reg) { 498 case RADEON_GPIO_DVI_DDC: 499 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 500 break; 501 case RADEON_GPIO_VGA_DDC: 502 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 503 break; 504 case RADEON_GPIO_CRT2_DDC: 505 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 506 break; 507 default: 508 DRM_ERROR("gpio not supported with hw i2c\n"); 509 ret = -EINVAL; 510 goto done; 511 } 512 break; 513 case CHIP_R300: 514 case CHIP_R350: 515 /* only bit 4 on r300/r350 */ 516 switch (rec->mask_clk_reg) { 517 case RADEON_GPIO_VGA_DDC: 518 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 519 break; 520 case RADEON_GPIO_DVI_DDC: 521 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 522 break; 523 default: 524 DRM_ERROR("gpio not supported with hw i2c\n"); 525 ret = -EINVAL; 526 goto done; 527 } 528 break; 529 case CHIP_RV350: 530 case CHIP_RV380: 531 case CHIP_R420: 532 case CHIP_R423: 533 case CHIP_RV410: 534 case CHIP_RS400: 535 case CHIP_RS480: 536 /* bits 3 and 4 */ 537 switch (rec->mask_clk_reg) { 538 case RADEON_GPIO_VGA_DDC: 539 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 540 break; 541 case RADEON_GPIO_DVI_DDC: 542 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 543 break; 544 case RADEON_GPIO_MONID: 545 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 546 break; 547 default: 548 DRM_ERROR("gpio not supported with hw i2c\n"); 549 ret = -EINVAL; 550 goto done; 551 } 552 break; 553 default: 554 DRM_ERROR("unsupported asic\n"); 555 ret = -EINVAL; 556 goto done; 557 break; 558 } 559 } 560 561 /* check for bus probe */ 562 p = &msgs[0]; 563 if ((num == 1) && (p->len == 0)) { 564 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 565 RADEON_I2C_NACK | 566 RADEON_I2C_HALT | 567 RADEON_I2C_SOFT_RST)); 568 WREG32(i2c_data, (p->addr << 1) & 0xff); 569 WREG32(i2c_data, 0); 570 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 571 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 572 RADEON_I2C_EN | 573 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 574 WREG32(i2c_cntl_0, reg); 575 for (k = 0; k < 32; k++) { 576 udelay(10); 577 tmp = RREG32(i2c_cntl_0); 578 if (tmp & RADEON_I2C_GO) 579 continue; 580 tmp = RREG32(i2c_cntl_0); 581 if (tmp & RADEON_I2C_DONE) 582 break; 583 else { 584 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 585 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 586 ret = -EIO; 587 goto done; 588 } 589 } 590 goto done; 591 } 592 593 for (i = 0; i < num; i++) { 594 p = &msgs[i]; 595 for (j = 0; j < p->len; j++) { 596 if (p->flags & I2C_M_RD) { 597 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 598 RADEON_I2C_NACK | 599 RADEON_I2C_HALT | 600 RADEON_I2C_SOFT_RST)); 601 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1); 602 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 603 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 604 RADEON_I2C_EN | 605 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 606 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE); 607 for (k = 0; k < 32; k++) { 608 udelay(10); 609 tmp = RREG32(i2c_cntl_0); 610 if (tmp & RADEON_I2C_GO) 611 continue; 612 tmp = RREG32(i2c_cntl_0); 613 if (tmp & RADEON_I2C_DONE) 614 break; 615 else { 616 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 617 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 618 ret = -EIO; 619 goto done; 620 } 621 } 622 p->buf[j] = RREG32(i2c_data) & 0xff; 623 } else { 624 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 625 RADEON_I2C_NACK | 626 RADEON_I2C_HALT | 627 RADEON_I2C_SOFT_RST)); 628 WREG32(i2c_data, (p->addr << 1) & 0xff); 629 WREG32(i2c_data, p->buf[j]); 630 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 631 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 632 RADEON_I2C_EN | 633 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 634 WREG32(i2c_cntl_0, reg); 635 for (k = 0; k < 32; k++) { 636 udelay(10); 637 tmp = RREG32(i2c_cntl_0); 638 if (tmp & RADEON_I2C_GO) 639 continue; 640 tmp = RREG32(i2c_cntl_0); 641 if (tmp & RADEON_I2C_DONE) 642 break; 643 else { 644 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 645 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 646 ret = -EIO; 647 goto done; 648 } 649 } 650 } 651 } 652 } 653 654 done: 655 WREG32(i2c_cntl_0, 0); 656 WREG32(i2c_cntl_1, 0); 657 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 658 RADEON_I2C_NACK | 659 RADEON_I2C_HALT | 660 RADEON_I2C_SOFT_RST)); 661 662 if (rdev->is_atom_bios) { 663 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 664 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 665 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 666 } 667 668 rw_exit_write(&rdev->pm.rwlock); 669 rw_exit_write(&rdev->dc_hw_i2c_rwlock); 670 671 return ret; 672 } 673 674 /* hw i2c engine for r5xx hardware 675 * hw can buffer up to 15 bytes 676 */ 677 static int r500_hw_i2c_xfer(struct i2c_controller *i2c_adap, 678 struct i2c_msg *msgs, int num) 679 { 680 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 681 struct radeon_device *rdev = i2c->dev->dev_private; 682 struct radeon_i2c_bus_rec *rec = &i2c->rec; 683 struct i2c_msg *p; 684 int i, j, remaining, current_count, buffer_offset, ret = num; 685 u32 prescale; 686 u32 tmp, reg; 687 u32 saved1, saved2; 688 689 rw_enter_write(&rdev->dc_hw_i2c_rwlock); 690 /* take the pm lock since we need a constant sclk */ 691 rw_enter_write(&rdev->pm.rwlock); 692 693 prescale = radeon_get_i2c_prescale(rdev); 694 695 /* clear gpio mask bits */ 696 tmp = RREG32(rec->mask_clk_reg); 697 tmp &= ~rec->mask_clk_mask; 698 WREG32(rec->mask_clk_reg, tmp); 699 tmp = RREG32(rec->mask_clk_reg); 700 701 tmp = RREG32(rec->mask_data_reg); 702 tmp &= ~rec->mask_data_mask; 703 WREG32(rec->mask_data_reg, tmp); 704 tmp = RREG32(rec->mask_data_reg); 705 706 /* clear pin values */ 707 tmp = RREG32(rec->a_clk_reg); 708 tmp &= ~rec->a_clk_mask; 709 WREG32(rec->a_clk_reg, tmp); 710 tmp = RREG32(rec->a_clk_reg); 711 712 tmp = RREG32(rec->a_data_reg); 713 tmp &= ~rec->a_data_mask; 714 WREG32(rec->a_data_reg, tmp); 715 tmp = RREG32(rec->a_data_reg); 716 717 /* set the pins to input */ 718 tmp = RREG32(rec->en_clk_reg); 719 tmp &= ~rec->en_clk_mask; 720 WREG32(rec->en_clk_reg, tmp); 721 tmp = RREG32(rec->en_clk_reg); 722 723 tmp = RREG32(rec->en_data_reg); 724 tmp &= ~rec->en_data_mask; 725 WREG32(rec->en_data_reg, tmp); 726 tmp = RREG32(rec->en_data_reg); 727 728 /* */ 729 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 730 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 731 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1); 732 saved2 = RREG32(0x494); 733 WREG32(0x494, saved2 | 0x1); 734 735 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C); 736 for (i = 0; i < 50; i++) { 737 udelay(1); 738 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C) 739 break; 740 } 741 if (i == 50) { 742 DRM_ERROR("failed to get i2c bus\n"); 743 ret = -EBUSY; 744 goto done; 745 } 746 747 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN; 748 switch (rec->mask_clk_reg) { 749 case AVIVO_DC_GPIO_DDC1_MASK: 750 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1); 751 break; 752 case AVIVO_DC_GPIO_DDC2_MASK: 753 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2); 754 break; 755 case AVIVO_DC_GPIO_DDC3_MASK: 756 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3); 757 break; 758 default: 759 DRM_ERROR("gpio not supported with hw i2c\n"); 760 ret = -EINVAL; 761 goto done; 762 } 763 764 /* check for bus probe */ 765 p = &msgs[0]; 766 if ((num == 1) && (p->len == 0)) { 767 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 768 AVIVO_DC_I2C_NACK | 769 AVIVO_DC_I2C_HALT)); 770 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 771 udelay(1); 772 WREG32(AVIVO_DC_I2C_RESET, 0); 773 774 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); 775 WREG32(AVIVO_DC_I2C_DATA, 0); 776 777 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 778 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 779 AVIVO_DC_I2C_DATA_COUNT(1) | 780 (prescale << 16))); 781 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 782 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 783 for (j = 0; j < 200; j++) { 784 udelay(50); 785 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 786 if (tmp & AVIVO_DC_I2C_GO) 787 continue; 788 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 789 if (tmp & AVIVO_DC_I2C_DONE) 790 break; 791 else { 792 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 793 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 794 ret = -EIO; 795 goto done; 796 } 797 } 798 goto done; 799 } 800 801 for (i = 0; i < num; i++) { 802 p = &msgs[i]; 803 remaining = p->len; 804 buffer_offset = 0; 805 if (p->flags & I2C_M_RD) { 806 while (remaining) { 807 if (remaining > 15) 808 current_count = 15; 809 else 810 current_count = remaining; 811 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 812 AVIVO_DC_I2C_NACK | 813 AVIVO_DC_I2C_HALT)); 814 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 815 udelay(1); 816 WREG32(AVIVO_DC_I2C_RESET, 0); 817 818 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1); 819 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 820 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 821 AVIVO_DC_I2C_DATA_COUNT(current_count) | 822 (prescale << 16))); 823 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE); 824 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 825 for (j = 0; j < 200; j++) { 826 udelay(50); 827 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 828 if (tmp & AVIVO_DC_I2C_GO) 829 continue; 830 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 831 if (tmp & AVIVO_DC_I2C_DONE) 832 break; 833 else { 834 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 835 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 836 ret = -EIO; 837 goto done; 838 } 839 } 840 for (j = 0; j < current_count; j++) 841 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff; 842 remaining -= current_count; 843 buffer_offset += current_count; 844 } 845 } else { 846 while (remaining) { 847 if (remaining > 15) 848 current_count = 15; 849 else 850 current_count = remaining; 851 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 852 AVIVO_DC_I2C_NACK | 853 AVIVO_DC_I2C_HALT)); 854 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 855 udelay(1); 856 WREG32(AVIVO_DC_I2C_RESET, 0); 857 858 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); 859 for (j = 0; j < current_count; j++) 860 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]); 861 862 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 863 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 864 AVIVO_DC_I2C_DATA_COUNT(current_count) | 865 (prescale << 16))); 866 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 867 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 868 for (j = 0; j < 200; j++) { 869 udelay(50); 870 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 871 if (tmp & AVIVO_DC_I2C_GO) 872 continue; 873 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 874 if (tmp & AVIVO_DC_I2C_DONE) 875 break; 876 else { 877 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 878 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 879 ret = -EIO; 880 goto done; 881 } 882 } 883 remaining -= current_count; 884 buffer_offset += current_count; 885 } 886 } 887 } 888 889 done: 890 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 891 AVIVO_DC_I2C_NACK | 892 AVIVO_DC_I2C_HALT)); 893 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 894 udelay(1); 895 WREG32(AVIVO_DC_I2C_RESET, 0); 896 897 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C); 898 WREG32(AVIVO_DC_I2C_CONTROL1, saved1); 899 WREG32(0x494, saved2); 900 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 901 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 902 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 903 904 rw_exit_write(&rdev->pm.rwlock); 905 rw_exit_write(&rdev->dc_hw_i2c_rwlock); 906 907 return ret; 908 } 909 910 static int radeon_hw_i2c_xfer(struct i2c_controller *i2c_adap, 911 struct i2c_msg *msgs, int num) 912 { 913 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 914 struct radeon_device *rdev = i2c->dev->dev_private; 915 struct radeon_i2c_bus_rec *rec = &i2c->rec; 916 int ret = 0; 917 918 switch (rdev->family) { 919 case CHIP_R100: 920 case CHIP_RV100: 921 case CHIP_RS100: 922 case CHIP_RV200: 923 case CHIP_RS200: 924 case CHIP_R200: 925 case CHIP_RV250: 926 case CHIP_RS300: 927 case CHIP_RV280: 928 case CHIP_R300: 929 case CHIP_R350: 930 case CHIP_RV350: 931 case CHIP_RV380: 932 case CHIP_R420: 933 case CHIP_R423: 934 case CHIP_RV410: 935 case CHIP_RS400: 936 case CHIP_RS480: 937 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); 938 break; 939 case CHIP_RS600: 940 case CHIP_RS690: 941 case CHIP_RS740: 942 /* XXX fill in hw i2c implementation */ 943 break; 944 case CHIP_RV515: 945 case CHIP_R520: 946 case CHIP_RV530: 947 case CHIP_RV560: 948 case CHIP_RV570: 949 case CHIP_R580: 950 if (rec->mm_i2c) 951 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); 952 else 953 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num); 954 break; 955 case CHIP_R600: 956 case CHIP_RV610: 957 case CHIP_RV630: 958 case CHIP_RV670: 959 /* XXX fill in hw i2c implementation */ 960 break; 961 case CHIP_RV620: 962 case CHIP_RV635: 963 case CHIP_RS780: 964 case CHIP_RS880: 965 case CHIP_RV770: 966 case CHIP_RV730: 967 case CHIP_RV710: 968 case CHIP_RV740: 969 /* XXX fill in hw i2c implementation */ 970 break; 971 case CHIP_CEDAR: 972 case CHIP_REDWOOD: 973 case CHIP_JUNIPER: 974 case CHIP_CYPRESS: 975 case CHIP_HEMLOCK: 976 /* XXX fill in hw i2c implementation */ 977 break; 978 default: 979 DRM_ERROR("i2c: unhandled radeon chip\n"); 980 ret = -EIO; 981 break; 982 } 983 984 return ret; 985 } 986 987 static u32 radeon_hw_i2c_func(struct i2c_controller *adap) 988 { 989 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 990 } 991 992 static const struct i2c_algorithm radeon_i2c_algo = { 993 .master_xfer = radeon_hw_i2c_xfer, 994 .functionality = radeon_hw_i2c_func, 995 }; 996 997 static const struct i2c_algorithm radeon_atom_i2c_algo = { 998 .master_xfer = radeon_atom_hw_i2c_xfer, 999 .functionality = radeon_atom_hw_i2c_func, 1000 }; 1001 #endif // notyet 1002 1003 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 1004 struct radeon_i2c_bus_rec *rec, 1005 const char *name) 1006 { 1007 struct radeon_device *rdev = dev->dev_private; 1008 struct radeon_i2c_chan *i2c; 1009 int ret = 0; 1010 1011 /* don't add the mm_i2c bus unless hw_i2c is enabled */ 1012 if (rec->mm_i2c && (radeon_hw_i2c == 0)) 1013 return NULL; 1014 1015 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL); 1016 if (i2c == NULL) 1017 return NULL; 1018 1019 i2c->rec = *rec; 1020 #ifdef notyet 1021 i2c->adapter.owner = THIS_MODULE; 1022 i2c->adapter.class = I2C_CLASS_DDC; 1023 i2c->adapter.dev.parent = &dev->pdev->dev; 1024 #else 1025 i2c->adapter.ic_cookie = i2c; 1026 i2c->adapter.ic_acquire_bus = radeon_acquire_bus; 1027 i2c->adapter.ic_release_bus = radeon_release_bus; 1028 i2c->adapter.ic_send_start = radeon_send_start; 1029 i2c->adapter.ic_send_stop = radeon_send_stop; 1030 i2c->adapter.ic_initiate_xfer = radeon_initiate_xfer; 1031 i2c->adapter.ic_read_byte = radeon_read_byte; 1032 i2c->adapter.ic_write_byte = radeon_write_byte; 1033 #endif 1034 i2c->dev = dev; 1035 #ifdef notyet 1036 i2c_set_adapdata(&i2c->adapter, i2c); 1037 #endif 1038 if (rec->mm_i2c || 1039 (rec->hw_capable && 1040 radeon_hw_i2c && 1041 ((rdev->family <= CHIP_RS480) || 1042 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) { 1043 /* set the radeon hw i2c adapter */ 1044 #ifdef notyet 1045 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 1046 "Radeon i2c hw bus %s", name); 1047 i2c->adapter.algo = &radeon_i2c_algo; 1048 ret = i2c_add_adapter(&i2c->adapter); 1049 #endif 1050 if (ret) { 1051 DRM_ERROR("Failed to register hw i2c %s\n", name); 1052 goto out_free; 1053 } 1054 } else if (rec->hw_capable && 1055 radeon_hw_i2c && 1056 ASIC_IS_DCE3(rdev)) { 1057 /* hw i2c using atom */ 1058 #ifdef notyet 1059 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 1060 "Radeon i2c hw bus %s", name); 1061 i2c->adapter.algo = &radeon_atom_i2c_algo; 1062 ret = i2c_add_adapter(&i2c->adapter); 1063 #endif 1064 if (ret) { 1065 DRM_ERROR("Failed to register hw i2c %s\n", name); 1066 goto out_free; 1067 } 1068 } else { 1069 /* set the radeon bit adapter */ 1070 #ifdef notyet 1071 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 1072 "Radeon i2c bit bus %s", name); 1073 i2c->adapter.algo_data = &i2c->algo.bit; 1074 i2c->algo.bit.pre_xfer = pre_xfer; 1075 i2c->algo.bit.post_xfer = post_xfer; 1076 i2c->algo.bit.setsda = set_data; 1077 i2c->algo.bit.setscl = set_clock; 1078 i2c->algo.bit.getsda = get_data; 1079 i2c->algo.bit.getscl = get_clock; 1080 i2c->algo.bit.udelay = 10; 1081 i2c->algo.bit.timeout = usecs_to_jiffies(2200); /* from VESA */ 1082 i2c->algo.bit.data = i2c; 1083 ret = i2c_bit_add_bus(&i2c->adapter); 1084 #endif 1085 if (ret) { 1086 DRM_ERROR("Failed to register bit i2c %s\n", name); 1087 goto out_free; 1088 } 1089 } 1090 1091 return i2c; 1092 out_free: 1093 kfree(i2c); 1094 return NULL; 1095 } 1096 1097 struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, 1098 struct radeon_i2c_bus_rec *rec, 1099 const char *name) 1100 { 1101 struct radeon_i2c_chan *i2c; 1102 int ret = 0; 1103 1104 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL); 1105 if (i2c == NULL) 1106 return NULL; 1107 1108 i2c->rec = *rec; 1109 #ifdef notyet 1110 i2c->adapter.owner = THIS_MODULE; 1111 i2c->adapter.class = I2C_CLASS_DDC; 1112 i2c->adapter.dev.parent = &dev->pdev->dev; 1113 #endif 1114 i2c->dev = dev; 1115 #ifdef notyet 1116 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 1117 "Radeon aux bus %s", name); 1118 i2c_set_adapdata(&i2c->adapter, i2c); 1119 i2c->adapter.algo_data = &i2c->algo.dp; 1120 #endif 1121 i2c->adapter.ic_cookie = &i2c->algo.dp; 1122 i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch; 1123 i2c->algo.dp.adapter = &i2c->adapter; 1124 i2c->algo.dp.address = 0; 1125 ret = i2c_dp_aux_add_bus(&i2c->adapter); 1126 if (ret) { 1127 DRM_INFO("Failed to register i2c %s\n", name); 1128 goto out_free; 1129 } 1130 1131 return i2c; 1132 out_free: 1133 kfree(i2c); 1134 return NULL; 1135 } 1136 1137 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c) 1138 { 1139 printf("%s stub\n", __func__); 1140 #ifdef notyet 1141 if (!i2c) 1142 return; 1143 i2c_del_adapter(&i2c->adapter); 1144 kfree(i2c); 1145 #endif 1146 } 1147 1148 /* Add the default buses */ 1149 void radeon_i2c_init(struct radeon_device *rdev) 1150 { 1151 if (radeon_hw_i2c) 1152 DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n"); 1153 1154 if (rdev->is_atom_bios) 1155 radeon_atombios_i2c_init(rdev); 1156 else 1157 radeon_combios_i2c_init(rdev); 1158 } 1159 1160 /* remove all the buses */ 1161 void radeon_i2c_fini(struct radeon_device *rdev) 1162 { 1163 int i; 1164 1165 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1166 if (rdev->i2c_bus[i]) { 1167 radeon_i2c_destroy(rdev->i2c_bus[i]); 1168 rdev->i2c_bus[i] = NULL; 1169 } 1170 } 1171 } 1172 1173 /* Add additional buses */ 1174 void radeon_i2c_add(struct radeon_device *rdev, 1175 struct radeon_i2c_bus_rec *rec, 1176 const char *name) 1177 { 1178 struct drm_device *dev = rdev->ddev; 1179 int i; 1180 1181 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1182 if (!rdev->i2c_bus[i]) { 1183 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name); 1184 return; 1185 } 1186 } 1187 } 1188 1189 /* looks up bus based on id */ 1190 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 1191 struct radeon_i2c_bus_rec *i2c_bus) 1192 { 1193 int i; 1194 1195 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1196 if (rdev->i2c_bus[i] && 1197 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) { 1198 return rdev->i2c_bus[i]; 1199 } 1200 } 1201 return NULL; 1202 } 1203 1204 struct drm_encoder *radeon_best_encoder(struct drm_connector *connector) 1205 { 1206 return NULL; 1207 } 1208 1209 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 1210 u8 slave_addr, 1211 u8 addr, 1212 u8 *val) 1213 { 1214 printf("%s stub\n", __func__); 1215 #ifdef notyet 1216 u8 out_buf[2]; 1217 u8 in_buf[2]; 1218 struct i2c_msg msgs[] = { 1219 { 1220 .addr = slave_addr, 1221 .flags = 0, 1222 .len = 1, 1223 .buf = out_buf, 1224 }, 1225 { 1226 .addr = slave_addr, 1227 .flags = I2C_M_RD, 1228 .len = 1, 1229 .buf = in_buf, 1230 } 1231 }; 1232 1233 out_buf[0] = addr; 1234 out_buf[1] = 0; 1235 1236 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) { 1237 *val = in_buf[0]; 1238 DRM_DEBUG("val = 0x%02x\n", *val); 1239 } else { 1240 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n", 1241 addr, *val); 1242 } 1243 #endif 1244 } 1245 1246 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus, 1247 u8 slave_addr, 1248 u8 addr, 1249 u8 val) 1250 { 1251 printf("%s stub\n", __func__); 1252 #ifdef notyet 1253 uint8_t out_buf[2]; 1254 struct i2c_msg msg = { 1255 .addr = slave_addr, 1256 .flags = 0, 1257 .len = 2, 1258 .buf = out_buf, 1259 }; 1260 1261 out_buf[0] = addr; 1262 out_buf[1] = val; 1263 1264 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) 1265 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n", 1266 addr, val); 1267 #endif 1268 } 1269 1270 /* ddc router switching */ 1271 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector) 1272 { 1273 u8 val; 1274 1275 if (!radeon_connector->router.ddc_valid) 1276 return; 1277 1278 if (!radeon_connector->router_bus) 1279 return; 1280 1281 radeon_i2c_get_byte(radeon_connector->router_bus, 1282 radeon_connector->router.i2c_addr, 1283 0x3, &val); 1284 val &= ~radeon_connector->router.ddc_mux_control_pin; 1285 radeon_i2c_put_byte(radeon_connector->router_bus, 1286 radeon_connector->router.i2c_addr, 1287 0x3, val); 1288 radeon_i2c_get_byte(radeon_connector->router_bus, 1289 radeon_connector->router.i2c_addr, 1290 0x1, &val); 1291 val &= ~radeon_connector->router.ddc_mux_control_pin; 1292 val |= radeon_connector->router.ddc_mux_state; 1293 radeon_i2c_put_byte(radeon_connector->router_bus, 1294 radeon_connector->router.i2c_addr, 1295 0x1, val); 1296 } 1297 1298 /* clock/data router switching */ 1299 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector) 1300 { 1301 u8 val; 1302 1303 if (!radeon_connector->router.cd_valid) 1304 return; 1305 1306 if (!radeon_connector->router_bus) 1307 return; 1308 1309 radeon_i2c_get_byte(radeon_connector->router_bus, 1310 radeon_connector->router.i2c_addr, 1311 0x3, &val); 1312 val &= ~radeon_connector->router.cd_mux_control_pin; 1313 radeon_i2c_put_byte(radeon_connector->router_bus, 1314 radeon_connector->router.i2c_addr, 1315 0x3, val); 1316 radeon_i2c_get_byte(radeon_connector->router_bus, 1317 radeon_connector->router.i2c_addr, 1318 0x1, &val); 1319 val &= ~radeon_connector->router.cd_mux_control_pin; 1320 val |= radeon_connector->router.cd_mux_state; 1321 radeon_i2c_put_byte(radeon_connector->router_bus, 1322 radeon_connector->router.i2c_addr, 1323 0x1, val); 1324 } 1325 1326