1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <linux/export.h> 28 #include <linux/pci.h> 29 30 #include <drm/drm_device.h> 31 #include <drm/drm_edid.h> 32 #include <drm/radeon_drm.h> 33 34 #include "radeon.h" 35 #include "atom.h" 36 37 #include <dev/i2c/i2cvar.h> 38 #include <dev/i2c/i2c_bitbang.h> 39 40 bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux) 41 { 42 u8 out = 0x0; 43 u8 buf[8]; 44 int ret; 45 struct i2c_msg msgs[] = { 46 { 47 .addr = DDC_ADDR, 48 .flags = 0, 49 .len = 1, 50 .buf = &out, 51 }, 52 { 53 .addr = DDC_ADDR, 54 .flags = I2C_M_RD, 55 .len = 8, 56 .buf = buf, 57 } 58 }; 59 60 /* on hw with routers, select right port */ 61 if (radeon_connector->router.ddc_valid) 62 radeon_router_select_ddc_port(radeon_connector); 63 64 if (use_aux) { 65 ret = i2c_transfer(&radeon_connector->ddc_bus->aux.ddc, msgs, 2); 66 } else { 67 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2); 68 } 69 70 if (ret != 2) 71 /* Couldn't find an accessible DDC on this connector */ 72 return false; 73 /* Probe also for valid EDID header 74 * EDID header starts with: 75 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 76 * Only the first 6 bytes must be valid as 77 * drm_edid_block_valid() can fix the last 2 bytes */ 78 if (drm_edid_header_is_valid(buf) < 6) { 79 /* Couldn't find an accessible EDID on this 80 * connector */ 81 return false; 82 } 83 return true; 84 } 85 86 /* bit banging i2c */ 87 88 static int pre_xfer(struct i2c_adapter *i2c_adap) 89 { 90 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 91 struct radeon_device *rdev = i2c->dev->dev_private; 92 struct radeon_i2c_bus_rec *rec = &i2c->rec; 93 uint32_t temp; 94 95 mutex_lock(&i2c->mutex); 96 97 /* RV410 appears to have a bug where the hw i2c in reset 98 * holds the i2c port in a bad state - switch hw i2c away before 99 * doing DDC - do this for all r200s/r300s/r400s for safety sake 100 */ 101 if (rec->hw_capable) { 102 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) { 103 u32 reg; 104 105 if (rdev->family >= CHIP_RV350) 106 reg = RADEON_GPIO_MONID; 107 else if ((rdev->family == CHIP_R300) || 108 (rdev->family == CHIP_R350)) 109 reg = RADEON_GPIO_DVI_DDC; 110 else 111 reg = RADEON_GPIO_CRT2_DDC; 112 113 mutex_lock(&rdev->dc_hw_i2c_mutex); 114 if (rec->a_clk_reg == reg) { 115 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 116 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1))); 117 } else { 118 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 119 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3))); 120 } 121 mutex_unlock(&rdev->dc_hw_i2c_mutex); 122 } 123 } 124 125 /* switch the pads to ddc mode */ 126 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) { 127 temp = RREG32(rec->mask_clk_reg); 128 temp &= ~(1 << 16); 129 WREG32(rec->mask_clk_reg, temp); 130 } 131 132 /* clear the output pin values */ 133 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; 134 WREG32(rec->a_clk_reg, temp); 135 136 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; 137 WREG32(rec->a_data_reg, temp); 138 139 /* set the pins to input */ 140 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 141 WREG32(rec->en_clk_reg, temp); 142 143 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 144 WREG32(rec->en_data_reg, temp); 145 146 /* mask the gpio pins for software use */ 147 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; 148 WREG32(rec->mask_clk_reg, temp); 149 temp = RREG32(rec->mask_clk_reg); 150 151 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; 152 WREG32(rec->mask_data_reg, temp); 153 temp = RREG32(rec->mask_data_reg); 154 155 return 0; 156 } 157 158 static void post_xfer(struct i2c_adapter *i2c_adap) 159 { 160 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 161 struct radeon_device *rdev = i2c->dev->dev_private; 162 struct radeon_i2c_bus_rec *rec = &i2c->rec; 163 uint32_t temp; 164 165 /* unmask the gpio pins for software use */ 166 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; 167 WREG32(rec->mask_clk_reg, temp); 168 temp = RREG32(rec->mask_clk_reg); 169 170 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask; 171 WREG32(rec->mask_data_reg, temp); 172 temp = RREG32(rec->mask_data_reg); 173 174 mutex_unlock(&i2c->mutex); 175 } 176 177 static int get_clock(void *i2c_priv) 178 { 179 struct radeon_i2c_chan *i2c = i2c_priv; 180 struct radeon_device *rdev = i2c->dev->dev_private; 181 struct radeon_i2c_bus_rec *rec = &i2c->rec; 182 uint32_t val; 183 184 /* read the value off the pin */ 185 val = RREG32(rec->y_clk_reg); 186 val &= rec->y_clk_mask; 187 188 return (val != 0); 189 } 190 191 192 static int get_data(void *i2c_priv) 193 { 194 struct radeon_i2c_chan *i2c = i2c_priv; 195 struct radeon_device *rdev = i2c->dev->dev_private; 196 struct radeon_i2c_bus_rec *rec = &i2c->rec; 197 uint32_t val; 198 199 /* read the value off the pin */ 200 val = RREG32(rec->y_data_reg); 201 val &= rec->y_data_mask; 202 203 return (val != 0); 204 } 205 206 static void set_clock(void *i2c_priv, int clock) 207 { 208 struct radeon_i2c_chan *i2c = i2c_priv; 209 struct radeon_device *rdev = i2c->dev->dev_private; 210 struct radeon_i2c_bus_rec *rec = &i2c->rec; 211 uint32_t val; 212 213 /* set pin direction */ 214 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 215 val |= clock ? 0 : rec->en_clk_mask; 216 WREG32(rec->en_clk_reg, val); 217 } 218 219 static void set_data(void *i2c_priv, int data) 220 { 221 struct radeon_i2c_chan *i2c = i2c_priv; 222 struct radeon_device *rdev = i2c->dev->dev_private; 223 struct radeon_i2c_bus_rec *rec = &i2c->rec; 224 uint32_t val; 225 226 /* set pin direction */ 227 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 228 val |= data ? 0 : rec->en_data_mask; 229 WREG32(rec->en_data_reg, val); 230 } 231 232 #ifdef __OpenBSD__ 233 234 void radeon_bb_set_bits(void *, uint32_t); 235 void radeon_bb_set_dir(void *, uint32_t); 236 uint32_t radeon_bb_read_bits(void *); 237 238 int radeon_acquire_bus(void *, int); 239 void radeon_release_bus(void *, int); 240 int radeon_send_start(void *, int); 241 int radeon_send_stop(void *, int); 242 int radeon_initiate_xfer(void *, i2c_addr_t, int); 243 int radeon_read_byte(void *, u_int8_t *, int); 244 int radeon_write_byte(void *, u_int8_t, int); 245 246 #define RADEON_BB_SDA (1 << I2C_BIT_SDA) 247 #define RADEON_BB_SCL (1 << I2C_BIT_SCL) 248 249 struct i2c_bitbang_ops radeon_bbops = { 250 radeon_bb_set_bits, 251 radeon_bb_set_dir, 252 radeon_bb_read_bits, 253 { RADEON_BB_SDA, RADEON_BB_SCL, 0, 0 } 254 }; 255 256 void 257 radeon_bb_set_bits(void *cookie, uint32_t bits) 258 { 259 set_clock(cookie, bits & RADEON_BB_SCL); 260 set_data(cookie, bits & RADEON_BB_SDA); 261 } 262 263 void 264 radeon_bb_set_dir(void *cookie, uint32_t bits) 265 { 266 } 267 268 uint32_t 269 radeon_bb_read_bits(void *cookie) 270 { 271 uint32_t bits = 0; 272 273 if (get_clock(cookie)) 274 bits |= RADEON_BB_SCL; 275 if (get_data(cookie)) 276 bits |= RADEON_BB_SDA; 277 278 return bits; 279 } 280 281 int 282 radeon_acquire_bus(void *cookie, int flags) 283 { 284 struct radeon_i2c_chan *i2c = cookie; 285 pre_xfer(&i2c->adapter); 286 return (0); 287 } 288 289 void 290 radeon_release_bus(void *cookie, int flags) 291 { 292 struct radeon_i2c_chan *i2c = cookie; 293 post_xfer(&i2c->adapter); 294 } 295 296 int 297 radeon_send_start(void *cookie, int flags) 298 { 299 return (i2c_bitbang_send_start(cookie, flags, &radeon_bbops)); 300 } 301 302 int 303 radeon_send_stop(void *cookie, int flags) 304 { 305 return (i2c_bitbang_send_stop(cookie, flags, &radeon_bbops)); 306 } 307 308 int 309 radeon_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 310 { 311 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, &radeon_bbops)); 312 } 313 314 int 315 radeon_read_byte(void *cookie, u_int8_t *bytep, int flags) 316 { 317 return (i2c_bitbang_read_byte(cookie, bytep, flags, &radeon_bbops)); 318 } 319 320 int 321 radeon_write_byte(void *cookie, u_int8_t byte, int flags) 322 { 323 return (i2c_bitbang_write_byte(cookie, byte, flags, &radeon_bbops)); 324 } 325 326 #endif /* __OpenBSD__ */ 327 328 /* hw i2c */ 329 330 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev) 331 { 332 u32 sclk = rdev->pm.current_sclk; 333 u32 prescale = 0; 334 u32 nm; 335 u8 n, m, loop; 336 int i2c_clock; 337 338 switch (rdev->family) { 339 case CHIP_R100: 340 case CHIP_RV100: 341 case CHIP_RS100: 342 case CHIP_RV200: 343 case CHIP_RS200: 344 case CHIP_R200: 345 case CHIP_RV250: 346 case CHIP_RS300: 347 case CHIP_RV280: 348 case CHIP_R300: 349 case CHIP_R350: 350 case CHIP_RV350: 351 i2c_clock = 60; 352 nm = (sclk * 10) / (i2c_clock * 4); 353 for (loop = 1; loop < 255; loop++) { 354 if ((nm / loop) < loop) 355 break; 356 } 357 n = loop - 1; 358 m = loop - 2; 359 prescale = m | (n << 8); 360 break; 361 case CHIP_RV380: 362 case CHIP_RS400: 363 case CHIP_RS480: 364 case CHIP_R420: 365 case CHIP_R423: 366 case CHIP_RV410: 367 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 368 break; 369 case CHIP_RS600: 370 case CHIP_RS690: 371 case CHIP_RS740: 372 /* todo */ 373 break; 374 case CHIP_RV515: 375 case CHIP_R520: 376 case CHIP_RV530: 377 case CHIP_RV560: 378 case CHIP_RV570: 379 case CHIP_R580: 380 i2c_clock = 50; 381 if (rdev->family == CHIP_R520) 382 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock)); 383 else 384 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 385 break; 386 case CHIP_R600: 387 case CHIP_RV610: 388 case CHIP_RV630: 389 case CHIP_RV670: 390 /* todo */ 391 break; 392 case CHIP_RV620: 393 case CHIP_RV635: 394 case CHIP_RS780: 395 case CHIP_RS880: 396 case CHIP_RV770: 397 case CHIP_RV730: 398 case CHIP_RV710: 399 case CHIP_RV740: 400 /* todo */ 401 break; 402 case CHIP_CEDAR: 403 case CHIP_REDWOOD: 404 case CHIP_JUNIPER: 405 case CHIP_CYPRESS: 406 case CHIP_HEMLOCK: 407 /* todo */ 408 break; 409 default: 410 DRM_ERROR("i2c: unhandled radeon chip\n"); 411 break; 412 } 413 return prescale; 414 } 415 416 417 /* hw i2c engine for r1xx-4xx hardware 418 * hw can buffer up to 15 bytes 419 */ 420 static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 421 struct i2c_msg *msgs, int num) 422 { 423 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 424 struct radeon_device *rdev = i2c->dev->dev_private; 425 struct radeon_i2c_bus_rec *rec = &i2c->rec; 426 struct i2c_msg *p; 427 int i, j, k, ret = num; 428 u32 prescale; 429 u32 i2c_cntl_0, i2c_cntl_1, i2c_data; 430 u32 tmp, reg; 431 432 mutex_lock(&rdev->dc_hw_i2c_mutex); 433 /* take the pm lock since we need a constant sclk */ 434 mutex_lock(&rdev->pm.mutex); 435 436 prescale = radeon_get_i2c_prescale(rdev); 437 438 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) | 439 RADEON_I2C_DRIVE_EN | 440 RADEON_I2C_START | 441 RADEON_I2C_STOP | 442 RADEON_I2C_GO); 443 444 if (rdev->is_atom_bios) { 445 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 446 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 447 } 448 449 if (rec->mm_i2c) { 450 i2c_cntl_0 = RADEON_I2C_CNTL_0; 451 i2c_cntl_1 = RADEON_I2C_CNTL_1; 452 i2c_data = RADEON_I2C_DATA; 453 } else { 454 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0; 455 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1; 456 i2c_data = RADEON_DVI_I2C_DATA; 457 458 switch (rdev->family) { 459 case CHIP_R100: 460 case CHIP_RV100: 461 case CHIP_RS100: 462 case CHIP_RV200: 463 case CHIP_RS200: 464 case CHIP_RS300: 465 switch (rec->mask_clk_reg) { 466 case RADEON_GPIO_DVI_DDC: 467 /* no gpio select bit */ 468 break; 469 default: 470 DRM_ERROR("gpio not supported with hw i2c\n"); 471 ret = -EINVAL; 472 goto done; 473 } 474 break; 475 case CHIP_R200: 476 /* only bit 4 on r200 */ 477 switch (rec->mask_clk_reg) { 478 case RADEON_GPIO_DVI_DDC: 479 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 480 break; 481 case RADEON_GPIO_MONID: 482 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 483 break; 484 default: 485 DRM_ERROR("gpio not supported with hw i2c\n"); 486 ret = -EINVAL; 487 goto done; 488 } 489 break; 490 case CHIP_RV250: 491 case CHIP_RV280: 492 /* bits 3 and 4 */ 493 switch (rec->mask_clk_reg) { 494 case RADEON_GPIO_DVI_DDC: 495 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 496 break; 497 case RADEON_GPIO_VGA_DDC: 498 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 499 break; 500 case RADEON_GPIO_CRT2_DDC: 501 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 502 break; 503 default: 504 DRM_ERROR("gpio not supported with hw i2c\n"); 505 ret = -EINVAL; 506 goto done; 507 } 508 break; 509 case CHIP_R300: 510 case CHIP_R350: 511 /* only bit 4 on r300/r350 */ 512 switch (rec->mask_clk_reg) { 513 case RADEON_GPIO_VGA_DDC: 514 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 515 break; 516 case RADEON_GPIO_DVI_DDC: 517 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 518 break; 519 default: 520 DRM_ERROR("gpio not supported with hw i2c\n"); 521 ret = -EINVAL; 522 goto done; 523 } 524 break; 525 case CHIP_RV350: 526 case CHIP_RV380: 527 case CHIP_R420: 528 case CHIP_R423: 529 case CHIP_RV410: 530 case CHIP_RS400: 531 case CHIP_RS480: 532 /* bits 3 and 4 */ 533 switch (rec->mask_clk_reg) { 534 case RADEON_GPIO_VGA_DDC: 535 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 536 break; 537 case RADEON_GPIO_DVI_DDC: 538 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 539 break; 540 case RADEON_GPIO_MONID: 541 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 542 break; 543 default: 544 DRM_ERROR("gpio not supported with hw i2c\n"); 545 ret = -EINVAL; 546 goto done; 547 } 548 break; 549 default: 550 DRM_ERROR("unsupported asic\n"); 551 ret = -EINVAL; 552 goto done; 553 break; 554 } 555 } 556 557 /* check for bus probe */ 558 p = &msgs[0]; 559 if ((num == 1) && (p->len == 0)) { 560 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 561 RADEON_I2C_NACK | 562 RADEON_I2C_HALT | 563 RADEON_I2C_SOFT_RST)); 564 WREG32(i2c_data, (p->addr << 1) & 0xff); 565 WREG32(i2c_data, 0); 566 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 567 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 568 RADEON_I2C_EN | 569 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 570 WREG32(i2c_cntl_0, reg); 571 for (k = 0; k < 32; k++) { 572 udelay(10); 573 tmp = RREG32(i2c_cntl_0); 574 if (tmp & RADEON_I2C_GO) 575 continue; 576 tmp = RREG32(i2c_cntl_0); 577 if (tmp & RADEON_I2C_DONE) 578 break; 579 else { 580 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 581 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 582 ret = -EIO; 583 goto done; 584 } 585 } 586 goto done; 587 } 588 589 for (i = 0; i < num; i++) { 590 p = &msgs[i]; 591 for (j = 0; j < p->len; j++) { 592 if (p->flags & I2C_M_RD) { 593 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 594 RADEON_I2C_NACK | 595 RADEON_I2C_HALT | 596 RADEON_I2C_SOFT_RST)); 597 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1); 598 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 599 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 600 RADEON_I2C_EN | 601 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 602 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE); 603 for (k = 0; k < 32; k++) { 604 udelay(10); 605 tmp = RREG32(i2c_cntl_0); 606 if (tmp & RADEON_I2C_GO) 607 continue; 608 tmp = RREG32(i2c_cntl_0); 609 if (tmp & RADEON_I2C_DONE) 610 break; 611 else { 612 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 613 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 614 ret = -EIO; 615 goto done; 616 } 617 } 618 p->buf[j] = RREG32(i2c_data) & 0xff; 619 } else { 620 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 621 RADEON_I2C_NACK | 622 RADEON_I2C_HALT | 623 RADEON_I2C_SOFT_RST)); 624 WREG32(i2c_data, (p->addr << 1) & 0xff); 625 WREG32(i2c_data, p->buf[j]); 626 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 627 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 628 RADEON_I2C_EN | 629 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 630 WREG32(i2c_cntl_0, reg); 631 for (k = 0; k < 32; k++) { 632 udelay(10); 633 tmp = RREG32(i2c_cntl_0); 634 if (tmp & RADEON_I2C_GO) 635 continue; 636 tmp = RREG32(i2c_cntl_0); 637 if (tmp & RADEON_I2C_DONE) 638 break; 639 else { 640 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 641 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 642 ret = -EIO; 643 goto done; 644 } 645 } 646 } 647 } 648 } 649 650 done: 651 WREG32(i2c_cntl_0, 0); 652 WREG32(i2c_cntl_1, 0); 653 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 654 RADEON_I2C_NACK | 655 RADEON_I2C_HALT | 656 RADEON_I2C_SOFT_RST)); 657 658 if (rdev->is_atom_bios) { 659 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 660 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 661 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 662 } 663 664 mutex_unlock(&rdev->pm.mutex); 665 mutex_unlock(&rdev->dc_hw_i2c_mutex); 666 667 return ret; 668 } 669 670 /* hw i2c engine for r5xx hardware 671 * hw can buffer up to 15 bytes 672 */ 673 static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 674 struct i2c_msg *msgs, int num) 675 { 676 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 677 struct radeon_device *rdev = i2c->dev->dev_private; 678 struct radeon_i2c_bus_rec *rec = &i2c->rec; 679 struct i2c_msg *p; 680 int i, j, remaining, current_count, buffer_offset, ret = num; 681 u32 prescale; 682 u32 tmp, reg; 683 u32 saved1, saved2; 684 685 mutex_lock(&rdev->dc_hw_i2c_mutex); 686 /* take the pm lock since we need a constant sclk */ 687 mutex_lock(&rdev->pm.mutex); 688 689 prescale = radeon_get_i2c_prescale(rdev); 690 691 /* clear gpio mask bits */ 692 tmp = RREG32(rec->mask_clk_reg); 693 tmp &= ~rec->mask_clk_mask; 694 WREG32(rec->mask_clk_reg, tmp); 695 tmp = RREG32(rec->mask_clk_reg); 696 697 tmp = RREG32(rec->mask_data_reg); 698 tmp &= ~rec->mask_data_mask; 699 WREG32(rec->mask_data_reg, tmp); 700 tmp = RREG32(rec->mask_data_reg); 701 702 /* clear pin values */ 703 tmp = RREG32(rec->a_clk_reg); 704 tmp &= ~rec->a_clk_mask; 705 WREG32(rec->a_clk_reg, tmp); 706 tmp = RREG32(rec->a_clk_reg); 707 708 tmp = RREG32(rec->a_data_reg); 709 tmp &= ~rec->a_data_mask; 710 WREG32(rec->a_data_reg, tmp); 711 tmp = RREG32(rec->a_data_reg); 712 713 /* set the pins to input */ 714 tmp = RREG32(rec->en_clk_reg); 715 tmp &= ~rec->en_clk_mask; 716 WREG32(rec->en_clk_reg, tmp); 717 tmp = RREG32(rec->en_clk_reg); 718 719 tmp = RREG32(rec->en_data_reg); 720 tmp &= ~rec->en_data_mask; 721 WREG32(rec->en_data_reg, tmp); 722 tmp = RREG32(rec->en_data_reg); 723 724 /* */ 725 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 726 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 727 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1); 728 saved2 = RREG32(0x494); 729 WREG32(0x494, saved2 | 0x1); 730 731 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C); 732 for (i = 0; i < 50; i++) { 733 udelay(1); 734 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C) 735 break; 736 } 737 if (i == 50) { 738 DRM_ERROR("failed to get i2c bus\n"); 739 ret = -EBUSY; 740 goto done; 741 } 742 743 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN; 744 switch (rec->mask_clk_reg) { 745 case AVIVO_DC_GPIO_DDC1_MASK: 746 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1); 747 break; 748 case AVIVO_DC_GPIO_DDC2_MASK: 749 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2); 750 break; 751 case AVIVO_DC_GPIO_DDC3_MASK: 752 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3); 753 break; 754 default: 755 DRM_ERROR("gpio not supported with hw i2c\n"); 756 ret = -EINVAL; 757 goto done; 758 } 759 760 /* check for bus probe */ 761 p = &msgs[0]; 762 if ((num == 1) && (p->len == 0)) { 763 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 764 AVIVO_DC_I2C_NACK | 765 AVIVO_DC_I2C_HALT)); 766 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 767 udelay(1); 768 WREG32(AVIVO_DC_I2C_RESET, 0); 769 770 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); 771 WREG32(AVIVO_DC_I2C_DATA, 0); 772 773 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 774 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 775 AVIVO_DC_I2C_DATA_COUNT(1) | 776 (prescale << 16))); 777 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 778 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 779 for (j = 0; j < 200; j++) { 780 udelay(50); 781 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 782 if (tmp & AVIVO_DC_I2C_GO) 783 continue; 784 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 785 if (tmp & AVIVO_DC_I2C_DONE) 786 break; 787 else { 788 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 789 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 790 ret = -EIO; 791 goto done; 792 } 793 } 794 goto done; 795 } 796 797 for (i = 0; i < num; i++) { 798 p = &msgs[i]; 799 remaining = p->len; 800 buffer_offset = 0; 801 if (p->flags & I2C_M_RD) { 802 while (remaining) { 803 if (remaining > 15) 804 current_count = 15; 805 else 806 current_count = remaining; 807 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 808 AVIVO_DC_I2C_NACK | 809 AVIVO_DC_I2C_HALT)); 810 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 811 udelay(1); 812 WREG32(AVIVO_DC_I2C_RESET, 0); 813 814 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1); 815 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 816 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 817 AVIVO_DC_I2C_DATA_COUNT(current_count) | 818 (prescale << 16))); 819 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE); 820 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 821 for (j = 0; j < 200; j++) { 822 udelay(50); 823 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 824 if (tmp & AVIVO_DC_I2C_GO) 825 continue; 826 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 827 if (tmp & AVIVO_DC_I2C_DONE) 828 break; 829 else { 830 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 831 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 832 ret = -EIO; 833 goto done; 834 } 835 } 836 for (j = 0; j < current_count; j++) 837 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff; 838 remaining -= current_count; 839 buffer_offset += current_count; 840 } 841 } else { 842 while (remaining) { 843 if (remaining > 15) 844 current_count = 15; 845 else 846 current_count = remaining; 847 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 848 AVIVO_DC_I2C_NACK | 849 AVIVO_DC_I2C_HALT)); 850 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 851 udelay(1); 852 WREG32(AVIVO_DC_I2C_RESET, 0); 853 854 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); 855 for (j = 0; j < current_count; j++) 856 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]); 857 858 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 859 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 860 AVIVO_DC_I2C_DATA_COUNT(current_count) | 861 (prescale << 16))); 862 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 863 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 864 for (j = 0; j < 200; j++) { 865 udelay(50); 866 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 867 if (tmp & AVIVO_DC_I2C_GO) 868 continue; 869 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 870 if (tmp & AVIVO_DC_I2C_DONE) 871 break; 872 else { 873 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 874 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 875 ret = -EIO; 876 goto done; 877 } 878 } 879 remaining -= current_count; 880 buffer_offset += current_count; 881 } 882 } 883 } 884 885 done: 886 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 887 AVIVO_DC_I2C_NACK | 888 AVIVO_DC_I2C_HALT)); 889 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 890 udelay(1); 891 WREG32(AVIVO_DC_I2C_RESET, 0); 892 893 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C); 894 WREG32(AVIVO_DC_I2C_CONTROL1, saved1); 895 WREG32(0x494, saved2); 896 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 897 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 898 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 899 900 mutex_unlock(&rdev->pm.mutex); 901 mutex_unlock(&rdev->dc_hw_i2c_mutex); 902 903 return ret; 904 } 905 906 static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 907 struct i2c_msg *msgs, int num) 908 { 909 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 910 struct radeon_device *rdev = i2c->dev->dev_private; 911 struct radeon_i2c_bus_rec *rec = &i2c->rec; 912 int ret = 0; 913 914 mutex_lock(&i2c->mutex); 915 916 switch (rdev->family) { 917 case CHIP_R100: 918 case CHIP_RV100: 919 case CHIP_RS100: 920 case CHIP_RV200: 921 case CHIP_RS200: 922 case CHIP_R200: 923 case CHIP_RV250: 924 case CHIP_RS300: 925 case CHIP_RV280: 926 case CHIP_R300: 927 case CHIP_R350: 928 case CHIP_RV350: 929 case CHIP_RV380: 930 case CHIP_R420: 931 case CHIP_R423: 932 case CHIP_RV410: 933 case CHIP_RS400: 934 case CHIP_RS480: 935 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); 936 break; 937 case CHIP_RS600: 938 case CHIP_RS690: 939 case CHIP_RS740: 940 /* XXX fill in hw i2c implementation */ 941 break; 942 case CHIP_RV515: 943 case CHIP_R520: 944 case CHIP_RV530: 945 case CHIP_RV560: 946 case CHIP_RV570: 947 case CHIP_R580: 948 if (rec->mm_i2c) 949 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); 950 else 951 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num); 952 break; 953 case CHIP_R600: 954 case CHIP_RV610: 955 case CHIP_RV630: 956 case CHIP_RV670: 957 /* XXX fill in hw i2c implementation */ 958 break; 959 case CHIP_RV620: 960 case CHIP_RV635: 961 case CHIP_RS780: 962 case CHIP_RS880: 963 case CHIP_RV770: 964 case CHIP_RV730: 965 case CHIP_RV710: 966 case CHIP_RV740: 967 /* XXX fill in hw i2c implementation */ 968 break; 969 case CHIP_CEDAR: 970 case CHIP_REDWOOD: 971 case CHIP_JUNIPER: 972 case CHIP_CYPRESS: 973 case CHIP_HEMLOCK: 974 /* XXX fill in hw i2c implementation */ 975 break; 976 default: 977 DRM_ERROR("i2c: unhandled radeon chip\n"); 978 ret = -EIO; 979 break; 980 } 981 982 mutex_unlock(&i2c->mutex); 983 984 return ret; 985 } 986 987 static u32 radeon_hw_i2c_func(struct i2c_adapter *adap) 988 { 989 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 990 } 991 992 static const struct i2c_algorithm radeon_i2c_algo = { 993 .master_xfer = radeon_hw_i2c_xfer, 994 .functionality = radeon_hw_i2c_func, 995 }; 996 997 static const struct i2c_algorithm radeon_atom_i2c_algo = { 998 .master_xfer = radeon_atom_hw_i2c_xfer, 999 .functionality = radeon_atom_hw_i2c_func, 1000 }; 1001 1002 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 1003 struct radeon_i2c_bus_rec *rec, 1004 const char *name) 1005 { 1006 struct radeon_device *rdev = dev->dev_private; 1007 struct radeon_i2c_chan *i2c; 1008 int ret; 1009 1010 /* don't add the mm_i2c bus unless hw_i2c is enabled */ 1011 if (rec->mm_i2c && (radeon_hw_i2c == 0)) 1012 return NULL; 1013 1014 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL); 1015 if (i2c == NULL) 1016 return NULL; 1017 1018 i2c->rec = *rec; 1019 #ifdef __linux__ 1020 i2c->adapter.owner = THIS_MODULE; 1021 i2c->adapter.class = I2C_CLASS_DDC; 1022 i2c->adapter.dev.parent = dev->dev; 1023 #endif 1024 i2c->dev = dev; 1025 i2c_set_adapdata(&i2c->adapter, i2c); 1026 rw_init(&i2c->mutex, "riic"); 1027 if (rec->mm_i2c || 1028 (rec->hw_capable && 1029 radeon_hw_i2c && 1030 ((rdev->family <= CHIP_RS480) || 1031 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) { 1032 /* set the radeon hw i2c adapter */ 1033 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 1034 "Radeon i2c hw bus %s", name); 1035 i2c->adapter.algo = &radeon_i2c_algo; 1036 ret = i2c_add_adapter(&i2c->adapter); 1037 if (ret) 1038 goto out_free; 1039 } else if (rec->hw_capable && 1040 radeon_hw_i2c && 1041 ASIC_IS_DCE3(rdev)) { 1042 /* hw i2c using atom */ 1043 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 1044 "Radeon i2c hw bus %s", name); 1045 i2c->adapter.algo = &radeon_atom_i2c_algo; 1046 ret = i2c_add_adapter(&i2c->adapter); 1047 if (ret) 1048 goto out_free; 1049 } else { 1050 /* set the radeon bit adapter */ 1051 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 1052 "Radeon i2c bit bus %s", name); 1053 i2c->adapter.algo_data = &i2c->bit; 1054 #ifdef notyet 1055 i2c->bit.pre_xfer = pre_xfer; 1056 i2c->bit.post_xfer = post_xfer; 1057 i2c->bit.setsda = set_data; 1058 i2c->bit.setscl = set_clock; 1059 i2c->bit.getsda = get_data; 1060 i2c->bit.getscl = get_clock; 1061 i2c->bit.udelay = 10; 1062 i2c->bit.timeout = usecs_to_jiffies(2200); /* from VESA */ 1063 i2c->bit.data = i2c; 1064 #else 1065 i2c->bit.ic.ic_cookie = i2c; 1066 i2c->bit.ic.ic_acquire_bus = radeon_acquire_bus; 1067 i2c->bit.ic.ic_release_bus = radeon_release_bus; 1068 i2c->bit.ic.ic_send_start = radeon_send_start; 1069 i2c->bit.ic.ic_send_stop = radeon_send_stop; 1070 i2c->bit.ic.ic_initiate_xfer = radeon_initiate_xfer; 1071 i2c->bit.ic.ic_read_byte = radeon_read_byte; 1072 i2c->bit.ic.ic_write_byte = radeon_write_byte; 1073 #endif 1074 ret = i2c_bit_add_bus(&i2c->adapter); 1075 if (ret) { 1076 DRM_ERROR("Failed to register bit i2c %s\n", name); 1077 goto out_free; 1078 } 1079 } 1080 1081 return i2c; 1082 out_free: 1083 kfree(i2c); 1084 return NULL; 1085 1086 } 1087 1088 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c) 1089 { 1090 if (!i2c) 1091 return; 1092 WARN_ON(i2c->has_aux); 1093 i2c_del_adapter(&i2c->adapter); 1094 kfree(i2c); 1095 } 1096 1097 /* Add the default buses */ 1098 void radeon_i2c_init(struct radeon_device *rdev) 1099 { 1100 if (radeon_hw_i2c) 1101 DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n"); 1102 1103 if (rdev->is_atom_bios) 1104 radeon_atombios_i2c_init(rdev); 1105 else 1106 radeon_combios_i2c_init(rdev); 1107 } 1108 1109 /* remove all the buses */ 1110 void radeon_i2c_fini(struct radeon_device *rdev) 1111 { 1112 int i; 1113 1114 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1115 if (rdev->i2c_bus[i]) { 1116 radeon_i2c_destroy(rdev->i2c_bus[i]); 1117 rdev->i2c_bus[i] = NULL; 1118 } 1119 } 1120 } 1121 1122 /* Add additional buses */ 1123 void radeon_i2c_add(struct radeon_device *rdev, 1124 struct radeon_i2c_bus_rec *rec, 1125 const char *name) 1126 { 1127 struct drm_device *dev = rdev_to_drm(rdev); 1128 int i; 1129 1130 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1131 if (!rdev->i2c_bus[i]) { 1132 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name); 1133 return; 1134 } 1135 } 1136 } 1137 1138 /* looks up bus based on id */ 1139 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 1140 struct radeon_i2c_bus_rec *i2c_bus) 1141 { 1142 int i; 1143 1144 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1145 if (rdev->i2c_bus[i] && 1146 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) { 1147 return rdev->i2c_bus[i]; 1148 } 1149 } 1150 return NULL; 1151 } 1152 1153 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 1154 u8 slave_addr, 1155 u8 addr, 1156 u8 *val) 1157 { 1158 u8 out_buf[2]; 1159 u8 in_buf[2]; 1160 struct i2c_msg msgs[] = { 1161 { 1162 .addr = slave_addr, 1163 .flags = 0, 1164 .len = 1, 1165 .buf = out_buf, 1166 }, 1167 { 1168 .addr = slave_addr, 1169 .flags = I2C_M_RD, 1170 .len = 1, 1171 .buf = in_buf, 1172 } 1173 }; 1174 1175 out_buf[0] = addr; 1176 out_buf[1] = 0; 1177 1178 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) { 1179 *val = in_buf[0]; 1180 DRM_DEBUG("val = 0x%02x\n", *val); 1181 } else { 1182 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n", 1183 addr, *val); 1184 } 1185 } 1186 1187 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus, 1188 u8 slave_addr, 1189 u8 addr, 1190 u8 val) 1191 { 1192 uint8_t out_buf[2]; 1193 struct i2c_msg msg = { 1194 .addr = slave_addr, 1195 .flags = 0, 1196 .len = 2, 1197 .buf = out_buf, 1198 }; 1199 1200 out_buf[0] = addr; 1201 out_buf[1] = val; 1202 1203 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) 1204 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n", 1205 addr, val); 1206 } 1207 1208 /* ddc router switching */ 1209 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector) 1210 { 1211 u8 val; 1212 1213 if (!radeon_connector->router.ddc_valid) 1214 return; 1215 1216 if (!radeon_connector->router_bus) 1217 return; 1218 1219 radeon_i2c_get_byte(radeon_connector->router_bus, 1220 radeon_connector->router.i2c_addr, 1221 0x3, &val); 1222 val &= ~radeon_connector->router.ddc_mux_control_pin; 1223 radeon_i2c_put_byte(radeon_connector->router_bus, 1224 radeon_connector->router.i2c_addr, 1225 0x3, val); 1226 radeon_i2c_get_byte(radeon_connector->router_bus, 1227 radeon_connector->router.i2c_addr, 1228 0x1, &val); 1229 val &= ~radeon_connector->router.ddc_mux_control_pin; 1230 val |= radeon_connector->router.ddc_mux_state; 1231 radeon_i2c_put_byte(radeon_connector->router_bus, 1232 radeon_connector->router.i2c_addr, 1233 0x1, val); 1234 } 1235 1236 /* clock/data router switching */ 1237 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector) 1238 { 1239 u8 val; 1240 1241 if (!radeon_connector->router.cd_valid) 1242 return; 1243 1244 if (!radeon_connector->router_bus) 1245 return; 1246 1247 radeon_i2c_get_byte(radeon_connector->router_bus, 1248 radeon_connector->router.i2c_addr, 1249 0x3, &val); 1250 val &= ~radeon_connector->router.cd_mux_control_pin; 1251 radeon_i2c_put_byte(radeon_connector->router_bus, 1252 radeon_connector->router.i2c_addr, 1253 0x3, val); 1254 radeon_i2c_get_byte(radeon_connector->router_bus, 1255 radeon_connector->router.i2c_addr, 1256 0x1, &val); 1257 val &= ~radeon_connector->router.cd_mux_control_pin; 1258 val |= radeon_connector->router.cd_mux_state; 1259 radeon_i2c_put_byte(radeon_connector->router_bus, 1260 radeon_connector->router.i2c_addr, 1261 0x1, val); 1262 } 1263 1264