1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2023 Intel Corporation
4 */
5
6 #include <linux/pci.h>
7 #include <linux/pnp.h>
8
9 #include <drm/drm_managed.h>
10 #include <drm/i915_drm.h>
11
12 #include "i915_drv.h"
13 #include "intel_gmch.h"
14 #include "intel_pci_config.h"
15
intel_gmch_bridge_release(struct drm_device * dev,void * bridge)16 static void intel_gmch_bridge_release(struct drm_device *dev, void *bridge)
17 {
18 pci_dev_put(bridge);
19 }
20
21 #ifdef __linux__
intel_gmch_bridge_setup(struct drm_i915_private * i915)22 int intel_gmch_bridge_setup(struct drm_i915_private *i915)
23 {
24 int domain = pci_domain_nr(to_pci_dev(i915->drm.dev)->bus);
25
26 i915->gmch.pdev = pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
27 if (!i915->gmch.pdev) {
28 drm_err(&i915->drm, "bridge device not found\n");
29 return -EIO;
30 }
31
32 return drmm_add_action_or_reset(&i915->drm, intel_gmch_bridge_release,
33 i915->gmch.pdev);
34 }
35 #else
intel_gmch_bridge_setup(struct drm_i915_private * i915)36 int intel_gmch_bridge_setup(struct drm_i915_private *i915)
37 {
38 struct drm_device *dev = &i915->drm;
39
40 /* may be already called from attach */
41 if (i915->gmch.pdev != NULL)
42 return 0;
43
44 i915->gmch.pdev = malloc(sizeof(*i915->gmch.pdev),
45 M_DEVBUF, M_WAITOK);
46 i915->gmch.pdev->pc = dev->pdev->pc;
47 i915->gmch.pdev->tag = pci_make_tag(dev->pdev->pc, 0, 0, 0);
48
49 return drmm_add_action_or_reset(&i915->drm, intel_gmch_bridge_release,
50 i915->gmch.pdev);
51 }
52 #endif
53
54 /* Allocate space for the MCH regs if needed, return nonzero on error */
55 static int
intel_alloc_mchbar_resource(struct drm_i915_private * i915)56 intel_alloc_mchbar_resource(struct drm_i915_private *i915)
57 {
58 int reg = GRAPHICS_VER(i915) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
59 u32 temp_lo, temp_hi = 0;
60 u64 mchbar_addr;
61 int ret;
62
63 if (GRAPHICS_VER(i915) >= 4)
64 pci_read_config_dword(i915->gmch.pdev, reg + 4, &temp_hi);
65 pci_read_config_dword(i915->gmch.pdev, reg, &temp_lo);
66 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
67
68 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
69 #ifdef CONFIG_PNP
70 if (IS_ENABLED(CONFIG_PNP) && mchbar_addr &&
71 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
72 return 0;
73 #endif
74
75 #ifdef __linux__
76 /* Get some space for it */
77 i915->gmch.mch_res.name = "i915 MCHBAR";
78 i915->gmch.mch_res.flags = IORESOURCE_MEM;
79 ret = pci_bus_alloc_resource(i915->gmch.pdev->bus,
80 &i915->gmch.mch_res,
81 MCHBAR_SIZE, MCHBAR_SIZE,
82 PCIBIOS_MIN_MEM,
83 0, pcibios_align_resource,
84 i915->gmch.pdev);
85 if (ret) {
86 drm_dbg(&i915->drm, "failed bus alloc: %d\n", ret);
87 i915->gmch.mch_res.start = 0;
88 return ret;
89 }
90 #else
91 if (i915->memex == NULL || extent_alloc(i915->memex,
92 MCHBAR_SIZE, MCHBAR_SIZE, 0, 0, 0, &i915->gmch.mch_res.start)) {
93 return -ENOMEM;
94 }
95 #endif
96
97 if (GRAPHICS_VER(i915) >= 4)
98 pci_write_config_dword(i915->gmch.pdev, reg + 4,
99 upper_32_bits(i915->gmch.mch_res.start));
100
101 pci_write_config_dword(i915->gmch.pdev, reg,
102 lower_32_bits(i915->gmch.mch_res.start));
103 return 0;
104 }
105
106 /* Setup MCHBAR if possible, return true if we should disable it again */
intel_gmch_bar_setup(struct drm_i915_private * i915)107 void intel_gmch_bar_setup(struct drm_i915_private *i915)
108 {
109 int mchbar_reg = GRAPHICS_VER(i915) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
110 u32 temp;
111 bool enabled;
112
113 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
114 return;
115
116 i915->gmch.mchbar_need_disable = false;
117
118 if (IS_I915G(i915) || IS_I915GM(i915)) {
119 pci_read_config_dword(i915->gmch.pdev, DEVEN, &temp);
120 enabled = !!(temp & DEVEN_MCHBAR_EN);
121 } else {
122 pci_read_config_dword(i915->gmch.pdev, mchbar_reg, &temp);
123 enabled = temp & 1;
124 }
125
126 /* If it's already enabled, don't have to do anything */
127 if (enabled)
128 return;
129
130 if (intel_alloc_mchbar_resource(i915))
131 return;
132
133 i915->gmch.mchbar_need_disable = true;
134
135 /* Space is allocated or reserved, so enable it. */
136 if (IS_I915G(i915) || IS_I915GM(i915)) {
137 pci_write_config_dword(i915->gmch.pdev, DEVEN,
138 temp | DEVEN_MCHBAR_EN);
139 } else {
140 pci_read_config_dword(i915->gmch.pdev, mchbar_reg, &temp);
141 pci_write_config_dword(i915->gmch.pdev, mchbar_reg, temp | 1);
142 }
143 }
144
intel_gmch_bar_teardown(struct drm_i915_private * i915)145 void intel_gmch_bar_teardown(struct drm_i915_private *i915)
146 {
147 int mchbar_reg = GRAPHICS_VER(i915) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
148
149 if (i915->gmch.mchbar_need_disable) {
150 if (IS_I915G(i915) || IS_I915GM(i915)) {
151 u32 deven_val;
152
153 pci_read_config_dword(i915->gmch.pdev, DEVEN,
154 &deven_val);
155 deven_val &= ~DEVEN_MCHBAR_EN;
156 pci_write_config_dword(i915->gmch.pdev, DEVEN,
157 deven_val);
158 } else {
159 u32 mchbar_val;
160
161 pci_read_config_dword(i915->gmch.pdev, mchbar_reg,
162 &mchbar_val);
163 mchbar_val &= ~1;
164 pci_write_config_dword(i915->gmch.pdev, mchbar_reg,
165 mchbar_val);
166 }
167 }
168
169 if (i915->gmch.mch_res.start)
170 #ifdef __linux__
171 release_resource(&i915->gmch.mch_res);
172 #else
173 extent_free(i915->memex, i915->gmch.mch_res.start,
174 MCHBAR_SIZE, 0);
175 #endif
176 }
177
intel_gmch_vga_set_state(struct drm_i915_private * i915,bool enable_decode)178 int intel_gmch_vga_set_state(struct drm_i915_private *i915, bool enable_decode)
179 {
180 unsigned int reg = DISPLAY_VER(i915) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
181 u16 gmch_ctrl;
182
183 if (pci_read_config_word(i915->gmch.pdev, reg, &gmch_ctrl)) {
184 drm_err(&i915->drm, "failed to read control word\n");
185 return -EIO;
186 }
187
188 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !enable_decode)
189 return 0;
190
191 if (enable_decode)
192 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
193 else
194 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
195
196 if (pci_write_config_word(i915->gmch.pdev, reg, gmch_ctrl)) {
197 drm_err(&i915->drm, "failed to write control word\n");
198 return -EIO;
199 }
200
201 return 0;
202 }
203