1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <generated/autoconf.h>
27
28 /*
29 * Pre-requisites: headers required by header of this unit
30 */
31 #include "hw_translate_dcn30.h"
32
33 #include "dm_services.h"
34 #include "include/gpio_types.h"
35 #include "../hw_translate.h"
36
37
38 #include "sienna_cichlid_ip_offset.h"
39 #include "dcn/dcn_3_0_0_offset.h"
40 #include "dcn/dcn_3_0_0_sh_mask.h"
41
42 #include "nbio/nbio_7_4_offset.h"
43
44 #include "dpcs/dpcs_3_0_0_offset.h"
45 #include "dpcs/dpcs_3_0_0_sh_mask.h"
46
47 #include "mmhub/mmhub_2_0_0_offset.h"
48 #include "mmhub/mmhub_2_0_0_sh_mask.h"
49 /* begin *********************
50 * macros to expend register list macro defined in HW object header file */
51
52 /* DCN */
53 #define block HPD
54 #define reg_num 0
55
56 #undef BASE_INNER
57 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
58
59 #define BASE(seg) BASE_INNER(seg)
60
61 #undef REG
62 #define REG(reg_name)\
63 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
64 #define SF_HPD(reg_name, field_name, post_fix)\
65 .field_name = reg_name ## __ ## field_name ## post_fix
66
67
68 /* macros to expend register list macro defined in HW object header file
69 * end *********************/
70
71
offset_to_id(uint32_t offset,uint32_t mask,enum gpio_id * id,uint32_t * en)72 static bool offset_to_id(
73 uint32_t offset,
74 uint32_t mask,
75 enum gpio_id *id,
76 uint32_t *en)
77 {
78 switch (offset) {
79 /* GENERIC */
80 case REG(DC_GPIO_GENERIC_A):
81 *id = GPIO_ID_GENERIC;
82 switch (mask) {
83 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
84 *en = GPIO_GENERIC_A;
85 return true;
86 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK:
87 *en = GPIO_GENERIC_B;
88 return true;
89 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK:
90 *en = GPIO_GENERIC_C;
91 return true;
92 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK:
93 *en = GPIO_GENERIC_D;
94 return true;
95 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK:
96 *en = GPIO_GENERIC_E;
97 return true;
98 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK:
99 *en = GPIO_GENERIC_F;
100 return true;
101 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK:
102 *en = GPIO_GENERIC_G;
103 return true;
104 default:
105 ASSERT_CRITICAL(false);
106 return false;
107 }
108 break;
109 /* HPD */
110 case REG(DC_GPIO_HPD_A):
111 *id = GPIO_ID_HPD;
112 switch (mask) {
113 case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK:
114 *en = GPIO_HPD_1;
115 return true;
116 case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK:
117 *en = GPIO_HPD_2;
118 return true;
119 case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK:
120 *en = GPIO_HPD_3;
121 return true;
122 case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK:
123 *en = GPIO_HPD_4;
124 return true;
125 case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK:
126 *en = GPIO_HPD_5;
127 return true;
128 case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK:
129 *en = GPIO_HPD_6;
130 return true;
131 default:
132 ASSERT_CRITICAL(false);
133 return false;
134 }
135 break;
136 /* REG(DC_GPIO_GENLK_MASK */
137 case REG(DC_GPIO_GENLK_A):
138 *id = GPIO_ID_GSL;
139 switch (mask) {
140 case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK:
141 *en = GPIO_GSL_GENLOCK_CLOCK;
142 return true;
143 case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK:
144 *en = GPIO_GSL_GENLOCK_VSYNC;
145 return true;
146 case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK:
147 *en = GPIO_GSL_SWAPLOCK_A;
148 return true;
149 case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK:
150 *en = GPIO_GSL_SWAPLOCK_B;
151 return true;
152 default:
153 ASSERT_CRITICAL(false);
154 return false;
155 }
156 break;
157 /* DDC */
158 /* we don't care about the GPIO_ID for DDC
159 * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
160 * directly in the create method
161 */
162 case REG(DC_GPIO_DDC1_A):
163 *en = GPIO_DDC_LINE_DDC1;
164 return true;
165 case REG(DC_GPIO_DDC2_A):
166 *en = GPIO_DDC_LINE_DDC2;
167 return true;
168 case REG(DC_GPIO_DDC3_A):
169 *en = GPIO_DDC_LINE_DDC3;
170 return true;
171 case REG(DC_GPIO_DDC4_A):
172 *en = GPIO_DDC_LINE_DDC4;
173 return true;
174 case REG(DC_GPIO_DDC5_A):
175 *en = GPIO_DDC_LINE_DDC5;
176 return true;
177 case REG(DC_GPIO_DDC6_A):
178 *en = GPIO_DDC_LINE_DDC6;
179 return true;
180 case REG(DC_GPIO_DDCVGA_A):
181 *en = GPIO_DDC_LINE_DDC_VGA;
182 return true;
183
184 /*
185 * case REG(DC_GPIO_I2CPAD_A): not exit
186 * case REG(DC_GPIO_PWRSEQ_A):
187 * case REG(DC_GPIO_PAD_STRENGTH_1):
188 * case REG(DC_GPIO_PAD_STRENGTH_2):
189 * case REG(DC_GPIO_DEBUG):
190 */
191 /* UNEXPECTED */
192 default:
193 /* case REG(DC_GPIO_SYNCA_A): not exist */
194 ASSERT_CRITICAL(false);
195 return false;
196 }
197 }
198
id_to_offset(enum gpio_id id,uint32_t en,struct gpio_pin_info * info)199 static bool id_to_offset(
200 enum gpio_id id,
201 uint32_t en,
202 struct gpio_pin_info *info)
203 {
204 bool result = true;
205
206 switch (id) {
207 case GPIO_ID_DDC_DATA:
208 info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK;
209 switch (en) {
210 case GPIO_DDC_LINE_DDC1:
211 info->offset = REG(DC_GPIO_DDC1_A);
212 break;
213 case GPIO_DDC_LINE_DDC2:
214 info->offset = REG(DC_GPIO_DDC2_A);
215 break;
216 case GPIO_DDC_LINE_DDC3:
217 info->offset = REG(DC_GPIO_DDC3_A);
218 break;
219 case GPIO_DDC_LINE_DDC4:
220 info->offset = REG(DC_GPIO_DDC4_A);
221 break;
222 case GPIO_DDC_LINE_DDC5:
223 info->offset = REG(DC_GPIO_DDC5_A);
224 break;
225 case GPIO_DDC_LINE_DDC6:
226 info->offset = REG(DC_GPIO_DDC6_A);
227 break;
228 case GPIO_DDC_LINE_DDC_VGA:
229 info->offset = REG(DC_GPIO_DDCVGA_A);
230 break;
231 case GPIO_DDC_LINE_I2C_PAD:
232 default:
233 ASSERT_CRITICAL(false);
234 result = false;
235 }
236 break;
237 case GPIO_ID_DDC_CLOCK:
238 info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK;
239 switch (en) {
240 case GPIO_DDC_LINE_DDC1:
241 info->offset = REG(DC_GPIO_DDC1_A);
242 break;
243 case GPIO_DDC_LINE_DDC2:
244 info->offset = REG(DC_GPIO_DDC2_A);
245 break;
246 case GPIO_DDC_LINE_DDC3:
247 info->offset = REG(DC_GPIO_DDC3_A);
248 break;
249 case GPIO_DDC_LINE_DDC4:
250 info->offset = REG(DC_GPIO_DDC4_A);
251 break;
252 case GPIO_DDC_LINE_DDC5:
253 info->offset = REG(DC_GPIO_DDC5_A);
254 break;
255 case GPIO_DDC_LINE_DDC6:
256 info->offset = REG(DC_GPIO_DDC6_A);
257 break;
258 case GPIO_DDC_LINE_DDC_VGA:
259 info->offset = REG(DC_GPIO_DDCVGA_A);
260 break;
261 case GPIO_DDC_LINE_I2C_PAD:
262 default:
263 ASSERT_CRITICAL(false);
264 result = false;
265 }
266 break;
267 case GPIO_ID_GENERIC:
268 info->offset = REG(DC_GPIO_GENERIC_A);
269 switch (en) {
270 case GPIO_GENERIC_A:
271 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;
272 break;
273 case GPIO_GENERIC_B:
274 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;
275 break;
276 case GPIO_GENERIC_C:
277 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;
278 break;
279 case GPIO_GENERIC_D:
280 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;
281 break;
282 case GPIO_GENERIC_E:
283 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;
284 break;
285 case GPIO_GENERIC_F:
286 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;
287 break;
288 case GPIO_GENERIC_G:
289 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;
290 break;
291 default:
292 ASSERT_CRITICAL(false);
293 result = false;
294 }
295 break;
296 case GPIO_ID_HPD:
297 info->offset = REG(DC_GPIO_HPD_A);
298 switch (en) {
299 case GPIO_HPD_1:
300 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
301 break;
302 case GPIO_HPD_2:
303 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;
304 break;
305 case GPIO_HPD_3:
306 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;
307 break;
308 case GPIO_HPD_4:
309 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;
310 break;
311 case GPIO_HPD_5:
312 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;
313 break;
314 case GPIO_HPD_6:
315 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;
316 break;
317 default:
318 ASSERT_CRITICAL(false);
319 result = false;
320 }
321 break;
322 case GPIO_ID_GSL:
323 switch (en) {
324 case GPIO_GSL_GENLOCK_CLOCK:
325 /*not implmented*/
326 ASSERT_CRITICAL(false);
327 result = false;
328 break;
329 case GPIO_GSL_GENLOCK_VSYNC:
330 /*not implmented*/
331 ASSERT_CRITICAL(false);
332 result = false;
333 break;
334 case GPIO_GSL_SWAPLOCK_A:
335 /*not implmented*/
336 ASSERT_CRITICAL(false);
337 result = false;
338 break;
339 case GPIO_GSL_SWAPLOCK_B:
340 /*not implmented*/
341 ASSERT_CRITICAL(false);
342 result = false;
343
344 break;
345 default:
346 ASSERT_CRITICAL(false);
347 result = false;
348 }
349 break;
350 case GPIO_ID_SYNC:
351 case GPIO_ID_VIP_PAD:
352 default:
353 ASSERT_CRITICAL(false);
354 result = false;
355 }
356
357 if (result) {
358 info->offset_y = info->offset + 2;
359 info->offset_en = info->offset + 1;
360 info->offset_mask = info->offset - 1;
361
362 info->mask_y = info->mask;
363 info->mask_en = info->mask;
364 info->mask_mask = info->mask;
365 }
366
367 return result;
368 }
369
370 /* function table */
371 static const struct hw_translate_funcs funcs = {
372 .offset_to_id = offset_to_id,
373 .id_to_offset = id_to_offset,
374 };
375
376 /*
377 * dal_hw_translate_dcn30_init
378 *
379 * @brief
380 * Initialize Hw translate function pointers.
381 *
382 * @param
383 * struct hw_translate *tr - [out] struct of function pointers
384 *
385 */
dal_hw_translate_dcn30_init(struct hw_translate * tr)386 void dal_hw_translate_dcn30_init(struct hw_translate *tr)
387 {
388 tr->funcs = &funcs;
389 }
390
391