1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "gc/gc_9_0_sh_mask.h" 35 #include "dce/dce_12_0_offset.h" 36 #include "dce/dce_12_0_sh_mask.h" 37 #include "vega10_enum.h" 38 #include "mmhub/mmhub_1_0_offset.h" 39 #include "athub/athub_1_0_sh_mask.h" 40 #include "athub/athub_1_0_offset.h" 41 #include "oss/osssys_4_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15d.h" 45 #include "soc15_common.h" 46 #include "umc/umc_6_0_sh_mask.h" 47 48 #include "gfxhub_v1_0.h" 49 #include "mmhub_v1_0.h" 50 #include "athub_v1_0.h" 51 #include "gfxhub_v1_1.h" 52 #include "gfxhub_v1_2.h" 53 #include "mmhub_v9_4.h" 54 #include "mmhub_v1_7.h" 55 #include "mmhub_v1_8.h" 56 #include "umc_v6_1.h" 57 #include "umc_v6_0.h" 58 #include "umc_v6_7.h" 59 #include "hdp_v4_0.h" 60 #include "mca_v3_0.h" 61 62 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 63 64 #include "amdgpu_ras.h" 65 #include "amdgpu_xgmi.h" 66 67 #include "amdgpu_reset.h" 68 69 /* add these here since we already include dce12 headers and these are for DCN */ 70 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 71 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 72 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 73 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 74 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 75 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 76 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d 77 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 78 79 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea 80 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2 81 82 #define MAX_MEM_RANGES 8 83 84 static const char * const gfxhub_client_ids[] = { 85 "CB", 86 "DB", 87 "IA", 88 "WD", 89 "CPF", 90 "CPC", 91 "CPG", 92 "RLC", 93 "TCP", 94 "SQC (inst)", 95 "SQC (data)", 96 "SQG", 97 "PA", 98 }; 99 100 static const char *mmhub_client_ids_raven[][2] = { 101 [0][0] = "MP1", 102 [1][0] = "MP0", 103 [2][0] = "VCN", 104 [3][0] = "VCNU", 105 [4][0] = "HDP", 106 [5][0] = "DCE", 107 [13][0] = "UTCL2", 108 [19][0] = "TLS", 109 [26][0] = "OSS", 110 [27][0] = "SDMA0", 111 [0][1] = "MP1", 112 [1][1] = "MP0", 113 [2][1] = "VCN", 114 [3][1] = "VCNU", 115 [4][1] = "HDP", 116 [5][1] = "XDP", 117 [6][1] = "DBGU0", 118 [7][1] = "DCE", 119 [8][1] = "DCEDWB0", 120 [9][1] = "DCEDWB1", 121 [26][1] = "OSS", 122 [27][1] = "SDMA0", 123 }; 124 125 static const char *mmhub_client_ids_renoir[][2] = { 126 [0][0] = "MP1", 127 [1][0] = "MP0", 128 [2][0] = "HDP", 129 [4][0] = "DCEDMC", 130 [5][0] = "DCEVGA", 131 [13][0] = "UTCL2", 132 [19][0] = "TLS", 133 [26][0] = "OSS", 134 [27][0] = "SDMA0", 135 [28][0] = "VCN", 136 [29][0] = "VCNU", 137 [30][0] = "JPEG", 138 [0][1] = "MP1", 139 [1][1] = "MP0", 140 [2][1] = "HDP", 141 [3][1] = "XDP", 142 [6][1] = "DBGU0", 143 [7][1] = "DCEDMC", 144 [8][1] = "DCEVGA", 145 [9][1] = "DCEDWB", 146 [26][1] = "OSS", 147 [27][1] = "SDMA0", 148 [28][1] = "VCN", 149 [29][1] = "VCNU", 150 [30][1] = "JPEG", 151 }; 152 153 static const char *mmhub_client_ids_vega10[][2] = { 154 [0][0] = "MP0", 155 [1][0] = "UVD", 156 [2][0] = "UVDU", 157 [3][0] = "HDP", 158 [13][0] = "UTCL2", 159 [14][0] = "OSS", 160 [15][0] = "SDMA1", 161 [32+0][0] = "VCE0", 162 [32+1][0] = "VCE0U", 163 [32+2][0] = "XDMA", 164 [32+3][0] = "DCE", 165 [32+4][0] = "MP1", 166 [32+14][0] = "SDMA0", 167 [0][1] = "MP0", 168 [1][1] = "UVD", 169 [2][1] = "UVDU", 170 [3][1] = "DBGU0", 171 [4][1] = "HDP", 172 [5][1] = "XDP", 173 [14][1] = "OSS", 174 [15][1] = "SDMA0", 175 [32+0][1] = "VCE0", 176 [32+1][1] = "VCE0U", 177 [32+2][1] = "XDMA", 178 [32+3][1] = "DCE", 179 [32+4][1] = "DCEDWB", 180 [32+5][1] = "MP1", 181 [32+6][1] = "DBGU1", 182 [32+14][1] = "SDMA1", 183 }; 184 185 static const char *mmhub_client_ids_vega12[][2] = { 186 [0][0] = "MP0", 187 [1][0] = "VCE0", 188 [2][0] = "VCE0U", 189 [3][0] = "HDP", 190 [13][0] = "UTCL2", 191 [14][0] = "OSS", 192 [15][0] = "SDMA1", 193 [32+0][0] = "DCE", 194 [32+1][0] = "XDMA", 195 [32+2][0] = "UVD", 196 [32+3][0] = "UVDU", 197 [32+4][0] = "MP1", 198 [32+15][0] = "SDMA0", 199 [0][1] = "MP0", 200 [1][1] = "VCE0", 201 [2][1] = "VCE0U", 202 [3][1] = "DBGU0", 203 [4][1] = "HDP", 204 [5][1] = "XDP", 205 [14][1] = "OSS", 206 [15][1] = "SDMA0", 207 [32+0][1] = "DCE", 208 [32+1][1] = "DCEDWB", 209 [32+2][1] = "XDMA", 210 [32+3][1] = "UVD", 211 [32+4][1] = "UVDU", 212 [32+5][1] = "MP1", 213 [32+6][1] = "DBGU1", 214 [32+15][1] = "SDMA1", 215 }; 216 217 static const char *mmhub_client_ids_vega20[][2] = { 218 [0][0] = "XDMA", 219 [1][0] = "DCE", 220 [2][0] = "VCE0", 221 [3][0] = "VCE0U", 222 [4][0] = "UVD", 223 [5][0] = "UVD1U", 224 [13][0] = "OSS", 225 [14][0] = "HDP", 226 [15][0] = "SDMA0", 227 [32+0][0] = "UVD", 228 [32+1][0] = "UVDU", 229 [32+2][0] = "MP1", 230 [32+3][0] = "MP0", 231 [32+12][0] = "UTCL2", 232 [32+14][0] = "SDMA1", 233 [0][1] = "XDMA", 234 [1][1] = "DCE", 235 [2][1] = "DCEDWB", 236 [3][1] = "VCE0", 237 [4][1] = "VCE0U", 238 [5][1] = "UVD1", 239 [6][1] = "UVD1U", 240 [7][1] = "DBGU0", 241 [8][1] = "XDP", 242 [13][1] = "OSS", 243 [14][1] = "HDP", 244 [15][1] = "SDMA0", 245 [32+0][1] = "UVD", 246 [32+1][1] = "UVDU", 247 [32+2][1] = "DBGU1", 248 [32+3][1] = "MP1", 249 [32+4][1] = "MP0", 250 [32+14][1] = "SDMA1", 251 }; 252 253 static const char *mmhub_client_ids_arcturus[][2] = { 254 [0][0] = "DBGU1", 255 [1][0] = "XDP", 256 [2][0] = "MP1", 257 [14][0] = "HDP", 258 [171][0] = "JPEG", 259 [172][0] = "VCN", 260 [173][0] = "VCNU", 261 [203][0] = "JPEG1", 262 [204][0] = "VCN1", 263 [205][0] = "VCN1U", 264 [256][0] = "SDMA0", 265 [257][0] = "SDMA1", 266 [258][0] = "SDMA2", 267 [259][0] = "SDMA3", 268 [260][0] = "SDMA4", 269 [261][0] = "SDMA5", 270 [262][0] = "SDMA6", 271 [263][0] = "SDMA7", 272 [384][0] = "OSS", 273 [0][1] = "DBGU1", 274 [1][1] = "XDP", 275 [2][1] = "MP1", 276 [14][1] = "HDP", 277 [171][1] = "JPEG", 278 [172][1] = "VCN", 279 [173][1] = "VCNU", 280 [203][1] = "JPEG1", 281 [204][1] = "VCN1", 282 [205][1] = "VCN1U", 283 [256][1] = "SDMA0", 284 [257][1] = "SDMA1", 285 [258][1] = "SDMA2", 286 [259][1] = "SDMA3", 287 [260][1] = "SDMA4", 288 [261][1] = "SDMA5", 289 [262][1] = "SDMA6", 290 [263][1] = "SDMA7", 291 [384][1] = "OSS", 292 }; 293 294 static const char *mmhub_client_ids_aldebaran[][2] = { 295 [2][0] = "MP1", 296 [3][0] = "MP0", 297 [32+1][0] = "DBGU_IO0", 298 [32+2][0] = "DBGU_IO2", 299 [32+4][0] = "MPIO", 300 [96+11][0] = "JPEG0", 301 [96+12][0] = "VCN0", 302 [96+13][0] = "VCNU0", 303 [128+11][0] = "JPEG1", 304 [128+12][0] = "VCN1", 305 [128+13][0] = "VCNU1", 306 [160+1][0] = "XDP", 307 [160+14][0] = "HDP", 308 [256+0][0] = "SDMA0", 309 [256+1][0] = "SDMA1", 310 [256+2][0] = "SDMA2", 311 [256+3][0] = "SDMA3", 312 [256+4][0] = "SDMA4", 313 [384+0][0] = "OSS", 314 [2][1] = "MP1", 315 [3][1] = "MP0", 316 [32+1][1] = "DBGU_IO0", 317 [32+2][1] = "DBGU_IO2", 318 [32+4][1] = "MPIO", 319 [96+11][1] = "JPEG0", 320 [96+12][1] = "VCN0", 321 [96+13][1] = "VCNU0", 322 [128+11][1] = "JPEG1", 323 [128+12][1] = "VCN1", 324 [128+13][1] = "VCNU1", 325 [160+1][1] = "XDP", 326 [160+14][1] = "HDP", 327 [256+0][1] = "SDMA0", 328 [256+1][1] = "SDMA1", 329 [256+2][1] = "SDMA2", 330 [256+3][1] = "SDMA3", 331 [256+4][1] = "SDMA4", 332 [384+0][1] = "OSS", 333 }; 334 335 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = { 336 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 337 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 338 }; 339 340 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = { 341 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 342 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 343 }; 344 345 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 346 (0x000143c0 + 0x00000000), 347 (0x000143c0 + 0x00000800), 348 (0x000143c0 + 0x00001000), 349 (0x000143c0 + 0x00001800), 350 (0x000543c0 + 0x00000000), 351 (0x000543c0 + 0x00000800), 352 (0x000543c0 + 0x00001000), 353 (0x000543c0 + 0x00001800), 354 (0x000943c0 + 0x00000000), 355 (0x000943c0 + 0x00000800), 356 (0x000943c0 + 0x00001000), 357 (0x000943c0 + 0x00001800), 358 (0x000d43c0 + 0x00000000), 359 (0x000d43c0 + 0x00000800), 360 (0x000d43c0 + 0x00001000), 361 (0x000d43c0 + 0x00001800), 362 (0x001143c0 + 0x00000000), 363 (0x001143c0 + 0x00000800), 364 (0x001143c0 + 0x00001000), 365 (0x001143c0 + 0x00001800), 366 (0x001543c0 + 0x00000000), 367 (0x001543c0 + 0x00000800), 368 (0x001543c0 + 0x00001000), 369 (0x001543c0 + 0x00001800), 370 (0x001943c0 + 0x00000000), 371 (0x001943c0 + 0x00000800), 372 (0x001943c0 + 0x00001000), 373 (0x001943c0 + 0x00001800), 374 (0x001d43c0 + 0x00000000), 375 (0x001d43c0 + 0x00000800), 376 (0x001d43c0 + 0x00001000), 377 (0x001d43c0 + 0x00001800), 378 }; 379 380 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 381 (0x000143e0 + 0x00000000), 382 (0x000143e0 + 0x00000800), 383 (0x000143e0 + 0x00001000), 384 (0x000143e0 + 0x00001800), 385 (0x000543e0 + 0x00000000), 386 (0x000543e0 + 0x00000800), 387 (0x000543e0 + 0x00001000), 388 (0x000543e0 + 0x00001800), 389 (0x000943e0 + 0x00000000), 390 (0x000943e0 + 0x00000800), 391 (0x000943e0 + 0x00001000), 392 (0x000943e0 + 0x00001800), 393 (0x000d43e0 + 0x00000000), 394 (0x000d43e0 + 0x00000800), 395 (0x000d43e0 + 0x00001000), 396 (0x000d43e0 + 0x00001800), 397 (0x001143e0 + 0x00000000), 398 (0x001143e0 + 0x00000800), 399 (0x001143e0 + 0x00001000), 400 (0x001143e0 + 0x00001800), 401 (0x001543e0 + 0x00000000), 402 (0x001543e0 + 0x00000800), 403 (0x001543e0 + 0x00001000), 404 (0x001543e0 + 0x00001800), 405 (0x001943e0 + 0x00000000), 406 (0x001943e0 + 0x00000800), 407 (0x001943e0 + 0x00001000), 408 (0x001943e0 + 0x00001800), 409 (0x001d43e0 + 0x00000000), 410 (0x001d43e0 + 0x00000800), 411 (0x001d43e0 + 0x00001000), 412 (0x001d43e0 + 0x00001800), 413 }; 414 415 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 416 struct amdgpu_irq_src *src, 417 unsigned int type, 418 enum amdgpu_interrupt_state state) 419 { 420 u32 bits, i, tmp, reg; 421 422 /* Devices newer then VEGA10/12 shall have these programming 423 * sequences performed by PSP BL 424 */ 425 if (adev->asic_type >= CHIP_VEGA20) 426 return 0; 427 428 bits = 0x7f; 429 430 switch (state) { 431 case AMDGPU_IRQ_STATE_DISABLE: 432 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 433 reg = ecc_umc_mcumc_ctrl_addrs[i]; 434 tmp = RREG32(reg); 435 tmp &= ~bits; 436 WREG32(reg, tmp); 437 } 438 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 439 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 440 tmp = RREG32(reg); 441 tmp &= ~bits; 442 WREG32(reg, tmp); 443 } 444 break; 445 case AMDGPU_IRQ_STATE_ENABLE: 446 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 447 reg = ecc_umc_mcumc_ctrl_addrs[i]; 448 tmp = RREG32(reg); 449 tmp |= bits; 450 WREG32(reg, tmp); 451 } 452 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 453 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 454 tmp = RREG32(reg); 455 tmp |= bits; 456 WREG32(reg, tmp); 457 } 458 break; 459 default: 460 break; 461 } 462 463 return 0; 464 } 465 466 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 467 struct amdgpu_irq_src *src, 468 unsigned int type, 469 enum amdgpu_interrupt_state state) 470 { 471 struct amdgpu_vmhub *hub; 472 u32 tmp, reg, bits, i, j; 473 474 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 475 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 476 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 477 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 478 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 479 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 480 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 481 482 switch (state) { 483 case AMDGPU_IRQ_STATE_DISABLE: 484 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 485 hub = &adev->vmhub[j]; 486 for (i = 0; i < 16; i++) { 487 reg = hub->vm_context0_cntl + i; 488 489 /* This works because this interrupt is only 490 * enabled at init/resume and disabled in 491 * fini/suspend, so the overall state doesn't 492 * change over the course of suspend/resume. 493 */ 494 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 495 continue; 496 497 if (j >= AMDGPU_MMHUB0(0)) 498 tmp = RREG32_SOC15_IP(MMHUB, reg); 499 else 500 tmp = RREG32_SOC15_IP(GC, reg); 501 502 tmp &= ~bits; 503 504 if (j >= AMDGPU_MMHUB0(0)) 505 WREG32_SOC15_IP(MMHUB, reg, tmp); 506 else 507 WREG32_SOC15_IP(GC, reg, tmp); 508 } 509 } 510 break; 511 case AMDGPU_IRQ_STATE_ENABLE: 512 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 513 hub = &adev->vmhub[j]; 514 for (i = 0; i < 16; i++) { 515 reg = hub->vm_context0_cntl + i; 516 517 /* This works because this interrupt is only 518 * enabled at init/resume and disabled in 519 * fini/suspend, so the overall state doesn't 520 * change over the course of suspend/resume. 521 */ 522 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 523 continue; 524 525 if (j >= AMDGPU_MMHUB0(0)) 526 tmp = RREG32_SOC15_IP(MMHUB, reg); 527 else 528 tmp = RREG32_SOC15_IP(GC, reg); 529 530 tmp |= bits; 531 532 if (j >= AMDGPU_MMHUB0(0)) 533 WREG32_SOC15_IP(MMHUB, reg, tmp); 534 else 535 WREG32_SOC15_IP(GC, reg, tmp); 536 } 537 } 538 break; 539 default: 540 break; 541 } 542 543 return 0; 544 } 545 546 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 547 struct amdgpu_irq_src *source, 548 struct amdgpu_iv_entry *entry) 549 { 550 bool retry_fault = !!(entry->src_data[1] & 0x80); 551 bool write_fault = !!(entry->src_data[1] & 0x20); 552 uint32_t status = 0, cid = 0, rw = 0; 553 struct amdgpu_task_info task_info; 554 struct amdgpu_vmhub *hub; 555 const char *mmhub_cid; 556 const char *hub_name; 557 u64 addr; 558 uint32_t cam_index = 0; 559 int ret, xcc_id = 0; 560 uint32_t node_id; 561 562 node_id = entry->node_id; 563 564 addr = (u64)entry->src_data[0] << 12; 565 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 566 567 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 568 hub_name = "mmhub0"; 569 hub = &adev->vmhub[AMDGPU_MMHUB0(node_id / 4)]; 570 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 571 hub_name = "mmhub1"; 572 hub = &adev->vmhub[AMDGPU_MMHUB1(0)]; 573 } else { 574 hub_name = "gfxhub0"; 575 if (adev->gfx.funcs->ih_node_to_logical_xcc) { 576 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev, 577 node_id); 578 if (xcc_id < 0) 579 xcc_id = 0; 580 } 581 hub = &adev->vmhub[xcc_id]; 582 } 583 584 if (retry_fault) { 585 if (adev->irq.retry_cam_enabled) { 586 /* Delegate it to a different ring if the hardware hasn't 587 * already done it. 588 */ 589 if (entry->ih == &adev->irq.ih) { 590 amdgpu_irq_delegate(adev, entry, 8); 591 return 1; 592 } 593 594 cam_index = entry->src_data[2] & 0x3ff; 595 596 ret = amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 597 addr, write_fault); 598 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); 599 if (ret) 600 return 1; 601 } else { 602 /* Process it onyl if it's the first fault for this address */ 603 if (entry->ih != &adev->irq.ih_soft && 604 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 605 entry->timestamp)) 606 return 1; 607 608 /* Delegate it to a different ring if the hardware hasn't 609 * already done it. 610 */ 611 if (entry->ih == &adev->irq.ih) { 612 amdgpu_irq_delegate(adev, entry, 8); 613 return 1; 614 } 615 616 /* Try to handle the recoverable page faults by filling page 617 * tables 618 */ 619 if (amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 620 addr, write_fault)) 621 return 1; 622 } 623 } 624 625 if (!printk_ratelimit()) 626 return 0; 627 628 629 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 630 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 631 632 dev_err(adev->dev, 633 "[%s] %s page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d)\n", 634 hub_name, retry_fault ? "retry" : "no-retry", 635 entry->src_id, entry->ring_id, entry->vmid, 636 entry->pasid, task_info.process_name, task_info.tgid, 637 task_info.task_name, task_info.pid); 638 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n", 639 addr, entry->client_id, 640 soc15_ih_clientid_name[entry->client_id]); 641 642 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) 643 dev_err(adev->dev, " cookie node_id %d fault from die %s%d%s\n", 644 node_id, node_id % 4 == 3 ? "RSV" : "AID", node_id / 4, 645 node_id % 4 == 1 ? ".XCD0" : node_id % 4 == 2 ? ".XCD1" : ""); 646 647 if (amdgpu_sriov_vf(adev)) 648 return 0; 649 650 /* 651 * Issue a dummy read to wait for the status register to 652 * be updated to avoid reading an incorrect value due to 653 * the new fast GRBM interface. 654 */ 655 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) && 656 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) 657 RREG32(hub->vm_l2_pro_fault_status); 658 659 status = RREG32(hub->vm_l2_pro_fault_status); 660 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID); 661 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW); 662 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 663 664 dev_err(adev->dev, 665 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 666 status); 667 if (entry->vmid_src == AMDGPU_GFXHUB(0)) { 668 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 669 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : 670 gfxhub_client_ids[cid], 671 cid); 672 } else { 673 switch (adev->ip_versions[MMHUB_HWIP][0]) { 674 case IP_VERSION(9, 0, 0): 675 mmhub_cid = mmhub_client_ids_vega10[cid][rw]; 676 break; 677 case IP_VERSION(9, 3, 0): 678 mmhub_cid = mmhub_client_ids_vega12[cid][rw]; 679 break; 680 case IP_VERSION(9, 4, 0): 681 mmhub_cid = mmhub_client_ids_vega20[cid][rw]; 682 break; 683 case IP_VERSION(9, 4, 1): 684 mmhub_cid = mmhub_client_ids_arcturus[cid][rw]; 685 break; 686 case IP_VERSION(9, 1, 0): 687 case IP_VERSION(9, 2, 0): 688 mmhub_cid = mmhub_client_ids_raven[cid][rw]; 689 break; 690 case IP_VERSION(1, 5, 0): 691 case IP_VERSION(2, 4, 0): 692 mmhub_cid = mmhub_client_ids_renoir[cid][rw]; 693 break; 694 case IP_VERSION(1, 8, 0): 695 case IP_VERSION(9, 4, 2): 696 mmhub_cid = mmhub_client_ids_aldebaran[cid][rw]; 697 break; 698 default: 699 mmhub_cid = NULL; 700 break; 701 } 702 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 703 mmhub_cid ? mmhub_cid : "unknown", cid); 704 } 705 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 706 REG_GET_FIELD(status, 707 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 708 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 709 REG_GET_FIELD(status, 710 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 711 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 712 REG_GET_FIELD(status, 713 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 714 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 715 REG_GET_FIELD(status, 716 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 717 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 718 return 0; 719 } 720 721 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 722 .set = gmc_v9_0_vm_fault_interrupt_state, 723 .process = gmc_v9_0_process_interrupt, 724 }; 725 726 727 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 728 .set = gmc_v9_0_ecc_interrupt_state, 729 .process = amdgpu_umc_process_ecc_irq, 730 }; 731 732 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 733 { 734 adev->gmc.vm_fault.num_types = 1; 735 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 736 737 if (!amdgpu_sriov_vf(adev) && 738 !adev->gmc.xgmi.connected_to_cpu) { 739 adev->gmc.ecc_irq.num_types = 1; 740 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 741 } 742 } 743 744 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 745 uint32_t flush_type) 746 { 747 u32 req = 0; 748 749 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 750 PER_VMID_INVALIDATE_REQ, 1 << vmid); 751 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 752 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 753 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 754 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 755 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 756 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 757 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 758 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 759 760 return req; 761 } 762 763 /** 764 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore 765 * 766 * @adev: amdgpu_device pointer 767 * @vmhub: vmhub type 768 * 769 */ 770 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, 771 uint32_t vmhub) 772 { 773 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || 774 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) 775 return false; 776 777 return ((vmhub == AMDGPU_MMHUB0(0) || 778 vmhub == AMDGPU_MMHUB1(0)) && 779 (!amdgpu_sriov_vf(adev)) && 780 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) && 781 (adev->apu_flags & AMD_APU_IS_PICASSO)))); 782 } 783 784 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 785 uint8_t vmid, uint16_t *p_pasid) 786 { 787 uint32_t value; 788 789 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 790 + vmid); 791 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 792 793 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 794 } 795 796 /* 797 * GART 798 * VMID 0 is the physical GPU addresses as used by the kernel. 799 * VMIDs 1-15 are used for userspace clients and are handled 800 * by the amdgpu vm/hsa code. 801 */ 802 803 /** 804 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 805 * 806 * @adev: amdgpu_device pointer 807 * @vmid: vm instance to flush 808 * @vmhub: which hub to flush 809 * @flush_type: the flush type 810 * 811 * Flush the TLB for the requested page table using certain type. 812 */ 813 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 814 uint32_t vmhub, uint32_t flush_type) 815 { 816 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); 817 const unsigned int eng = 17; 818 u32 j, inv_req, inv_req2, tmp; 819 struct amdgpu_vmhub *hub; 820 821 BUG_ON(vmhub >= AMDGPU_MAX_VMHUBS); 822 823 hub = &adev->vmhub[vmhub]; 824 if (adev->gmc.xgmi.num_physical_nodes && 825 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)) { 826 /* Vega20+XGMI caches PTEs in TC and TLB. Add a 827 * heavy-weight TLB flush (type 2), which flushes 828 * both. Due to a race condition with concurrent 829 * memory accesses using the same TLB cache line, we 830 * still need a second TLB flush after this. 831 */ 832 inv_req = gmc_v9_0_get_invalidate_req(vmid, 2); 833 inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type); 834 } else if (flush_type == 2 && 835 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3) && 836 adev->rev_id == 0) { 837 inv_req = gmc_v9_0_get_invalidate_req(vmid, 0); 838 inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type); 839 } else { 840 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); 841 inv_req2 = 0; 842 } 843 844 /* This is necessary for a HW workaround under SRIOV as well 845 * as GFXOFF under bare metal 846 */ 847 if (adev->gfx.kiq[0].ring.sched.ready && 848 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 849 down_read_trylock(&adev->reset_domain->sem)) { 850 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 851 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 852 853 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 854 1 << vmid); 855 up_read(&adev->reset_domain->sem); 856 return; 857 } 858 859 spin_lock(&adev->gmc.invalidate_lock); 860 861 /* 862 * It may lose gpuvm invalidate acknowldege state across power-gating 863 * off cycle, add semaphore acquire before invalidation and semaphore 864 * release after invalidation to avoid entering power gated state 865 * to WA the Issue 866 */ 867 868 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 869 if (use_semaphore) { 870 for (j = 0; j < adev->usec_timeout; j++) { 871 /* a read return value of 1 means semaphore acquire */ 872 if (vmhub >= AMDGPU_MMHUB0(0)) 873 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng); 874 else 875 tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng); 876 if (tmp & 0x1) 877 break; 878 udelay(1); 879 } 880 881 if (j >= adev->usec_timeout) 882 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 883 } 884 885 do { 886 if (vmhub >= AMDGPU_MMHUB0(0)) 887 WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); 888 else 889 WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); 890 891 /* 892 * Issue a dummy read to wait for the ACK register to 893 * be cleared to avoid a false ACK due to the new fast 894 * GRBM interface. 895 */ 896 if ((vmhub == AMDGPU_GFXHUB(0)) && 897 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) 898 RREG32_NO_KIQ(hub->vm_inv_eng0_req + 899 hub->eng_distance * eng); 900 901 for (j = 0; j < adev->usec_timeout; j++) { 902 if (vmhub >= AMDGPU_MMHUB0(0)) 903 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_ack + hub->eng_distance * eng); 904 else 905 tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_ack + hub->eng_distance * eng); 906 if (tmp & (1 << vmid)) 907 break; 908 udelay(1); 909 } 910 911 inv_req = inv_req2; 912 inv_req2 = 0; 913 } while (inv_req); 914 915 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 916 if (use_semaphore) { 917 /* 918 * add semaphore release after invalidation, 919 * write with 0 means semaphore release 920 */ 921 if (vmhub >= AMDGPU_MMHUB0(0)) 922 WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0); 923 else 924 WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0); 925 } 926 927 spin_unlock(&adev->gmc.invalidate_lock); 928 929 if (j < adev->usec_timeout) 930 return; 931 932 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 933 } 934 935 /** 936 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid 937 * 938 * @adev: amdgpu_device pointer 939 * @pasid: pasid to be flush 940 * @flush_type: the flush type 941 * @all_hub: flush all hubs 942 * @inst: is used to select which instance of KIQ to use for the invalidation 943 * 944 * Flush the TLB for the requested pasid. 945 */ 946 static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 947 uint16_t pasid, uint32_t flush_type, 948 bool all_hub, uint32_t inst) 949 { 950 int vmid, i; 951 signed long r; 952 uint32_t seq; 953 uint16_t queried_pasid; 954 bool ret; 955 u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : adev->usec_timeout; 956 struct amdgpu_ring *ring = &adev->gfx.kiq[inst].ring; 957 struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst]; 958 959 if (amdgpu_in_reset(adev)) 960 return -EIO; 961 962 if (ring->sched.ready && down_read_trylock(&adev->reset_domain->sem)) { 963 /* Vega20+XGMI caches PTEs in TC and TLB. Add a 964 * heavy-weight TLB flush (type 2), which flushes 965 * both. Due to a race condition with concurrent 966 * memory accesses using the same TLB cache line, we 967 * still need a second TLB flush after this. 968 */ 969 bool vega20_xgmi_wa = (adev->gmc.xgmi.num_physical_nodes && 970 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)); 971 /* 2 dwords flush + 8 dwords fence */ 972 unsigned int ndw = kiq->pmf->invalidate_tlbs_size + 8; 973 974 if (vega20_xgmi_wa) 975 ndw += kiq->pmf->invalidate_tlbs_size; 976 977 spin_lock(&adev->gfx.kiq[inst].ring_lock); 978 /* 2 dwords flush + 8 dwords fence */ 979 amdgpu_ring_alloc(ring, ndw); 980 if (vega20_xgmi_wa) 981 kiq->pmf->kiq_invalidate_tlbs(ring, 982 pasid, 2, all_hub); 983 984 if (flush_type == 2 && 985 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3) && 986 adev->rev_id == 0) 987 kiq->pmf->kiq_invalidate_tlbs(ring, 988 pasid, 0, all_hub); 989 990 kiq->pmf->kiq_invalidate_tlbs(ring, 991 pasid, flush_type, all_hub); 992 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 993 if (r) { 994 amdgpu_ring_undo(ring); 995 spin_unlock(&adev->gfx.kiq[inst].ring_lock); 996 up_read(&adev->reset_domain->sem); 997 return -ETIME; 998 } 999 1000 amdgpu_ring_commit(ring); 1001 spin_unlock(&adev->gfx.kiq[inst].ring_lock); 1002 r = amdgpu_fence_wait_polling(ring, seq, usec_timeout); 1003 if (r < 1) { 1004 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 1005 up_read(&adev->reset_domain->sem); 1006 return -ETIME; 1007 } 1008 up_read(&adev->reset_domain->sem); 1009 return 0; 1010 } 1011 1012 for (vmid = 1; vmid < 16; vmid++) { 1013 1014 ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 1015 &queried_pasid); 1016 if (ret && queried_pasid == pasid) { 1017 if (all_hub) { 1018 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) 1019 gmc_v9_0_flush_gpu_tlb(adev, vmid, 1020 i, flush_type); 1021 } else { 1022 gmc_v9_0_flush_gpu_tlb(adev, vmid, 1023 AMDGPU_GFXHUB(0), flush_type); 1024 } 1025 break; 1026 } 1027 } 1028 1029 return 0; 1030 1031 } 1032 1033 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 1034 unsigned int vmid, uint64_t pd_addr) 1035 { 1036 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 1037 struct amdgpu_device *adev = ring->adev; 1038 struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub]; 1039 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 1040 unsigned int eng = ring->vm_inv_eng; 1041 1042 /* 1043 * It may lose gpuvm invalidate acknowldege state across power-gating 1044 * off cycle, add semaphore acquire before invalidation and semaphore 1045 * release after invalidation to avoid entering power gated state 1046 * to WA the Issue 1047 */ 1048 1049 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1050 if (use_semaphore) 1051 /* a read return value of 1 means semaphore acuqire */ 1052 amdgpu_ring_emit_reg_wait(ring, 1053 hub->vm_inv_eng0_sem + 1054 hub->eng_distance * eng, 0x1, 0x1); 1055 1056 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 1057 (hub->ctx_addr_distance * vmid), 1058 lower_32_bits(pd_addr)); 1059 1060 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 1061 (hub->ctx_addr_distance * vmid), 1062 upper_32_bits(pd_addr)); 1063 1064 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 1065 hub->eng_distance * eng, 1066 hub->vm_inv_eng0_ack + 1067 hub->eng_distance * eng, 1068 req, 1 << vmid); 1069 1070 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1071 if (use_semaphore) 1072 /* 1073 * add semaphore release after invalidation, 1074 * write with 0 means semaphore release 1075 */ 1076 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 1077 hub->eng_distance * eng, 0); 1078 1079 return pd_addr; 1080 } 1081 1082 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 1083 unsigned int pasid) 1084 { 1085 struct amdgpu_device *adev = ring->adev; 1086 uint32_t reg; 1087 1088 /* Do nothing because there's no lut register for mmhub1. */ 1089 if (ring->vm_hub == AMDGPU_MMHUB1(0)) 1090 return; 1091 1092 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 1093 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 1094 else 1095 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 1096 1097 amdgpu_ring_emit_wreg(ring, reg, pasid); 1098 } 1099 1100 /* 1101 * PTE format on VEGA 10: 1102 * 63:59 reserved 1103 * 58:57 mtype 1104 * 56 F 1105 * 55 L 1106 * 54 P 1107 * 53 SW 1108 * 52 T 1109 * 50:48 reserved 1110 * 47:12 4k physical page base address 1111 * 11:7 fragment 1112 * 6 write 1113 * 5 read 1114 * 4 exe 1115 * 3 Z 1116 * 2 snooped 1117 * 1 system 1118 * 0 valid 1119 * 1120 * PDE format on VEGA 10: 1121 * 63:59 block fragment size 1122 * 58:55 reserved 1123 * 54 P 1124 * 53:48 reserved 1125 * 47:6 physical base address of PD or PTE 1126 * 5:3 reserved 1127 * 2 C 1128 * 1 system 1129 * 0 valid 1130 */ 1131 1132 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 1133 1134 { 1135 switch (flags) { 1136 case AMDGPU_VM_MTYPE_DEFAULT: 1137 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1138 case AMDGPU_VM_MTYPE_NC: 1139 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1140 case AMDGPU_VM_MTYPE_WC: 1141 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC); 1142 case AMDGPU_VM_MTYPE_RW: 1143 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW); 1144 case AMDGPU_VM_MTYPE_CC: 1145 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); 1146 case AMDGPU_VM_MTYPE_UC: 1147 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC); 1148 default: 1149 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1150 } 1151 } 1152 1153 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 1154 uint64_t *addr, uint64_t *flags) 1155 { 1156 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 1157 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 1158 BUG_ON(*addr & 0xFFFF00000000003FULL); 1159 1160 if (!adev->gmc.translate_further) 1161 return; 1162 1163 if (level == AMDGPU_VM_PDB1) { 1164 /* Set the block fragment size */ 1165 if (!(*flags & AMDGPU_PDE_PTE)) 1166 *flags |= AMDGPU_PDE_BFS(0x9); 1167 1168 } else if (level == AMDGPU_VM_PDB0) { 1169 if (*flags & AMDGPU_PDE_PTE) { 1170 *flags &= ~AMDGPU_PDE_PTE; 1171 if (!(*flags & AMDGPU_PTE_VALID)) 1172 *addr |= 1 << PAGE_SHIFT; 1173 } else { 1174 *flags |= AMDGPU_PTE_TF; 1175 } 1176 } 1177 } 1178 1179 static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, 1180 struct amdgpu_bo *bo, 1181 struct amdgpu_bo_va_mapping *mapping, 1182 uint64_t *flags) 1183 { 1184 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); 1185 bool is_vram = bo->tbo.resource->mem_type == TTM_PL_VRAM; 1186 bool coherent = bo->flags & AMDGPU_GEM_CREATE_COHERENT; 1187 bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED; 1188 struct amdgpu_vm *vm = mapping->bo_va->base.vm; 1189 unsigned int mtype_local, mtype; 1190 bool snoop = false; 1191 bool is_local; 1192 1193 switch (adev->ip_versions[GC_HWIP][0]) { 1194 case IP_VERSION(9, 4, 1): 1195 case IP_VERSION(9, 4, 2): 1196 if (is_vram) { 1197 if (bo_adev == adev) { 1198 if (uncached) 1199 mtype = MTYPE_UC; 1200 else if (coherent) 1201 mtype = MTYPE_CC; 1202 else 1203 mtype = MTYPE_RW; 1204 /* FIXME: is this still needed? Or does 1205 * amdgpu_ttm_tt_pde_flags already handle this? 1206 */ 1207 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || 1208 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) && 1209 adev->gmc.xgmi.connected_to_cpu) 1210 snoop = true; 1211 } else { 1212 if (uncached || coherent) 1213 mtype = MTYPE_UC; 1214 else 1215 mtype = MTYPE_NC; 1216 if (mapping->bo_va->is_xgmi) 1217 snoop = true; 1218 } 1219 } else { 1220 if (uncached || coherent) 1221 mtype = MTYPE_UC; 1222 else 1223 mtype = MTYPE_NC; 1224 /* FIXME: is this still needed? Or does 1225 * amdgpu_ttm_tt_pde_flags already handle this? 1226 */ 1227 snoop = true; 1228 } 1229 break; 1230 case IP_VERSION(9, 4, 3): 1231 /* Only local VRAM BOs or system memory on non-NUMA APUs 1232 * can be assumed to be local in their entirety. Choose 1233 * MTYPE_NC as safe fallback for all system memory BOs on 1234 * NUMA systems. Their MTYPE can be overridden per-page in 1235 * gmc_v9_0_override_vm_pte_flags. 1236 */ 1237 mtype_local = MTYPE_RW; 1238 if (amdgpu_mtype_local == 1) { 1239 DRM_INFO_ONCE("Using MTYPE_NC for local memory\n"); 1240 mtype_local = MTYPE_NC; 1241 } else if (amdgpu_mtype_local == 2) { 1242 DRM_INFO_ONCE("Using MTYPE_CC for local memory\n"); 1243 mtype_local = MTYPE_CC; 1244 } else { 1245 DRM_INFO_ONCE("Using MTYPE_RW for local memory\n"); 1246 } 1247 is_local = (!is_vram && (adev->flags & AMD_IS_APU) && 1248 num_possible_nodes() <= 1) || 1249 (is_vram && adev == bo_adev && 1250 KFD_XCP_MEM_ID(adev, bo->xcp_id) == vm->mem_id); 1251 snoop = true; 1252 if (uncached) { 1253 mtype = MTYPE_UC; 1254 } else if (adev->flags & AMD_IS_APU) { 1255 mtype = is_local ? mtype_local : MTYPE_NC; 1256 } else { 1257 /* dGPU */ 1258 if (is_local) 1259 mtype = mtype_local; 1260 else if (is_vram) 1261 mtype = MTYPE_NC; 1262 else 1263 mtype = MTYPE_UC; 1264 } 1265 1266 break; 1267 default: 1268 if (uncached || coherent) 1269 mtype = MTYPE_UC; 1270 else 1271 mtype = MTYPE_NC; 1272 1273 /* FIXME: is this still needed? Or does 1274 * amdgpu_ttm_tt_pde_flags already handle this? 1275 */ 1276 if (!is_vram) 1277 snoop = true; 1278 } 1279 1280 if (mtype != MTYPE_NC) 1281 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) | 1282 AMDGPU_PTE_MTYPE_VG10(mtype); 1283 *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0; 1284 } 1285 1286 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, 1287 struct amdgpu_bo_va_mapping *mapping, 1288 uint64_t *flags) 1289 { 1290 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 1291 1292 *flags &= ~AMDGPU_PTE_EXECUTABLE; 1293 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 1294 1295 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 1296 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK; 1297 1298 if (mapping->flags & AMDGPU_PTE_PRT) { 1299 *flags |= AMDGPU_PTE_PRT; 1300 *flags &= ~AMDGPU_PTE_VALID; 1301 } 1302 1303 if (bo && bo->tbo.resource) 1304 gmc_v9_0_get_coherence_flags(adev, mapping->bo_va->base.bo, 1305 mapping, flags); 1306 } 1307 1308 static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev, 1309 struct amdgpu_vm *vm, 1310 uint64_t addr, uint64_t *flags) 1311 { 1312 int local_node, nid; 1313 1314 /* Only GFX 9.4.3 APUs associate GPUs with NUMA nodes. Local system 1315 * memory can use more efficient MTYPEs. 1316 */ 1317 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 3)) 1318 return; 1319 1320 /* Only direct-mapped memory allows us to determine the NUMA node from 1321 * the DMA address. 1322 */ 1323 if (!adev->ram_is_direct_mapped) { 1324 dev_dbg(adev->dev, "RAM is not direct mapped\n"); 1325 return; 1326 } 1327 1328 /* Only override mappings with MTYPE_NC, which is the safe default for 1329 * cacheable memory. 1330 */ 1331 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1332 AMDGPU_PTE_MTYPE_VG10(MTYPE_NC)) { 1333 dev_dbg(adev->dev, "MTYPE is not NC\n"); 1334 return; 1335 } 1336 1337 /* FIXME: Only supported on native mode for now. For carve-out, the 1338 * NUMA affinity of the GPU/VM needs to come from the PCI info because 1339 * memory partitions are not associated with different NUMA nodes. 1340 */ 1341 if (adev->gmc.is_app_apu && vm->mem_id >= 0) { 1342 local_node = adev->gmc.mem_partitions[vm->mem_id].numa.node; 1343 } else { 1344 dev_dbg(adev->dev, "Only native mode APU is supported.\n"); 1345 return; 1346 } 1347 1348 /* Only handle real RAM. Mappings of PCIe resources don't have struct 1349 * page or NUMA nodes. 1350 */ 1351 #ifdef notyet 1352 if (!page_is_ram(addr >> PAGE_SHIFT)) { 1353 dev_dbg(adev->dev, "Page is not RAM.\n"); 1354 return; 1355 } 1356 #endif 1357 nid = pfn_to_nid(addr >> PAGE_SHIFT); 1358 dev_dbg(adev->dev, "vm->mem_id=%d, local_node=%d, nid=%d\n", 1359 vm->mem_id, local_node, nid); 1360 if (nid == local_node) { 1361 uint64_t old_flags = *flags; 1362 unsigned int mtype_local = MTYPE_RW; 1363 1364 if (amdgpu_mtype_local == 1) 1365 mtype_local = MTYPE_NC; 1366 else if (amdgpu_mtype_local == 2) 1367 mtype_local = MTYPE_CC; 1368 1369 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) | 1370 AMDGPU_PTE_MTYPE_VG10(mtype_local); 1371 dev_dbg(adev->dev, "flags updated from %llx to %llx\n", 1372 old_flags, *flags); 1373 } 1374 } 1375 1376 static unsigned int gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 1377 { 1378 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1379 unsigned int size; 1380 1381 /* TODO move to DC so GMC doesn't need to hard-code DCN registers */ 1382 1383 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1384 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1385 } else { 1386 u32 viewport; 1387 1388 switch (adev->ip_versions[DCE_HWIP][0]) { 1389 case IP_VERSION(1, 0, 0): 1390 case IP_VERSION(1, 0, 1): 1391 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1392 size = (REG_GET_FIELD(viewport, 1393 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1394 REG_GET_FIELD(viewport, 1395 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1396 4); 1397 break; 1398 case IP_VERSION(2, 1, 0): 1399 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2); 1400 size = (REG_GET_FIELD(viewport, 1401 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1402 REG_GET_FIELD(viewport, 1403 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1404 4); 1405 break; 1406 default: 1407 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1408 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1409 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1410 4); 1411 break; 1412 } 1413 } 1414 1415 return size; 1416 } 1417 1418 static enum amdgpu_memory_partition 1419 gmc_v9_0_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes) 1420 { 1421 enum amdgpu_memory_partition mode = UNKNOWN_MEMORY_PARTITION_MODE; 1422 1423 if (adev->nbio.funcs->get_memory_partition_mode) 1424 mode = adev->nbio.funcs->get_memory_partition_mode(adev, 1425 supp_modes); 1426 1427 return mode; 1428 } 1429 1430 static enum amdgpu_memory_partition 1431 gmc_v9_0_query_memory_partition(struct amdgpu_device *adev) 1432 { 1433 if (amdgpu_sriov_vf(adev)) 1434 return AMDGPU_NPS1_PARTITION_MODE; 1435 1436 return gmc_v9_0_get_memory_partition(adev, NULL); 1437 } 1438 1439 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 1440 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 1441 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, 1442 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 1443 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 1444 .map_mtype = gmc_v9_0_map_mtype, 1445 .get_vm_pde = gmc_v9_0_get_vm_pde, 1446 .get_vm_pte = gmc_v9_0_get_vm_pte, 1447 .override_vm_pte_flags = gmc_v9_0_override_vm_pte_flags, 1448 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size, 1449 .query_mem_partition_mode = &gmc_v9_0_query_memory_partition, 1450 }; 1451 1452 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 1453 { 1454 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 1455 } 1456 1457 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 1458 { 1459 switch (adev->ip_versions[UMC_HWIP][0]) { 1460 case IP_VERSION(6, 0, 0): 1461 adev->umc.funcs = &umc_v6_0_funcs; 1462 break; 1463 case IP_VERSION(6, 1, 1): 1464 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1465 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1466 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1467 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; 1468 adev->umc.retire_unit = 1; 1469 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1470 adev->umc.ras = &umc_v6_1_ras; 1471 break; 1472 case IP_VERSION(6, 1, 2): 1473 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1474 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1475 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1476 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT; 1477 adev->umc.retire_unit = 1; 1478 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1479 adev->umc.ras = &umc_v6_1_ras; 1480 break; 1481 case IP_VERSION(6, 7, 0): 1482 adev->umc.max_ras_err_cnt_per_query = 1483 UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL; 1484 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM; 1485 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM; 1486 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET; 1487 adev->umc.retire_unit = (UMC_V6_7_NA_MAP_PA_NUM * 2); 1488 if (!adev->gmc.xgmi.connected_to_cpu) 1489 adev->umc.ras = &umc_v6_7_ras; 1490 if (1 & adev->smuio.funcs->get_die_id(adev)) 1491 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0]; 1492 else 1493 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0]; 1494 break; 1495 default: 1496 break; 1497 } 1498 } 1499 1500 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 1501 { 1502 switch (adev->ip_versions[MMHUB_HWIP][0]) { 1503 case IP_VERSION(9, 4, 1): 1504 adev->mmhub.funcs = &mmhub_v9_4_funcs; 1505 break; 1506 case IP_VERSION(9, 4, 2): 1507 adev->mmhub.funcs = &mmhub_v1_7_funcs; 1508 break; 1509 case IP_VERSION(1, 8, 0): 1510 adev->mmhub.funcs = &mmhub_v1_8_funcs; 1511 break; 1512 default: 1513 adev->mmhub.funcs = &mmhub_v1_0_funcs; 1514 break; 1515 } 1516 } 1517 1518 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev) 1519 { 1520 switch (adev->ip_versions[MMHUB_HWIP][0]) { 1521 case IP_VERSION(9, 4, 0): 1522 adev->mmhub.ras = &mmhub_v1_0_ras; 1523 break; 1524 case IP_VERSION(9, 4, 1): 1525 adev->mmhub.ras = &mmhub_v9_4_ras; 1526 break; 1527 case IP_VERSION(9, 4, 2): 1528 adev->mmhub.ras = &mmhub_v1_7_ras; 1529 break; 1530 case IP_VERSION(1, 8, 0): 1531 adev->mmhub.ras = &mmhub_v1_8_ras; 1532 break; 1533 default: 1534 /* mmhub ras is not available */ 1535 break; 1536 } 1537 } 1538 1539 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev) 1540 { 1541 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) 1542 adev->gfxhub.funcs = &gfxhub_v1_2_funcs; 1543 else 1544 adev->gfxhub.funcs = &gfxhub_v1_0_funcs; 1545 } 1546 1547 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev) 1548 { 1549 adev->hdp.ras = &hdp_v4_0_ras; 1550 } 1551 1552 static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev) 1553 { 1554 struct amdgpu_mca *mca = &adev->mca; 1555 1556 /* is UMC the right IP to check for MCA? Maybe DF? */ 1557 switch (adev->ip_versions[UMC_HWIP][0]) { 1558 case IP_VERSION(6, 7, 0): 1559 if (!adev->gmc.xgmi.connected_to_cpu) { 1560 mca->mp0.ras = &mca_v3_0_mp0_ras; 1561 mca->mp1.ras = &mca_v3_0_mp1_ras; 1562 mca->mpio.ras = &mca_v3_0_mpio_ras; 1563 } 1564 break; 1565 default: 1566 break; 1567 } 1568 } 1569 1570 static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev) 1571 { 1572 if (!adev->gmc.xgmi.connected_to_cpu) 1573 adev->gmc.xgmi.ras = &xgmi_ras; 1574 } 1575 1576 static int gmc_v9_0_early_init(void *handle) 1577 { 1578 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1579 1580 /* 1581 * 9.4.0, 9.4.1 and 9.4.3 don't have XGMI defined 1582 * in their IP discovery tables 1583 */ 1584 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0) || 1585 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || 1586 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) 1587 adev->gmc.xgmi.supported = true; 1588 1589 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(6, 1, 0)) { 1590 adev->gmc.xgmi.supported = true; 1591 adev->gmc.xgmi.connected_to_cpu = 1592 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); 1593 } 1594 1595 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) { 1596 enum amdgpu_pkg_type pkg_type = 1597 adev->smuio.funcs->get_pkg_type(adev); 1598 /* On GFXIP 9.4.3. APU, there is no physical VRAM domain present 1599 * and the APU, can be in used two possible modes: 1600 * - carveout mode 1601 * - native APU mode 1602 * "is_app_apu" can be used to identify the APU in the native 1603 * mode. 1604 */ 1605 #ifdef notyet 1606 adev->gmc.is_app_apu = (pkg_type == AMDGPU_PKG_TYPE_APU && 1607 !pci_resource_len(adev->pdev, 0)); 1608 #else 1609 adev->gmc.is_app_apu = (pkg_type == AMDGPU_PKG_TYPE_APU && 1610 !adev->fb_aper_size); 1611 #endif 1612 } 1613 1614 gmc_v9_0_set_gmc_funcs(adev); 1615 gmc_v9_0_set_irq_funcs(adev); 1616 gmc_v9_0_set_umc_funcs(adev); 1617 gmc_v9_0_set_mmhub_funcs(adev); 1618 gmc_v9_0_set_mmhub_ras_funcs(adev); 1619 gmc_v9_0_set_gfxhub_funcs(adev); 1620 gmc_v9_0_set_hdp_ras_funcs(adev); 1621 gmc_v9_0_set_mca_ras_funcs(adev); 1622 gmc_v9_0_set_xgmi_ras_funcs(adev); 1623 1624 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1625 adev->gmc.shared_aperture_end = 1626 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1627 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 1628 adev->gmc.private_aperture_end = 1629 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1630 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 1631 1632 return 0; 1633 } 1634 1635 static int gmc_v9_0_late_init(void *handle) 1636 { 1637 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1638 int r; 1639 1640 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 1641 if (r) 1642 return r; 1643 1644 /* 1645 * Workaround performance drop issue with VBIOS enables partial 1646 * writes, while disables HBM ECC for vega10. 1647 */ 1648 if (!amdgpu_sriov_vf(adev) && 1649 (adev->ip_versions[UMC_HWIP][0] == IP_VERSION(6, 0, 0))) { 1650 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) { 1651 if (adev->df.funcs && 1652 adev->df.funcs->enable_ecc_force_par_wr_rmw) 1653 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); 1654 } 1655 } 1656 1657 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1658 if (adev->mmhub.ras && adev->mmhub.ras->ras_block.hw_ops && 1659 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count) 1660 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(adev); 1661 1662 if (adev->hdp.ras && adev->hdp.ras->ras_block.hw_ops && 1663 adev->hdp.ras->ras_block.hw_ops->reset_ras_error_count) 1664 adev->hdp.ras->ras_block.hw_ops->reset_ras_error_count(adev); 1665 } 1666 1667 r = amdgpu_gmc_ras_late_init(adev); 1668 if (r) 1669 return r; 1670 1671 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1672 } 1673 1674 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 1675 struct amdgpu_gmc *mc) 1676 { 1677 u64 base = adev->mmhub.funcs->get_fb_location(adev); 1678 1679 /* add the xgmi offset of the physical node */ 1680 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1681 if (adev->gmc.xgmi.connected_to_cpu) { 1682 amdgpu_gmc_sysvm_location(adev, mc); 1683 } else { 1684 amdgpu_gmc_vram_location(adev, mc, base); 1685 amdgpu_gmc_gart_location(adev, mc); 1686 amdgpu_gmc_agp_location(adev, mc); 1687 } 1688 /* base offset of vram pages */ 1689 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 1690 1691 /* XXX: add the xgmi offset of the physical node? */ 1692 adev->vm_manager.vram_base_offset += 1693 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1694 } 1695 1696 /** 1697 * gmc_v9_0_mc_init - initialize the memory controller driver params 1698 * 1699 * @adev: amdgpu_device pointer 1700 * 1701 * Look up the amount of vram, vram width, and decide how to place 1702 * vram and gart within the GPU's physical address space. 1703 * Returns 0 for success. 1704 */ 1705 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 1706 { 1707 int r; 1708 1709 /* size in MB on si */ 1710 if (!adev->gmc.is_app_apu) { 1711 adev->gmc.mc_vram_size = 1712 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 1713 } else { 1714 DRM_DEBUG("Set mc_vram_size = 0 for APP APU\n"); 1715 adev->gmc.mc_vram_size = 0; 1716 } 1717 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 1718 1719 if (!(adev->flags & AMD_IS_APU) && 1720 !adev->gmc.xgmi.connected_to_cpu) { 1721 r = amdgpu_device_resize_fb_bar(adev); 1722 if (r) 1723 return r; 1724 } 1725 adev->gmc.aper_base = adev->fb_aper_offset; 1726 adev->gmc.aper_size = adev->fb_aper_size; 1727 1728 #ifdef CONFIG_X86_64 1729 /* 1730 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi 1731 * interface can use VRAM through here as it appears system reserved 1732 * memory in host address space. 1733 * 1734 * For APUs, VRAM is just the stolen system memory and can be accessed 1735 * directly. 1736 * 1737 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR. 1738 */ 1739 1740 /* check whether both host-gpu and gpu-gpu xgmi links exist */ 1741 if ((!amdgpu_sriov_vf(adev) && 1742 (adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) || 1743 (adev->gmc.xgmi.supported && 1744 adev->gmc.xgmi.connected_to_cpu)) { 1745 adev->gmc.aper_base = 1746 adev->gfxhub.funcs->get_mc_fb_offset(adev) + 1747 adev->gmc.xgmi.physical_node_id * 1748 adev->gmc.xgmi.node_segment_size; 1749 adev->gmc.aper_size = adev->gmc.real_vram_size; 1750 } 1751 1752 #endif 1753 adev->gmc.visible_vram_size = adev->gmc.aper_size; 1754 1755 /* set the gart size */ 1756 if (amdgpu_gart_size == -1) { 1757 switch (adev->ip_versions[GC_HWIP][0]) { 1758 case IP_VERSION(9, 0, 1): /* all engines support GPUVM */ 1759 case IP_VERSION(9, 2, 1): /* all engines support GPUVM */ 1760 case IP_VERSION(9, 4, 0): 1761 case IP_VERSION(9, 4, 1): 1762 case IP_VERSION(9, 4, 2): 1763 case IP_VERSION(9, 4, 3): 1764 default: 1765 adev->gmc.gart_size = 512ULL << 20; 1766 break; 1767 case IP_VERSION(9, 1, 0): /* DCE SG support */ 1768 case IP_VERSION(9, 2, 2): /* DCE SG support */ 1769 case IP_VERSION(9, 3, 0): 1770 adev->gmc.gart_size = 1024ULL << 20; 1771 break; 1772 } 1773 } else { 1774 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 1775 } 1776 1777 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; 1778 1779 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 1780 1781 return 0; 1782 } 1783 1784 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 1785 { 1786 int r; 1787 1788 if (adev->gart.bo) { 1789 WARN(1, "VEGA10 PCIE GART already initialized\n"); 1790 return 0; 1791 } 1792 1793 if (adev->gmc.xgmi.connected_to_cpu) { 1794 adev->gmc.vmid0_page_table_depth = 1; 1795 adev->gmc.vmid0_page_table_block_size = 12; 1796 } else { 1797 adev->gmc.vmid0_page_table_depth = 0; 1798 adev->gmc.vmid0_page_table_block_size = 0; 1799 } 1800 1801 /* Initialize common gart structure */ 1802 r = amdgpu_gart_init(adev); 1803 if (r) 1804 return r; 1805 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 1806 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) | 1807 AMDGPU_PTE_EXECUTABLE; 1808 1809 if (!adev->gmc.real_vram_size) { 1810 dev_info(adev->dev, "Put GART in system memory for APU\n"); 1811 r = amdgpu_gart_table_ram_alloc(adev); 1812 if (r) 1813 dev_err(adev->dev, "Failed to allocate GART in system memory\n"); 1814 } else { 1815 r = amdgpu_gart_table_vram_alloc(adev); 1816 if (r) 1817 return r; 1818 1819 if (adev->gmc.xgmi.connected_to_cpu) 1820 r = amdgpu_gmc_pdb0_alloc(adev); 1821 } 1822 1823 return r; 1824 } 1825 1826 /** 1827 * gmc_v9_0_save_registers - saves regs 1828 * 1829 * @adev: amdgpu_device pointer 1830 * 1831 * This saves potential register values that should be 1832 * restored upon resume 1833 */ 1834 static void gmc_v9_0_save_registers(struct amdgpu_device *adev) 1835 { 1836 if ((adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 0)) || 1837 (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 1))) 1838 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); 1839 } 1840 1841 static bool gmc_v9_0_validate_partition_info(struct amdgpu_device *adev) 1842 { 1843 enum amdgpu_memory_partition mode; 1844 u32 supp_modes; 1845 bool valid; 1846 1847 mode = gmc_v9_0_get_memory_partition(adev, &supp_modes); 1848 1849 /* Mode detected by hardware not present in supported modes */ 1850 if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) && 1851 !(BIT(mode - 1) & supp_modes)) 1852 return false; 1853 1854 switch (mode) { 1855 case UNKNOWN_MEMORY_PARTITION_MODE: 1856 case AMDGPU_NPS1_PARTITION_MODE: 1857 valid = (adev->gmc.num_mem_partitions == 1); 1858 break; 1859 case AMDGPU_NPS2_PARTITION_MODE: 1860 valid = (adev->gmc.num_mem_partitions == 2); 1861 break; 1862 case AMDGPU_NPS4_PARTITION_MODE: 1863 valid = (adev->gmc.num_mem_partitions == 3 || 1864 adev->gmc.num_mem_partitions == 4); 1865 break; 1866 default: 1867 valid = false; 1868 } 1869 1870 return valid; 1871 } 1872 1873 static bool gmc_v9_0_is_node_present(int *node_ids, int num_ids, int nid) 1874 { 1875 int i; 1876 1877 /* Check if node with id 'nid' is present in 'node_ids' array */ 1878 for (i = 0; i < num_ids; ++i) 1879 if (node_ids[i] == nid) 1880 return true; 1881 1882 return false; 1883 } 1884 1885 static void 1886 gmc_v9_0_init_acpi_mem_ranges(struct amdgpu_device *adev, 1887 struct amdgpu_mem_partition_info *mem_ranges) 1888 { 1889 int num_ranges = 0, ret, mem_groups; 1890 struct amdgpu_numa_info numa_info; 1891 int node_ids[MAX_MEM_RANGES]; 1892 int num_xcc, xcc_id; 1893 uint32_t xcc_mask; 1894 1895 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1896 xcc_mask = (1U << num_xcc) - 1; 1897 mem_groups = hweight32(adev->aid_mask); 1898 1899 for_each_inst(xcc_id, xcc_mask) { 1900 ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); 1901 if (ret) 1902 continue; 1903 1904 if (numa_info.nid == NUMA_NO_NODE) { 1905 mem_ranges[0].size = numa_info.size; 1906 mem_ranges[0].numa.node = numa_info.nid; 1907 num_ranges = 1; 1908 break; 1909 } 1910 1911 if (gmc_v9_0_is_node_present(node_ids, num_ranges, 1912 numa_info.nid)) 1913 continue; 1914 1915 node_ids[num_ranges] = numa_info.nid; 1916 mem_ranges[num_ranges].numa.node = numa_info.nid; 1917 mem_ranges[num_ranges].size = numa_info.size; 1918 ++num_ranges; 1919 } 1920 1921 adev->gmc.num_mem_partitions = num_ranges; 1922 1923 /* If there is only partition, don't use entire size */ 1924 if (adev->gmc.num_mem_partitions == 1) { 1925 mem_ranges[0].size = mem_ranges[0].size * (mem_groups - 1); 1926 do_div(mem_ranges[0].size, mem_groups); 1927 } 1928 } 1929 1930 static void 1931 gmc_v9_0_init_sw_mem_ranges(struct amdgpu_device *adev, 1932 struct amdgpu_mem_partition_info *mem_ranges) 1933 { 1934 enum amdgpu_memory_partition mode; 1935 u32 start_addr = 0, size; 1936 int i; 1937 1938 mode = gmc_v9_0_query_memory_partition(adev); 1939 1940 switch (mode) { 1941 case UNKNOWN_MEMORY_PARTITION_MODE: 1942 case AMDGPU_NPS1_PARTITION_MODE: 1943 adev->gmc.num_mem_partitions = 1; 1944 break; 1945 case AMDGPU_NPS2_PARTITION_MODE: 1946 adev->gmc.num_mem_partitions = 2; 1947 break; 1948 case AMDGPU_NPS4_PARTITION_MODE: 1949 if (adev->flags & AMD_IS_APU) 1950 adev->gmc.num_mem_partitions = 3; 1951 else 1952 adev->gmc.num_mem_partitions = 4; 1953 break; 1954 default: 1955 adev->gmc.num_mem_partitions = 1; 1956 break; 1957 } 1958 1959 size = (adev->gmc.real_vram_size + SZ_16M) >> AMDGPU_GPU_PAGE_SHIFT; 1960 size /= adev->gmc.num_mem_partitions; 1961 1962 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) { 1963 mem_ranges[i].range.fpfn = start_addr; 1964 mem_ranges[i].size = ((u64)size << AMDGPU_GPU_PAGE_SHIFT); 1965 mem_ranges[i].range.lpfn = start_addr + size - 1; 1966 start_addr += size; 1967 } 1968 1969 /* Adjust the last one */ 1970 mem_ranges[adev->gmc.num_mem_partitions - 1].range.lpfn = 1971 (adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT) - 1; 1972 mem_ranges[adev->gmc.num_mem_partitions - 1].size = 1973 adev->gmc.real_vram_size - 1974 ((u64)mem_ranges[adev->gmc.num_mem_partitions - 1].range.fpfn 1975 << AMDGPU_GPU_PAGE_SHIFT); 1976 } 1977 1978 static int gmc_v9_0_init_mem_ranges(struct amdgpu_device *adev) 1979 { 1980 bool valid; 1981 1982 adev->gmc.mem_partitions = kzalloc( 1983 MAX_MEM_RANGES * sizeof(struct amdgpu_mem_partition_info), 1984 GFP_KERNEL); 1985 1986 if (!adev->gmc.mem_partitions) 1987 return -ENOMEM; 1988 1989 /* TODO : Get the range from PSP/Discovery for dGPU */ 1990 if (adev->gmc.is_app_apu) 1991 gmc_v9_0_init_acpi_mem_ranges(adev, adev->gmc.mem_partitions); 1992 else 1993 gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions); 1994 1995 if (amdgpu_sriov_vf(adev)) 1996 valid = true; 1997 else 1998 valid = gmc_v9_0_validate_partition_info(adev); 1999 if (!valid) { 2000 /* TODO: handle invalid case */ 2001 dev_WARN(adev->dev, 2002 "Mem ranges not matching with hardware config"); 2003 } 2004 2005 return 0; 2006 } 2007 2008 static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev) 2009 { 2010 static const u32 regBIF_BIOS_SCRATCH_4 = 0x50; 2011 u32 vram_info; 2012 2013 if (!amdgpu_sriov_vf(adev)) { 2014 vram_info = RREG32(regBIF_BIOS_SCRATCH_4); 2015 adev->gmc.vram_vendor = vram_info & 0xF; 2016 } 2017 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 2018 adev->gmc.vram_width = 128 * 64; 2019 } 2020 2021 static int gmc_v9_0_sw_init(void *handle) 2022 { 2023 int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits; 2024 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2025 unsigned long inst_mask = adev->aid_mask; 2026 2027 adev->gfxhub.funcs->init(adev); 2028 2029 adev->mmhub.funcs->init(adev); 2030 2031 mtx_init(&adev->gmc.invalidate_lock, IPL_NONE); 2032 2033 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) { 2034 gmc_v9_4_3_init_vram_info(adev); 2035 } else if (!adev->bios) { 2036 if (adev->flags & AMD_IS_APU) { 2037 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 2038 adev->gmc.vram_width = 64 * 64; 2039 } else { 2040 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 2041 adev->gmc.vram_width = 128 * 64; 2042 } 2043 } else { 2044 r = amdgpu_atomfirmware_get_vram_info(adev, 2045 &vram_width, &vram_type, &vram_vendor); 2046 if (amdgpu_sriov_vf(adev)) 2047 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 2048 * and DF related registers is not readable, seems hardcord is the 2049 * only way to set the correct vram_width 2050 */ 2051 adev->gmc.vram_width = 2048; 2052 else if (amdgpu_emu_mode != 1) 2053 adev->gmc.vram_width = vram_width; 2054 2055 if (!adev->gmc.vram_width) { 2056 int chansize, numchan; 2057 2058 /* hbm memory channel size */ 2059 if (adev->flags & AMD_IS_APU) 2060 chansize = 64; 2061 else 2062 chansize = 128; 2063 if (adev->df.funcs && 2064 adev->df.funcs->get_hbm_channel_number) { 2065 numchan = adev->df.funcs->get_hbm_channel_number(adev); 2066 adev->gmc.vram_width = numchan * chansize; 2067 } 2068 } 2069 2070 adev->gmc.vram_type = vram_type; 2071 adev->gmc.vram_vendor = vram_vendor; 2072 } 2073 switch (adev->ip_versions[GC_HWIP][0]) { 2074 case IP_VERSION(9, 1, 0): 2075 case IP_VERSION(9, 2, 2): 2076 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2077 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2078 2079 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 2080 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2081 } else { 2082 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 2083 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 2084 adev->gmc.translate_further = 2085 adev->vm_manager.num_level > 1; 2086 } 2087 break; 2088 case IP_VERSION(9, 0, 1): 2089 case IP_VERSION(9, 2, 1): 2090 case IP_VERSION(9, 4, 0): 2091 case IP_VERSION(9, 3, 0): 2092 case IP_VERSION(9, 4, 2): 2093 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2094 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2095 2096 /* 2097 * To fulfill 4-level page support, 2098 * vm size is 256TB (48bit), maximum size of Vega10, 2099 * block size 512 (9bit) 2100 */ 2101 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */ 2102 if (amdgpu_sriov_vf(adev)) 2103 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47); 2104 else 2105 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2106 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 2107 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2108 break; 2109 case IP_VERSION(9, 4, 1): 2110 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2111 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2112 set_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask); 2113 2114 /* Keep the vm size same with Vega20 */ 2115 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2116 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2117 break; 2118 case IP_VERSION(9, 4, 3): 2119 bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0), 2120 NUM_XCC(adev->gfx.xcc_mask)); 2121 2122 inst_mask <<= AMDGPU_MMHUB0(0); 2123 bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32); 2124 2125 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2126 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2127 break; 2128 default: 2129 break; 2130 } 2131 2132 /* This interrupt is VMC page fault.*/ 2133 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 2134 &adev->gmc.vm_fault); 2135 if (r) 2136 return r; 2137 2138 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) { 2139 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 2140 &adev->gmc.vm_fault); 2141 if (r) 2142 return r; 2143 } 2144 2145 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 2146 &adev->gmc.vm_fault); 2147 2148 if (r) 2149 return r; 2150 2151 if (!amdgpu_sriov_vf(adev) && 2152 !adev->gmc.xgmi.connected_to_cpu) { 2153 /* interrupt sent to DF. */ 2154 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 2155 &adev->gmc.ecc_irq); 2156 if (r) 2157 return r; 2158 } 2159 2160 /* Set the internal MC address mask 2161 * This is the max address of the GPU's 2162 * internal address space. 2163 */ 2164 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 2165 2166 dma_addr_bits = adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) ? 48:44; 2167 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits)); 2168 if (r) { 2169 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 2170 return r; 2171 } 2172 adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits); 2173 2174 r = gmc_v9_0_mc_init(adev); 2175 if (r) 2176 return r; 2177 2178 amdgpu_gmc_get_vbios_allocations(adev); 2179 2180 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) { 2181 r = gmc_v9_0_init_mem_ranges(adev); 2182 if (r) 2183 return r; 2184 } 2185 2186 /* Memory manager */ 2187 r = amdgpu_bo_init(adev); 2188 if (r) 2189 return r; 2190 2191 r = gmc_v9_0_gart_init(adev); 2192 if (r) 2193 return r; 2194 2195 /* 2196 * number of VMs 2197 * VMID 0 is reserved for System 2198 * amdgpu graphics/compute will use VMIDs 1..n-1 2199 * amdkfd will use VMIDs n..15 2200 * 2201 * The first KFD VMID is 8 for GPUs with graphics, 3 for 2202 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs 2203 * for video processing. 2204 */ 2205 adev->vm_manager.first_kfd_vmid = 2206 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || 2207 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || 2208 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) ? 3 : 8; 2209 2210 amdgpu_vm_manager_init(adev); 2211 2212 gmc_v9_0_save_registers(adev); 2213 2214 r = amdgpu_gmc_ras_sw_init(adev); 2215 if (r) 2216 return r; 2217 2218 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) 2219 amdgpu_gmc_sysfs_init(adev); 2220 2221 return 0; 2222 } 2223 2224 static int gmc_v9_0_sw_fini(void *handle) 2225 { 2226 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2227 2228 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) 2229 amdgpu_gmc_sysfs_fini(adev); 2230 2231 amdgpu_gmc_ras_fini(adev); 2232 amdgpu_gem_force_release(adev); 2233 amdgpu_vm_manager_fini(adev); 2234 if (!adev->gmc.real_vram_size) { 2235 dev_info(adev->dev, "Put GART in system memory for APU free\n"); 2236 amdgpu_gart_table_ram_free(adev); 2237 } else { 2238 amdgpu_gart_table_vram_free(adev); 2239 } 2240 amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0); 2241 amdgpu_bo_fini(adev); 2242 2243 adev->gmc.num_mem_partitions = 0; 2244 kfree(adev->gmc.mem_partitions); 2245 2246 return 0; 2247 } 2248 2249 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 2250 { 2251 2252 switch (adev->ip_versions[MMHUB_HWIP][0]) { 2253 case IP_VERSION(9, 0, 0): 2254 if (amdgpu_sriov_vf(adev)) 2255 break; 2256 fallthrough; 2257 case IP_VERSION(9, 4, 0): 2258 soc15_program_register_sequence(adev, 2259 golden_settings_mmhub_1_0_0, 2260 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 2261 soc15_program_register_sequence(adev, 2262 golden_settings_athub_1_0_0, 2263 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2264 break; 2265 case IP_VERSION(9, 1, 0): 2266 case IP_VERSION(9, 2, 0): 2267 /* TODO for renoir */ 2268 soc15_program_register_sequence(adev, 2269 golden_settings_athub_1_0_0, 2270 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2271 break; 2272 default: 2273 break; 2274 } 2275 } 2276 2277 /** 2278 * gmc_v9_0_restore_registers - restores regs 2279 * 2280 * @adev: amdgpu_device pointer 2281 * 2282 * This restores register values, saved at suspend. 2283 */ 2284 void gmc_v9_0_restore_registers(struct amdgpu_device *adev) 2285 { 2286 if ((adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 0)) || 2287 (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 1))) { 2288 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); 2289 WARN_ON(adev->gmc.sdpif_register != 2290 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0)); 2291 } 2292 } 2293 2294 /** 2295 * gmc_v9_0_gart_enable - gart enable 2296 * 2297 * @adev: amdgpu_device pointer 2298 */ 2299 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 2300 { 2301 int r; 2302 2303 if (adev->gmc.xgmi.connected_to_cpu) 2304 amdgpu_gmc_init_pdb0(adev); 2305 2306 if (adev->gart.bo == NULL) { 2307 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 2308 return -EINVAL; 2309 } 2310 2311 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 2312 2313 if (!adev->in_s0ix) { 2314 r = adev->gfxhub.funcs->gart_enable(adev); 2315 if (r) 2316 return r; 2317 } 2318 2319 r = adev->mmhub.funcs->gart_enable(adev); 2320 if (r) 2321 return r; 2322 2323 DRM_INFO("PCIE GART of %uM enabled.\n", 2324 (unsigned int)(adev->gmc.gart_size >> 20)); 2325 if (adev->gmc.pdb0_bo) 2326 DRM_INFO("PDB0 located at 0x%016llX\n", 2327 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); 2328 DRM_INFO("PTB located at 0x%016llX\n", 2329 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 2330 2331 return 0; 2332 } 2333 2334 static int gmc_v9_0_hw_init(void *handle) 2335 { 2336 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2337 bool value; 2338 int i, r; 2339 2340 /* The sequence of these two function calls matters.*/ 2341 gmc_v9_0_init_golden_registers(adev); 2342 2343 if (adev->mode_info.num_crtc) { 2344 /* Lockout access through VGA aperture*/ 2345 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 2346 /* disable VGA render */ 2347 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 2348 } 2349 2350 if (adev->mmhub.funcs->update_power_gating) 2351 adev->mmhub.funcs->update_power_gating(adev, true); 2352 2353 adev->hdp.funcs->init_registers(adev); 2354 2355 /* After HDP is initialized, flush HDP.*/ 2356 adev->hdp.funcs->flush_hdp(adev, NULL); 2357 2358 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 2359 value = false; 2360 else 2361 value = true; 2362 2363 if (!amdgpu_sriov_vf(adev)) { 2364 if (!adev->in_s0ix) 2365 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 2366 adev->mmhub.funcs->set_fault_enable_default(adev, value); 2367 } 2368 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 2369 if (adev->in_s0ix && (i == AMDGPU_GFXHUB(0))) 2370 continue; 2371 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); 2372 } 2373 2374 if (adev->umc.funcs && adev->umc.funcs->init_registers) 2375 adev->umc.funcs->init_registers(adev); 2376 2377 r = gmc_v9_0_gart_enable(adev); 2378 if (r) 2379 return r; 2380 2381 if (amdgpu_emu_mode == 1) 2382 return amdgpu_gmc_vram_checking(adev); 2383 2384 return 0; 2385 } 2386 2387 /** 2388 * gmc_v9_0_gart_disable - gart disable 2389 * 2390 * @adev: amdgpu_device pointer 2391 * 2392 * This disables all VM page table. 2393 */ 2394 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 2395 { 2396 if (!adev->in_s0ix) 2397 adev->gfxhub.funcs->gart_disable(adev); 2398 adev->mmhub.funcs->gart_disable(adev); 2399 } 2400 2401 static int gmc_v9_0_hw_fini(void *handle) 2402 { 2403 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2404 2405 gmc_v9_0_gart_disable(adev); 2406 2407 if (amdgpu_sriov_vf(adev)) { 2408 /* full access mode, so don't touch any GMC register */ 2409 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 2410 return 0; 2411 } 2412 2413 /* 2414 * Pair the operations did in gmc_v9_0_hw_init and thus maintain 2415 * a correct cached state for GMC. Otherwise, the "gate" again 2416 * operation on S3 resuming will fail due to wrong cached state. 2417 */ 2418 if (adev->mmhub.funcs->update_power_gating) 2419 adev->mmhub.funcs->update_power_gating(adev, false); 2420 2421 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 2422 2423 if (adev->gmc.ecc_irq.funcs && 2424 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 2425 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 2426 2427 return 0; 2428 } 2429 2430 static int gmc_v9_0_suspend(void *handle) 2431 { 2432 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2433 2434 return gmc_v9_0_hw_fini(adev); 2435 } 2436 2437 static int gmc_v9_0_resume(void *handle) 2438 { 2439 int r; 2440 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2441 2442 r = gmc_v9_0_hw_init(adev); 2443 if (r) 2444 return r; 2445 2446 amdgpu_vmid_reset_all(adev); 2447 2448 return 0; 2449 } 2450 2451 static bool gmc_v9_0_is_idle(void *handle) 2452 { 2453 /* MC is always ready in GMC v9.*/ 2454 return true; 2455 } 2456 2457 static int gmc_v9_0_wait_for_idle(void *handle) 2458 { 2459 /* There is no need to wait for MC idle in GMC v9.*/ 2460 return 0; 2461 } 2462 2463 static int gmc_v9_0_soft_reset(void *handle) 2464 { 2465 /* XXX for emulation.*/ 2466 return 0; 2467 } 2468 2469 static int gmc_v9_0_set_clockgating_state(void *handle, 2470 enum amd_clockgating_state state) 2471 { 2472 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2473 2474 adev->mmhub.funcs->set_clockgating(adev, state); 2475 2476 athub_v1_0_set_clockgating(adev, state); 2477 2478 return 0; 2479 } 2480 2481 static void gmc_v9_0_get_clockgating_state(void *handle, u64 *flags) 2482 { 2483 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2484 2485 adev->mmhub.funcs->get_clockgating(adev, flags); 2486 2487 athub_v1_0_get_clockgating(adev, flags); 2488 } 2489 2490 static int gmc_v9_0_set_powergating_state(void *handle, 2491 enum amd_powergating_state state) 2492 { 2493 return 0; 2494 } 2495 2496 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 2497 .name = "gmc_v9_0", 2498 .early_init = gmc_v9_0_early_init, 2499 .late_init = gmc_v9_0_late_init, 2500 .sw_init = gmc_v9_0_sw_init, 2501 .sw_fini = gmc_v9_0_sw_fini, 2502 .hw_init = gmc_v9_0_hw_init, 2503 .hw_fini = gmc_v9_0_hw_fini, 2504 .suspend = gmc_v9_0_suspend, 2505 .resume = gmc_v9_0_resume, 2506 .is_idle = gmc_v9_0_is_idle, 2507 .wait_for_idle = gmc_v9_0_wait_for_idle, 2508 .soft_reset = gmc_v9_0_soft_reset, 2509 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 2510 .set_powergating_state = gmc_v9_0_set_powergating_state, 2511 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 2512 }; 2513 2514 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = { 2515 .type = AMD_IP_BLOCK_TYPE_GMC, 2516 .major = 9, 2517 .minor = 0, 2518 .rev = 0, 2519 .funcs = &gmc_v9_0_ip_funcs, 2520 }; 2521