1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/pci.h> 30 #include <linux/vmalloc.h> 31 32 #include <drm/amdgpu_drm.h> 33 #ifdef CONFIG_X86 34 #include <asm/set_memory.h> 35 #endif 36 #include "amdgpu.h" 37 #include <drm/drm_drv.h> 38 #include <drm/ttm/ttm_tt.h> 39 40 /* 41 * GART 42 * The GART (Graphics Aperture Remapping Table) is an aperture 43 * in the GPU's address space. System pages can be mapped into 44 * the aperture and look like contiguous pages from the GPU's 45 * perspective. A page table maps the pages in the aperture 46 * to the actual backing pages in system memory. 47 * 48 * Radeon GPUs support both an internal GART, as described above, 49 * and AGP. AGP works similarly, but the GART table is configured 50 * and maintained by the northbridge rather than the driver. 51 * Radeon hw has a separate AGP aperture that is programmed to 52 * point to the AGP aperture provided by the northbridge and the 53 * requests are passed through to the northbridge aperture. 54 * Both AGP and internal GART can be used at the same time, however 55 * that is not currently supported by the driver. 56 * 57 * This file handles the common internal GART management. 58 */ 59 60 /* 61 * Common GART table functions. 62 */ 63 64 /** 65 * amdgpu_gart_dummy_page_init - init dummy page used by the driver 66 * 67 * @adev: amdgpu_device pointer 68 * 69 * Allocate the dummy page used by the driver (all asics). 70 * This dummy page is used by the driver as a filler for gart entries 71 * when pages are taken out of the GART 72 * Returns 0 on sucess, -ENOMEM on failure. 73 */ 74 static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev) 75 { 76 struct vm_page *dummy_page = ttm_glob.dummy_read_page; 77 78 if (adev->dummy_page_addr) 79 return 0; 80 adev->dummy_page_addr = dma_map_page(&adev->pdev->dev, dummy_page, 0, 81 PAGE_SIZE, DMA_BIDIRECTIONAL); 82 if (dma_mapping_error(&adev->pdev->dev, adev->dummy_page_addr)) { 83 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); 84 adev->dummy_page_addr = 0; 85 return -ENOMEM; 86 } 87 return 0; 88 } 89 90 /** 91 * amdgpu_gart_dummy_page_fini - free dummy page used by the driver 92 * 93 * @adev: amdgpu_device pointer 94 * 95 * Frees the dummy page used by the driver (all asics). 96 */ 97 void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev) 98 { 99 if (!adev->dummy_page_addr) 100 return; 101 dma_unmap_page(&adev->pdev->dev, adev->dummy_page_addr, PAGE_SIZE, 102 DMA_BIDIRECTIONAL); 103 adev->dummy_page_addr = 0; 104 } 105 106 /** 107 * amdgpu_gart_table_ram_alloc - allocate system ram for gart page table 108 * 109 * @adev: amdgpu_device pointer 110 * 111 * Allocate system memory for GART page table for ASICs that don't have 112 * dedicated VRAM. 113 * Returns 0 for success, error for failure. 114 */ 115 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev) 116 { 117 STUB(); 118 return -ENOSYS; 119 #ifdef notyet 120 unsigned int order = get_order(adev->gart.table_size); 121 gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO; 122 struct amdgpu_bo *bo = NULL; 123 struct sg_table *sg = NULL; 124 struct amdgpu_bo_param bp; 125 dma_addr_t dma_addr; 126 struct vm_page *p; 127 int ret; 128 129 if (adev->gart.bo != NULL) 130 return 0; 131 132 p = alloc_pages(gfp_flags, order); 133 if (!p) 134 return -ENOMEM; 135 136 /* If the hardware does not support UTCL2 snooping of the CPU caches 137 * then set_memory_wc() could be used as a workaround to mark the pages 138 * as write combine memory. 139 */ 140 dma_addr = dma_map_page(&adev->pdev->dev, p, 0, adev->gart.table_size, 141 DMA_BIDIRECTIONAL); 142 if (dma_mapping_error(&adev->pdev->dev, dma_addr)) { 143 dev_err(&adev->pdev->dev, "Failed to DMA MAP the GART BO page\n"); 144 __free_pages(p, order); 145 p = NULL; 146 return -EFAULT; 147 } 148 149 dev_info(adev->dev, "%s dma_addr:%pad\n", __func__, &dma_addr); 150 /* Create SG table */ 151 sg = kmalloc(sizeof(*sg), GFP_KERNEL); 152 if (!sg) { 153 ret = -ENOMEM; 154 goto error; 155 } 156 ret = sg_alloc_table(sg, 1, GFP_KERNEL); 157 if (ret) 158 goto error; 159 160 sg_dma_address(sg->sgl) = dma_addr; 161 sg->sgl->length = adev->gart.table_size; 162 #ifdef CONFIG_NEED_SG_DMA_LENGTH 163 sg->sgl->dma_length = adev->gart.table_size; 164 #endif 165 /* Create SG BO */ 166 memset(&bp, 0, sizeof(bp)); 167 bp.size = adev->gart.table_size; 168 bp.byte_align = PAGE_SIZE; 169 bp.domain = AMDGPU_GEM_DOMAIN_CPU; 170 bp.type = ttm_bo_type_sg; 171 bp.resv = NULL; 172 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 173 bp.flags = 0; 174 ret = amdgpu_bo_create(adev, &bp, &bo); 175 if (ret) 176 goto error; 177 178 bo->tbo.sg = sg; 179 bo->tbo.ttm->sg = sg; 180 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 181 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; 182 183 ret = amdgpu_bo_reserve(bo, true); 184 if (ret) { 185 dev_err(adev->dev, "(%d) failed to reserve bo for GART system bo\n", ret); 186 goto error; 187 } 188 189 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); 190 WARN(ret, "Pinning the GART table failed"); 191 if (ret) 192 goto error_resv; 193 194 adev->gart.bo = bo; 195 adev->gart.ptr = page_to_virt(p); 196 /* Make GART table accessible in VMID0 */ 197 ret = amdgpu_ttm_alloc_gart(&adev->gart.bo->tbo); 198 if (ret) 199 amdgpu_gart_table_ram_free(adev); 200 amdgpu_bo_unreserve(bo); 201 202 return 0; 203 204 error_resv: 205 amdgpu_bo_unreserve(bo); 206 error: 207 amdgpu_bo_unref(&bo); 208 if (sg) { 209 sg_free_table(sg); 210 kfree(sg); 211 } 212 __free_pages(p, order); 213 return ret; 214 #endif 215 } 216 217 /** 218 * amdgpu_gart_table_ram_free - free gart page table system ram 219 * 220 * @adev: amdgpu_device pointer 221 * 222 * Free the system memory used for the GART page tableon ASICs that don't 223 * have dedicated VRAM. 224 */ 225 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev) 226 { 227 unsigned int order = get_order(adev->gart.table_size); 228 struct sg_table *sg = adev->gart.bo->tbo.sg; 229 struct vm_page *p; 230 int ret; 231 232 ret = amdgpu_bo_reserve(adev->gart.bo, false); 233 if (!ret) { 234 amdgpu_bo_unpin(adev->gart.bo); 235 amdgpu_bo_unreserve(adev->gart.bo); 236 } 237 amdgpu_bo_unref(&adev->gart.bo); 238 sg_free_table(sg); 239 kfree(sg); 240 p = virt_to_page(adev->gart.ptr); 241 __free_pages(p, order); 242 243 adev->gart.ptr = NULL; 244 } 245 246 /** 247 * amdgpu_gart_table_vram_alloc - allocate vram for gart page table 248 * 249 * @adev: amdgpu_device pointer 250 * 251 * Allocate video memory for GART page table 252 * (pcie r4xx, r5xx+). These asics require the 253 * gart table to be in video memory. 254 * Returns 0 for success, error for failure. 255 */ 256 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev) 257 { 258 if (adev->gart.bo != NULL) 259 return 0; 260 261 return amdgpu_bo_create_kernel(adev, adev->gart.table_size, PAGE_SIZE, 262 AMDGPU_GEM_DOMAIN_VRAM, &adev->gart.bo, 263 NULL, (void *)&adev->gart.ptr); 264 } 265 266 /** 267 * amdgpu_gart_table_vram_free - free gart page table vram 268 * 269 * @adev: amdgpu_device pointer 270 * 271 * Free the video memory used for the GART page table 272 * (pcie r4xx, r5xx+). These asics require the gart table to 273 * be in video memory. 274 */ 275 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev) 276 { 277 amdgpu_bo_free_kernel(&adev->gart.bo, NULL, (void *)&adev->gart.ptr); 278 } 279 280 /* 281 * Common gart functions. 282 */ 283 /** 284 * amdgpu_gart_unbind - unbind pages from the gart page table 285 * 286 * @adev: amdgpu_device pointer 287 * @offset: offset into the GPU's gart aperture 288 * @pages: number of pages to unbind 289 * 290 * Unbinds the requested pages from the gart page table and 291 * replaces them with the dummy page (all asics). 292 * Returns 0 for success, -EINVAL for failure. 293 */ 294 void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, 295 int pages) 296 { 297 unsigned t; 298 unsigned p; 299 int i, j; 300 u64 page_base; 301 /* Starting from VEGA10, system bit must be 0 to mean invalid. */ 302 uint64_t flags = 0; 303 int idx; 304 305 if (!adev->gart.ptr) 306 return; 307 308 if (!drm_dev_enter(adev_to_drm(adev), &idx)) 309 return; 310 311 t = offset / AMDGPU_GPU_PAGE_SIZE; 312 p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE; 313 for (i = 0; i < pages; i++, p++) { 314 page_base = adev->dummy_page_addr; 315 if (!adev->gart.ptr) 316 continue; 317 318 for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) { 319 amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr, 320 t, page_base, flags); 321 page_base += AMDGPU_GPU_PAGE_SIZE; 322 } 323 } 324 mb(); 325 amdgpu_device_flush_hdp(adev, NULL); 326 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) 327 amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); 328 329 drm_dev_exit(idx); 330 } 331 332 /** 333 * amdgpu_gart_map - map dma_addresses into GART entries 334 * 335 * @adev: amdgpu_device pointer 336 * @offset: offset into the GPU's gart aperture 337 * @pages: number of pages to bind 338 * @dma_addr: DMA addresses of pages 339 * @flags: page table entry flags 340 * @dst: CPU address of the gart table 341 * 342 * Map the dma_addresses into GART entries (all asics). 343 * Returns 0 for success, -EINVAL for failure. 344 */ 345 void amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset, 346 int pages, dma_addr_t *dma_addr, uint64_t flags, 347 void *dst) 348 { 349 uint64_t page_base; 350 unsigned i, j, t; 351 int idx; 352 353 if (!drm_dev_enter(adev_to_drm(adev), &idx)) 354 return; 355 356 t = offset / AMDGPU_GPU_PAGE_SIZE; 357 358 for (i = 0; i < pages; i++) { 359 page_base = dma_addr[i]; 360 for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) { 361 amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags); 362 page_base += AMDGPU_GPU_PAGE_SIZE; 363 } 364 } 365 drm_dev_exit(idx); 366 } 367 368 /** 369 * amdgpu_gart_bind - bind pages into the gart page table 370 * 371 * @adev: amdgpu_device pointer 372 * @offset: offset into the GPU's gart aperture 373 * @pages: number of pages to bind 374 * @dma_addr: DMA addresses of pages 375 * @flags: page table entry flags 376 * 377 * Binds the requested pages to the gart page table 378 * (all asics). 379 * Returns 0 for success, -EINVAL for failure. 380 */ 381 void amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, 382 int pages, dma_addr_t *dma_addr, 383 uint64_t flags) 384 { 385 if (!adev->gart.ptr) 386 return; 387 388 amdgpu_gart_map(adev, offset, pages, dma_addr, flags, adev->gart.ptr); 389 } 390 391 /** 392 * amdgpu_gart_invalidate_tlb - invalidate gart TLB 393 * 394 * @adev: amdgpu device driver pointer 395 * 396 * Invalidate gart TLB which can be use as a way to flush gart changes 397 * 398 */ 399 void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev) 400 { 401 int i; 402 403 if (!adev->gart.ptr) 404 return; 405 406 mb(); 407 amdgpu_device_flush_hdp(adev, NULL); 408 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) 409 amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); 410 } 411 412 /** 413 * amdgpu_gart_init - init the driver info for managing the gart 414 * 415 * @adev: amdgpu_device pointer 416 * 417 * Allocate the dummy page and init the gart driver info (all asics). 418 * Returns 0 for success, error for failure. 419 */ 420 int amdgpu_gart_init(struct amdgpu_device *adev) 421 { 422 int r; 423 424 if (adev->dummy_page_addr) 425 return 0; 426 427 /* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */ 428 if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) { 429 DRM_ERROR("Page size is smaller than GPU page size!\n"); 430 return -EINVAL; 431 } 432 r = amdgpu_gart_dummy_page_init(adev); 433 if (r) 434 return r; 435 /* Compute table size */ 436 adev->gart.num_cpu_pages = adev->gmc.gart_size / PAGE_SIZE; 437 adev->gart.num_gpu_pages = adev->gmc.gart_size / AMDGPU_GPU_PAGE_SIZE; 438 DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", 439 adev->gart.num_cpu_pages, adev->gart.num_gpu_pages); 440 441 return 0; 442 } 443