1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/pci.h> 30 #include <linux/vmalloc.h> 31 32 #include <drm/amdgpu_drm.h> 33 #ifdef CONFIG_X86 34 #include <asm/set_memory.h> 35 #endif 36 #include "amdgpu.h" 37 #include "amdgpu_reset.h" 38 #include <drm/drm_drv.h> 39 #include <drm/ttm/ttm_tt.h> 40 41 /* 42 * GART 43 * The GART (Graphics Aperture Remapping Table) is an aperture 44 * in the GPU's address space. System pages can be mapped into 45 * the aperture and look like contiguous pages from the GPU's 46 * perspective. A page table maps the pages in the aperture 47 * to the actual backing pages in system memory. 48 * 49 * Radeon GPUs support both an internal GART, as described above, 50 * and AGP. AGP works similarly, but the GART table is configured 51 * and maintained by the northbridge rather than the driver. 52 * Radeon hw has a separate AGP aperture that is programmed to 53 * point to the AGP aperture provided by the northbridge and the 54 * requests are passed through to the northbridge aperture. 55 * Both AGP and internal GART can be used at the same time, however 56 * that is not currently supported by the driver. 57 * 58 * This file handles the common internal GART management. 59 */ 60 61 /* 62 * Common GART table functions. 63 */ 64 65 /** 66 * amdgpu_gart_dummy_page_init - init dummy page used by the driver 67 * 68 * @adev: amdgpu_device pointer 69 * 70 * Allocate the dummy page used by the driver (all asics). 71 * This dummy page is used by the driver as a filler for gart entries 72 * when pages are taken out of the GART 73 * Returns 0 on sucess, -ENOMEM on failure. 74 */ 75 static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev) 76 { 77 struct vm_page *dummy_page = ttm_glob.dummy_read_page; 78 79 if (adev->dummy_page_addr) 80 return 0; 81 adev->dummy_page_addr = dma_map_page(&adev->pdev->dev, dummy_page, 0, 82 PAGE_SIZE, DMA_BIDIRECTIONAL); 83 if (dma_mapping_error(&adev->pdev->dev, adev->dummy_page_addr)) { 84 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); 85 adev->dummy_page_addr = 0; 86 return -ENOMEM; 87 } 88 return 0; 89 } 90 91 /** 92 * amdgpu_gart_dummy_page_fini - free dummy page used by the driver 93 * 94 * @adev: amdgpu_device pointer 95 * 96 * Frees the dummy page used by the driver (all asics). 97 */ 98 void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev) 99 { 100 if (!adev->dummy_page_addr) 101 return; 102 dma_unmap_page(&adev->pdev->dev, adev->dummy_page_addr, PAGE_SIZE, 103 DMA_BIDIRECTIONAL); 104 adev->dummy_page_addr = 0; 105 } 106 107 /** 108 * amdgpu_gart_table_ram_alloc - allocate system ram for gart page table 109 * 110 * @adev: amdgpu_device pointer 111 * 112 * Allocate system memory for GART page table for ASICs that don't have 113 * dedicated VRAM. 114 * Returns 0 for success, error for failure. 115 */ 116 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev) 117 { 118 STUB(); 119 return -ENOSYS; 120 #ifdef notyet 121 unsigned int order = get_order(adev->gart.table_size); 122 gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO; 123 struct amdgpu_bo *bo = NULL; 124 struct sg_table *sg = NULL; 125 struct amdgpu_bo_param bp; 126 dma_addr_t dma_addr; 127 struct vm_page *p; 128 int ret; 129 130 if (adev->gart.bo != NULL) 131 return 0; 132 133 p = alloc_pages(gfp_flags, order); 134 if (!p) 135 return -ENOMEM; 136 137 /* If the hardware does not support UTCL2 snooping of the CPU caches 138 * then set_memory_wc() could be used as a workaround to mark the pages 139 * as write combine memory. 140 */ 141 dma_addr = dma_map_page(&adev->pdev->dev, p, 0, adev->gart.table_size, 142 DMA_BIDIRECTIONAL); 143 if (dma_mapping_error(&adev->pdev->dev, dma_addr)) { 144 dev_err(&adev->pdev->dev, "Failed to DMA MAP the GART BO page\n"); 145 __free_pages(p, order); 146 p = NULL; 147 return -EFAULT; 148 } 149 150 dev_info(adev->dev, "%s dma_addr:%pad\n", __func__, &dma_addr); 151 /* Create SG table */ 152 sg = kmalloc(sizeof(*sg), GFP_KERNEL); 153 if (!sg) { 154 ret = -ENOMEM; 155 goto error; 156 } 157 ret = sg_alloc_table(sg, 1, GFP_KERNEL); 158 if (ret) 159 goto error; 160 161 sg_dma_address(sg->sgl) = dma_addr; 162 sg->sgl->length = adev->gart.table_size; 163 #ifdef CONFIG_NEED_SG_DMA_LENGTH 164 sg->sgl->dma_length = adev->gart.table_size; 165 #endif 166 /* Create SG BO */ 167 memset(&bp, 0, sizeof(bp)); 168 bp.size = adev->gart.table_size; 169 bp.byte_align = PAGE_SIZE; 170 bp.domain = AMDGPU_GEM_DOMAIN_CPU; 171 bp.type = ttm_bo_type_sg; 172 bp.resv = NULL; 173 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 174 bp.flags = 0; 175 ret = amdgpu_bo_create(adev, &bp, &bo); 176 if (ret) 177 goto error; 178 179 bo->tbo.sg = sg; 180 bo->tbo.ttm->sg = sg; 181 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 182 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; 183 184 ret = amdgpu_bo_reserve(bo, true); 185 if (ret) { 186 dev_err(adev->dev, "(%d) failed to reserve bo for GART system bo\n", ret); 187 goto error; 188 } 189 190 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); 191 WARN(ret, "Pinning the GART table failed"); 192 if (ret) 193 goto error_resv; 194 195 adev->gart.bo = bo; 196 adev->gart.ptr = page_to_virt(p); 197 /* Make GART table accessible in VMID0 */ 198 ret = amdgpu_ttm_alloc_gart(&adev->gart.bo->tbo); 199 if (ret) 200 amdgpu_gart_table_ram_free(adev); 201 amdgpu_bo_unreserve(bo); 202 203 return 0; 204 205 error_resv: 206 amdgpu_bo_unreserve(bo); 207 error: 208 amdgpu_bo_unref(&bo); 209 if (sg) { 210 sg_free_table(sg); 211 kfree(sg); 212 } 213 __free_pages(p, order); 214 return ret; 215 #endif 216 } 217 218 /** 219 * amdgpu_gart_table_ram_free - free gart page table system ram 220 * 221 * @adev: amdgpu_device pointer 222 * 223 * Free the system memory used for the GART page tableon ASICs that don't 224 * have dedicated VRAM. 225 */ 226 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev) 227 { 228 unsigned int order = get_order(adev->gart.table_size); 229 struct sg_table *sg = adev->gart.bo->tbo.sg; 230 struct vm_page *p; 231 int ret; 232 233 ret = amdgpu_bo_reserve(adev->gart.bo, false); 234 if (!ret) { 235 amdgpu_bo_unpin(adev->gart.bo); 236 amdgpu_bo_unreserve(adev->gart.bo); 237 } 238 amdgpu_bo_unref(&adev->gart.bo); 239 sg_free_table(sg); 240 kfree(sg); 241 p = virt_to_page(adev->gart.ptr); 242 __free_pages(p, order); 243 244 adev->gart.ptr = NULL; 245 } 246 247 /** 248 * amdgpu_gart_table_vram_alloc - allocate vram for gart page table 249 * 250 * @adev: amdgpu_device pointer 251 * 252 * Allocate video memory for GART page table 253 * (pcie r4xx, r5xx+). These asics require the 254 * gart table to be in video memory. 255 * Returns 0 for success, error for failure. 256 */ 257 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev) 258 { 259 if (adev->gart.bo != NULL) 260 return 0; 261 262 return amdgpu_bo_create_kernel(adev, adev->gart.table_size, PAGE_SIZE, 263 AMDGPU_GEM_DOMAIN_VRAM, &adev->gart.bo, 264 NULL, (void *)&adev->gart.ptr); 265 } 266 267 /** 268 * amdgpu_gart_table_vram_free - free gart page table vram 269 * 270 * @adev: amdgpu_device pointer 271 * 272 * Free the video memory used for the GART page table 273 * (pcie r4xx, r5xx+). These asics require the gart table to 274 * be in video memory. 275 */ 276 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev) 277 { 278 amdgpu_bo_free_kernel(&adev->gart.bo, NULL, (void *)&adev->gart.ptr); 279 } 280 281 /* 282 * Common gart functions. 283 */ 284 /** 285 * amdgpu_gart_unbind - unbind pages from the gart page table 286 * 287 * @adev: amdgpu_device pointer 288 * @offset: offset into the GPU's gart aperture 289 * @pages: number of pages to unbind 290 * 291 * Unbinds the requested pages from the gart page table and 292 * replaces them with the dummy page (all asics). 293 * Returns 0 for success, -EINVAL for failure. 294 */ 295 void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, 296 int pages) 297 { 298 unsigned t; 299 unsigned p; 300 int i, j; 301 u64 page_base; 302 /* Starting from VEGA10, system bit must be 0 to mean invalid. */ 303 uint64_t flags = 0; 304 int idx; 305 306 if (!adev->gart.ptr) 307 return; 308 309 if (!drm_dev_enter(adev_to_drm(adev), &idx)) 310 return; 311 312 t = offset / AMDGPU_GPU_PAGE_SIZE; 313 p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE; 314 for (i = 0; i < pages; i++, p++) { 315 page_base = adev->dummy_page_addr; 316 if (!adev->gart.ptr) 317 continue; 318 319 for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) { 320 amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr, 321 t, page_base, flags); 322 page_base += AMDGPU_GPU_PAGE_SIZE; 323 } 324 } 325 mb(); 326 amdgpu_device_flush_hdp(adev, NULL); 327 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) 328 amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); 329 330 drm_dev_exit(idx); 331 } 332 333 /** 334 * amdgpu_gart_map - map dma_addresses into GART entries 335 * 336 * @adev: amdgpu_device pointer 337 * @offset: offset into the GPU's gart aperture 338 * @pages: number of pages to bind 339 * @dma_addr: DMA addresses of pages 340 * @flags: page table entry flags 341 * @dst: CPU address of the gart table 342 * 343 * Map the dma_addresses into GART entries (all asics). 344 * Returns 0 for success, -EINVAL for failure. 345 */ 346 void amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset, 347 int pages, dma_addr_t *dma_addr, uint64_t flags, 348 void *dst) 349 { 350 uint64_t page_base; 351 unsigned i, j, t; 352 int idx; 353 354 if (!drm_dev_enter(adev_to_drm(adev), &idx)) 355 return; 356 357 t = offset / AMDGPU_GPU_PAGE_SIZE; 358 359 for (i = 0; i < pages; i++) { 360 page_base = dma_addr[i]; 361 for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) { 362 amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags); 363 page_base += AMDGPU_GPU_PAGE_SIZE; 364 } 365 } 366 drm_dev_exit(idx); 367 } 368 369 /** 370 * amdgpu_gart_bind - bind pages into the gart page table 371 * 372 * @adev: amdgpu_device pointer 373 * @offset: offset into the GPU's gart aperture 374 * @pages: number of pages to bind 375 * @dma_addr: DMA addresses of pages 376 * @flags: page table entry flags 377 * 378 * Binds the requested pages to the gart page table 379 * (all asics). 380 * Returns 0 for success, -EINVAL for failure. 381 */ 382 void amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, 383 int pages, dma_addr_t *dma_addr, 384 uint64_t flags) 385 { 386 if (!adev->gart.ptr) 387 return; 388 389 amdgpu_gart_map(adev, offset, pages, dma_addr, flags, adev->gart.ptr); 390 } 391 392 /** 393 * amdgpu_gart_invalidate_tlb - invalidate gart TLB 394 * 395 * @adev: amdgpu device driver pointer 396 * 397 * Invalidate gart TLB which can be use as a way to flush gart changes 398 * 399 */ 400 void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev) 401 { 402 int i; 403 404 if (!adev->gart.ptr) 405 return; 406 407 mb(); 408 if (down_read_trylock(&adev->reset_domain->sem)) { 409 amdgpu_device_flush_hdp(adev, NULL); 410 up_read(&adev->reset_domain->sem); 411 } 412 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) 413 amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); 414 } 415 416 /** 417 * amdgpu_gart_init - init the driver info for managing the gart 418 * 419 * @adev: amdgpu_device pointer 420 * 421 * Allocate the dummy page and init the gart driver info (all asics). 422 * Returns 0 for success, error for failure. 423 */ 424 int amdgpu_gart_init(struct amdgpu_device *adev) 425 { 426 int r; 427 428 if (adev->dummy_page_addr) 429 return 0; 430 431 /* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */ 432 if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) { 433 DRM_ERROR("Page size is smaller than GPU page size!\n"); 434 return -EINVAL; 435 } 436 r = amdgpu_gart_dummy_page_init(adev); 437 if (r) 438 return r; 439 /* Compute table size */ 440 adev->gart.num_cpu_pages = adev->gmc.gart_size / PAGE_SIZE; 441 adev->gart.num_gpu_pages = adev->gmc.gart_size / AMDGPU_GPU_PAGE_SIZE; 442 DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", 443 adev->gart.num_cpu_pages, adev->gart.num_gpu_pages); 444 445 return 0; 446 } 447