1 /* $OpenBSD: dwmmc.c,v 1.27 2022/06/09 14:43:28 kettenis Exp $ */ 2 /* 3 * Copyright (c) 2017 Mark Kettenis 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <sys/param.h> 19 #include <sys/kernel.h> 20 #include <sys/malloc.h> 21 #include <sys/systm.h> 22 23 #include <machine/bus.h> 24 #include <machine/fdt.h> 25 #include <machine/intr.h> 26 27 #include <dev/ofw/openfirm.h> 28 #include <dev/ofw/ofw_clock.h> 29 #include <dev/ofw/ofw_gpio.h> 30 #include <dev/ofw/ofw_pinctrl.h> 31 #include <dev/ofw/fdt.h> 32 33 #include <dev/sdmmc/sdmmcvar.h> 34 #include <dev/sdmmc/sdmmc_ioreg.h> 35 36 #define SDMMC_CTRL 0x0000 37 #define SDMMC_CTRL_USE_INTERNAL_DMAC (1 << 25) 38 #define SDMMC_CTRL_DMA_ENABLE (1 << 5) 39 #define SDMMC_CTRL_INT_ENABLE (1 << 4) 40 #define SDMMC_CTRL_DMA_RESET (1 << 2) 41 #define SDMMC_CTRL_FIFO_RESET (1 << 1) 42 #define SDMMC_CTRL_CONTROLLER_RESET (1 << 0) 43 #define SDMMC_CTRL_ALL_RESET (SDMMC_CTRL_CONTROLLER_RESET | \ 44 SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET) 45 #define SDMMC_PWREN 0x0004 46 #define SDMMC_CLKDIV 0x0008 47 #define SDMMC_CLKSRC 0x000c 48 #define SDMMC_CLKENA 0x0010 49 #define SDMMC_CLKENA_CCLK_LOW_POWER (1 << 16) 50 #define SDMMC_CLKENA_CCLK_ENABLE (1 << 0) 51 #define SDMMC_TMOUT 0x0014 52 #define SDMMC_CTYPE 0x0018 53 #define SDMMC_CTYPE_8BIT (1 << 16) 54 #define SDMMC_CTYPE_4BIT (1 << 0) 55 #define SDMMC_BLKSIZ 0x001c 56 #define SDMMC_BYTCNT 0x0020 57 #define SDMMC_INTMASK 0x0024 58 #define SDMMC_CMDARG 0x0028 59 #define SDMMC_CMD 0x002c 60 #define SDMMC_CMD_START_CMD (1U << 31) 61 #define SDMMC_CMD_USE_HOLD_REG (1 << 29) 62 #define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY (1 << 21) 63 #define SDMMC_CMD_SEND_INITIALIZATION (1 << 15) 64 #define SDMMC_CMD_STOP_ABORT_CMD (1 << 14) 65 #define SDMMC_CMD_WAIT_PRVDATA_COMPLETE (1 << 13) 66 #define SDMMC_CMD_SEND_AUTO_STOP (1 << 12) 67 #define SDMMC_CMD_WR (1 << 10) 68 #define SDMMC_CMD_DATA_EXPECTED (1 << 9) 69 #define SDMMC_CMD_CHECK_REPONSE_CRC (1 << 8) 70 #define SDMMC_CMD_RESPONSE_LENGTH (1 << 7) 71 #define SDMMC_CMD_RESPONSE_EXPECT (1 << 6) 72 #define SDMMC_RESP0 0x0030 73 #define SDMMC_RESP1 0x0034 74 #define SDMMC_RESP2 0x0038 75 #define SDMMC_RESP3 0x003c 76 #define SDMMC_MINTSTS 0x0040 77 #define SDMMC_RINTSTS 0x0044 78 #define SDMMC_RINTSTS_SDIO (1 << 24) 79 #define SDMMC_RINTSTS_EBE (1 << 15) 80 #define SDMMC_RINTSTS_ACD (1 << 14) 81 #define SDMMC_RINTSTS_SBE (1 << 13) 82 #define SDMMC_RINTSTS_HLE (1 << 12) 83 #define SDMMC_RINTSTS_FRUN (1 << 11) 84 #define SDMMC_RINTSTS_HTO (1 << 10) 85 #define SDMMC_RINTSTS_DRTO (1 << 9) 86 #define SDMMC_RINTSTS_RTO (1 << 8) 87 #define SDMMC_RINTSTS_DCRC (1 << 7) 88 #define SDMMC_RINTSTS_RCRC (1 << 6) 89 #define SDMMC_RINTSTS_RXDR (1 << 5) 90 #define SDMMC_RINTSTS_TXDR (1 << 4) 91 #define SDMMC_RINTSTS_DTO (1 << 3) 92 #define SDMMC_RINTSTS_CD (1 << 2) 93 #define SDMMC_RINTSTS_RE (1 << 1) 94 #define SDMMC_RINTSTS_CDT (1 << 0) 95 #define SDMMC_RINTSTS_DATA_ERR (SDMMC_RINTSTS_EBE | SDMMC_RINTSTS_SBE | \ 96 SDMMC_RINTSTS_HLE | SDMMC_RINTSTS_FRUN | SDMMC_RINTSTS_DCRC) 97 #define SDMMC_RINTSTS_DATA_TO (SDMMC_RINTSTS_HTO | SDMMC_RINTSTS_DRTO) 98 #define SDMMC_STATUS 0x0048 99 #define SDMMC_STATUS_FIFO_COUNT(x) (((x) >> 17) & 0x1fff) 100 #define SDMMC_STATUS_DATA_BUSY (1 << 9) 101 #define SDMMC_FIFOTH 0x004c 102 #define SDMMC_FIFOTH_MSIZE_SHIFT 28 103 #define SDMMC_FIFOTH_RXWM_SHIFT 16 104 #define SDMMC_FIFOTH_RXWM(x) (((x) >> 16) & 0xfff) 105 #define SDMMC_FIFOTH_TXWM_SHIFT 0 106 #define SDMMC_CDETECT 0x0050 107 #define SDMMC_CDETECT_CARD_DETECT_0 (1 << 0) 108 #define SDMMC_WRTPRT 0x0054 109 #define SDMMC_TCBCNT 0x005c 110 #define SDMMC_TBBCNT 0x0060 111 #define SDMMC_DEBNCE 0x0064 112 #define SDMMC_USRID 0x0068 113 #define SDMMC_VERID 0x006c 114 #define SDMMC_HCON 0x0070 115 #define SDMMC_HCON_DATA_WIDTH(x) (((x) >> 7) & 0x7) 116 #define SDMMC_HCON_DMA64 (1 << 27) 117 #define SDMMC_UHS_REG 0x0074 118 #define SDMMC_RST_n 0x0078 119 #define SDMMC_BMOD 0x0080 120 #define SDMMC_BMOD_DE (1 << 7) 121 #define SDMMC_BMOD_FB (1 << 1) 122 #define SDMMC_BMOD_SWR (1 << 0) 123 #define SDMMC_PLDMND 0x0084 124 #define SDMMC_DBADDR 0x0088 125 #define SDMMC_IDSTS32 0x008c 126 #define SDMMC_IDSTS_NIS (1 << 8) 127 #define SDMMC_IDSTS_RI (1 << 1) 128 #define SDMMC_IDSTS_TI (1 << 0) 129 #define SDMMC_IDINTEN32 0x0090 130 #define SDMMC_IDINTEN_NI (1 << 8) 131 #define SDMMC_IDINTEN_RI (1 << 1) 132 #define SDMMC_IDINTEN_TI (1 << 0) 133 #define SDMMC_DSCADDR 0x0094 134 #define SDMMC_BUFADDR 0x0098 135 #define SDMMC_CLKSEL 0x009c 136 #define SDMMC_CARDTHRCTL 0x0100 137 #define SDMMC_CARDTHRCTL_RDTHR_SHIFT 16 138 #define SDMMC_CARDTHRCTL_RDTHREN (1 << 0) 139 #define SDMMC_BACK_END_POWER 0x0104 140 #define SDMMC_EMMC_DDR_REG 0x0108 141 #define SDMMC_FIFO_BASE 0x0200 142 143 #define SDMMC_DBADDRL 0x0088 144 #define SDMMC_DBADDRH 0x008c 145 #define SDMMC_IDSTS64 0x0090 146 #define SDMMC_IDINTEN64 0x0094 147 #define SDMMC_DSCADDRL 0x0098 148 #define SDMMC_DSCADDRH 0x009c 149 #define SDMMC_BUFADDRL 0x00a0 150 #define SDMMC_BUFADDRH 0x00a4 151 152 #define SDMMC_IDSTS(sc) \ 153 ((sc)->sc_dma64 ? SDMMC_IDSTS64 : SDMMC_IDSTS32) 154 155 #define HREAD4(sc, reg) \ 156 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) 157 #define HWRITE4(sc, reg, val) \ 158 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 159 #define HSET4(sc, reg, bits) \ 160 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits)) 161 #define HCLR4(sc, reg, bits) \ 162 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits)) 163 164 struct dwmmc_desc32 { 165 uint32_t des[4]; 166 }; 167 168 struct dwmmc_desc64 { 169 uint32_t des[8]; 170 }; 171 172 #define DWMMC_NDESC (PAGE_SIZE / sizeof(struct dwmmc_desc64)) 173 #define DWMMC_MAXSEGSZ 0x1000 174 175 #define DES0_OWN (1U << 31) 176 #define DES0_CES (1 << 30) 177 #define DES0_ER (1 << 5) 178 #define DES0_CH (1 << 4) 179 #define DES0_FS (1 << 3) 180 #define DES0_LD (1 << 2) 181 #define DES0_DIC (1 << 1) 182 183 #define DES1_BS2(sz) (((sz) & 0x1fff) << 13) 184 #define DES1_BS1(sz) (((sz) & 0x1fff) << 0) 185 #define DES2_BS2(sz) DES1_BS2(sz) 186 #define DES2_BS1(sz) DES1_BS1(sz) 187 188 struct dwmmc_softc { 189 struct device sc_dev; 190 bus_space_tag_t sc_iot; 191 bus_space_handle_t sc_ioh; 192 bus_size_t sc_size; 193 bus_dma_tag_t sc_dmat; 194 bus_dmamap_t sc_dmap; 195 int sc_node; 196 197 void *sc_ih; 198 199 uint32_t sc_clkbase; 200 uint32_t sc_fifo_depth; 201 uint32_t sc_fifo_width; 202 void (*sc_read_data)(struct dwmmc_softc *, u_char *, int); 203 void (*sc_write_data)(struct dwmmc_softc *, u_char *, int); 204 int sc_blklen; 205 206 bus_dmamap_t sc_desc_map; 207 bus_dma_segment_t sc_desc_segs[1]; 208 caddr_t sc_desc; 209 int sc_dma64; 210 int sc_dmamode; 211 uint32_t sc_idsts; 212 213 uint32_t sc_gpio[4]; 214 int sc_sdio_irq; 215 uint32_t sc_pwrseq; 216 uint32_t sc_vdd; 217 218 struct device *sc_sdmmc; 219 }; 220 221 int dwmmc_match(struct device *, void *, void *); 222 void dwmmc_attach(struct device *, struct device *, void *); 223 224 const struct cfattach dwmmc_ca = { 225 sizeof(struct dwmmc_softc), dwmmc_match, dwmmc_attach 226 }; 227 228 struct cfdriver dwmmc_cd = { 229 NULL, "dwmmc", DV_DULL 230 }; 231 232 int dwmmc_intr(void *); 233 234 int dwmmc_host_reset(sdmmc_chipset_handle_t); 235 uint32_t dwmmc_host_ocr(sdmmc_chipset_handle_t); 236 int dwmmc_host_maxblklen(sdmmc_chipset_handle_t); 237 int dwmmc_card_detect(sdmmc_chipset_handle_t); 238 int dwmmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 239 int dwmmc_bus_clock(sdmmc_chipset_handle_t, int, int); 240 int dwmmc_bus_width(sdmmc_chipset_handle_t, int); 241 void dwmmc_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *); 242 void dwmmc_card_intr_mask(sdmmc_chipset_handle_t, int); 243 void dwmmc_card_intr_ack(sdmmc_chipset_handle_t); 244 245 struct sdmmc_chip_functions dwmmc_chip_functions = { 246 .host_reset = dwmmc_host_reset, 247 .host_ocr = dwmmc_host_ocr, 248 .host_maxblklen = dwmmc_host_maxblklen, 249 .card_detect = dwmmc_card_detect, 250 .bus_power = dwmmc_bus_power, 251 .bus_clock = dwmmc_bus_clock, 252 .bus_width = dwmmc_bus_width, 253 .exec_command = dwmmc_exec_command, 254 .card_intr_mask = dwmmc_card_intr_mask, 255 .card_intr_ack = dwmmc_card_intr_ack, 256 }; 257 258 void dwmmc_pio_mode(struct dwmmc_softc *); 259 int dwmmc_alloc_descriptors(struct dwmmc_softc *); 260 void dwmmc_init_descriptors(struct dwmmc_softc *); 261 void dwmmc_transfer_data(struct dwmmc_softc *, struct sdmmc_command *); 262 void dwmmc_read_data32(struct dwmmc_softc *, u_char *, int); 263 void dwmmc_write_data32(struct dwmmc_softc *, u_char *, int); 264 void dwmmc_read_data64(struct dwmmc_softc *, u_char *, int); 265 void dwmmc_write_data64(struct dwmmc_softc *, u_char *, int); 266 void dwmmc_pwrseq_pre(uint32_t); 267 void dwmmc_pwrseq_post(uint32_t); 268 269 int 270 dwmmc_match(struct device *parent, void *match, void *aux) 271 { 272 struct fdt_attach_args *faa = aux; 273 274 return (OF_is_compatible(faa->fa_node, "hisilicon,hi3660-dw-mshc") || 275 OF_is_compatible(faa->fa_node, "hisilicon,hi3670-dw-mshc") || 276 OF_is_compatible(faa->fa_node, "rockchip,rk3288-dw-mshc") || 277 OF_is_compatible(faa->fa_node, "samsung,exynos5420-dw-mshc") || 278 OF_is_compatible(faa->fa_node, "snps,dw-mshc")); 279 } 280 281 void 282 dwmmc_attach(struct device *parent, struct device *self, void *aux) 283 { 284 struct dwmmc_softc *sc = (struct dwmmc_softc *)self; 285 struct fdt_attach_args *faa = aux; 286 struct sdmmcbus_attach_args saa; 287 uint32_t freq = 0, div = 0; 288 uint32_t hcon, width; 289 uint32_t fifoth; 290 int error, timeout; 291 292 if (faa->fa_nreg < 1) { 293 printf(": no registers\n"); 294 return; 295 } 296 297 sc->sc_node = faa->fa_node; 298 sc->sc_iot = faa->fa_iot; 299 sc->sc_size = faa->fa_reg[0].size; 300 301 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, 302 faa->fa_reg[0].size, 0, &sc->sc_ioh)) { 303 printf(": can't map registers\n"); 304 return; 305 } 306 307 pinctrl_byname(faa->fa_node, "default"); 308 309 clock_enable_all(faa->fa_node); 310 reset_deassert_all(faa->fa_node); 311 312 /* 313 * Determine FIFO width from hardware configuration register. 314 * We only support 32-bit and 64-bit FIFOs. 315 */ 316 hcon = HREAD4(sc, SDMMC_HCON); 317 switch (SDMMC_HCON_DATA_WIDTH(hcon)) { 318 case 1: 319 sc->sc_fifo_width = 4; 320 sc->sc_read_data = dwmmc_read_data32; 321 sc->sc_write_data = dwmmc_write_data32; 322 break; 323 case 2: 324 sc->sc_fifo_width = 8; 325 sc->sc_read_data = dwmmc_read_data64; 326 sc->sc_write_data = dwmmc_write_data64; 327 break; 328 default: 329 printf(": unsupported FIFO width\n"); 330 return; 331 } 332 333 sc->sc_fifo_depth = OF_getpropint(faa->fa_node, "fifo-depth", 0); 334 if (sc->sc_fifo_depth == 0) { 335 fifoth = HREAD4(sc, SDMMC_FIFOTH); 336 sc->sc_fifo_depth = SDMMC_FIFOTH_RXWM(fifoth) + 1; 337 } 338 339 if (hcon & SDMMC_HCON_DMA64) 340 sc->sc_dma64 = 1; 341 342 /* Some SoCs pre-divide the clock. */ 343 if (OF_is_compatible(faa->fa_node, "rockchip,rk3288-dw-mshc")) 344 div = 1; 345 if (OF_is_compatible(faa->fa_node, "hisilicon,hi3660-dw-mshc") || 346 OF_is_compatible(faa->fa_node, "hisilicon,hi3670-dw-mshc")) 347 div = 7; 348 349 /* Force the base clock to 50MHz on Rockchip SoCs. */ 350 if (OF_is_compatible(faa->fa_node, "rockchip,rk3288-dw-mshc")) 351 freq = 50000000; 352 353 freq = OF_getpropint(faa->fa_node, "clock-frequency", freq); 354 if (freq > 0) 355 clock_set_frequency(faa->fa_node, "ciu", (div + 1) * freq); 356 357 sc->sc_clkbase = clock_get_frequency(faa->fa_node, "ciu"); 358 /* if ciu clock is missing the rate is clock-frequency */ 359 if (sc->sc_clkbase == 0) 360 sc->sc_clkbase = freq; 361 div = OF_getpropint(faa->fa_node, "samsung,dw-mshc-ciu-div", div); 362 sc->sc_clkbase /= (div + 1); 363 364 sc->sc_ih = fdt_intr_establish(faa->fa_node, IPL_BIO, 365 dwmmc_intr, sc, sc->sc_dev.dv_xname); 366 if (sc->sc_ih == NULL) { 367 printf(": can't establish interrupt\n"); 368 goto unmap; 369 } 370 371 OF_getpropintarray(faa->fa_node, "cd-gpios", sc->sc_gpio, 372 sizeof(sc->sc_gpio)); 373 if (sc->sc_gpio[0]) 374 gpio_controller_config_pin(sc->sc_gpio, GPIO_CONFIG_INPUT); 375 376 sc->sc_sdio_irq = (OF_getproplen(sc->sc_node, "cap-sdio-irq") == 0); 377 sc->sc_pwrseq = OF_getpropint(sc->sc_node, "mmc-pwrseq", 0); 378 379 printf(": %d MHz base clock\n", sc->sc_clkbase / 1000000); 380 381 HSET4(sc, SDMMC_CTRL, SDMMC_CTRL_ALL_RESET); 382 for (timeout = 5000; timeout > 0; timeout--) { 383 if ((HREAD4(sc, SDMMC_CTRL) & SDMMC_CTRL_ALL_RESET) == 0) 384 break; 385 delay(100); 386 } 387 if (timeout == 0) 388 printf("%s: reset failed\n", sc->sc_dev.dv_xname); 389 390 /* Enable interrupts, but mask them all. */ 391 HWRITE4(sc, SDMMC_INTMASK, 0); 392 HWRITE4(sc, SDMMC_RINTSTS, 0xffffffff); 393 HSET4(sc, SDMMC_CTRL, SDMMC_CTRL_INT_ENABLE); 394 395 dwmmc_bus_width(sc, 1); 396 397 /* Start out in non-DMA mode. */ 398 dwmmc_pio_mode(sc); 399 400 sc->sc_dmat = faa->fa_dmat; 401 dwmmc_alloc_descriptors(sc); 402 dwmmc_init_descriptors(sc); 403 404 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, DWMMC_NDESC, 405 DWMMC_MAXSEGSZ, 0, BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW, &sc->sc_dmap); 406 if (error) { 407 printf(": can't create DMA map\n"); 408 goto unmap; 409 } 410 411 memset(&saa, 0, sizeof(saa)); 412 saa.saa_busname = "sdmmc"; 413 saa.sct = &dwmmc_chip_functions; 414 saa.sch = sc; 415 saa.dmat = sc->sc_dmat; 416 saa.dmap = sc->sc_dmap; 417 saa.caps |= SMC_CAPS_DMA; 418 419 if (OF_getproplen(sc->sc_node, "cap-mmc-highspeed") == 0) 420 saa.caps |= SMC_CAPS_MMC_HIGHSPEED; 421 if (OF_getproplen(sc->sc_node, "cap-sd-highspeed") == 0) 422 saa.caps |= SMC_CAPS_SD_HIGHSPEED; 423 424 width = OF_getpropint(faa->fa_node, "bus-width", 1); 425 if (width >= 8) 426 saa.caps |= SMC_CAPS_8BIT_MODE; 427 if (width >= 4) 428 saa.caps |= SMC_CAPS_4BIT_MODE; 429 430 sc->sc_sdmmc = config_found(self, &saa, NULL); 431 return; 432 433 unmap: 434 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_size); 435 } 436 437 int 438 dwmmc_alloc_descriptors(struct dwmmc_softc *sc) 439 { 440 int error, rseg; 441 442 /* Allocate descriptor memory */ 443 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 444 PAGE_SIZE, sc->sc_desc_segs, 1, &rseg, 445 BUS_DMA_WAITOK | BUS_DMA_ZERO); 446 if (error) 447 return error; 448 error = bus_dmamem_map(sc->sc_dmat, sc->sc_desc_segs, rseg, 449 PAGE_SIZE, &sc->sc_desc, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 450 if (error) { 451 bus_dmamem_free(sc->sc_dmat, sc->sc_desc_segs, rseg); 452 return error; 453 } 454 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 455 0, BUS_DMA_WAITOK, &sc->sc_desc_map); 456 if (error) { 457 bus_dmamem_unmap(sc->sc_dmat, sc->sc_desc, PAGE_SIZE); 458 bus_dmamem_free(sc->sc_dmat, sc->sc_desc_segs, rseg); 459 return error; 460 } 461 error = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_map, 462 sc->sc_desc, PAGE_SIZE, NULL, BUS_DMA_WAITOK | BUS_DMA_WRITE); 463 if (error) { 464 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_map); 465 bus_dmamem_unmap(sc->sc_dmat, sc->sc_desc, PAGE_SIZE); 466 bus_dmamem_free(sc->sc_dmat, sc->sc_desc_segs, rseg); 467 return error; 468 } 469 470 return 0; 471 } 472 473 void 474 dwmmc_init_descriptors32(struct dwmmc_softc *sc) 475 { 476 struct dwmmc_desc32 *desc; 477 bus_addr_t addr; 478 int i; 479 480 desc = (void *)sc->sc_desc; 481 addr = sc->sc_desc_map->dm_segs[0].ds_addr; 482 for (i = 0; i < DWMMC_NDESC; i++) { 483 addr += sizeof(struct dwmmc_desc32); 484 desc[i].des[3] = addr; 485 } 486 desc[DWMMC_NDESC - 1].des[3] = sc->sc_desc_map->dm_segs[0].ds_addr; 487 desc[DWMMC_NDESC - 1].des[0] = DES0_ER; 488 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0, 489 PAGE_SIZE, BUS_DMASYNC_PREWRITE); 490 491 HWRITE4(sc, SDMMC_IDSTS32, 0xffffffff); 492 HWRITE4(sc, SDMMC_IDINTEN32, 493 SDMMC_IDINTEN_NI | SDMMC_IDINTEN_RI | SDMMC_IDINTEN_TI); 494 HWRITE4(sc, SDMMC_DBADDR, sc->sc_desc_map->dm_segs[0].ds_addr); 495 } 496 497 void 498 dwmmc_init_descriptors64(struct dwmmc_softc *sc) 499 { 500 struct dwmmc_desc64 *desc; 501 bus_addr_t addr; 502 int i; 503 504 desc = (void *)sc->sc_desc; 505 addr = sc->sc_desc_map->dm_segs[0].ds_addr; 506 for (i = 0; i < DWMMC_NDESC; i++) { 507 addr += sizeof(struct dwmmc_desc64); 508 desc[i].des[6] = addr; 509 desc[i].des[7] = (uint64_t)addr >> 32; 510 } 511 desc[DWMMC_NDESC - 1].des[6] = sc->sc_desc_map->dm_segs[0].ds_addr; 512 desc[DWMMC_NDESC - 1].des[7] = 513 (uint64_t)sc->sc_desc_map->dm_segs[0].ds_addr >> 32; 514 desc[DWMMC_NDESC - 1].des[0] = DES0_ER; 515 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0, 516 PAGE_SIZE, BUS_DMASYNC_PREWRITE); 517 518 HWRITE4(sc, SDMMC_IDSTS64, 0xffffffff); 519 HWRITE4(sc, SDMMC_IDINTEN64, 520 SDMMC_IDINTEN_NI | SDMMC_IDINTEN_RI | SDMMC_IDINTEN_TI); 521 HWRITE4(sc, SDMMC_DBADDRL, sc->sc_desc_map->dm_segs[0].ds_addr); 522 HWRITE4(sc, SDMMC_DBADDRH, 523 (uint64_t)sc->sc_desc_map->dm_segs[0].ds_addr >> 32); 524 } 525 526 void 527 dwmmc_init_descriptors(struct dwmmc_softc *sc) 528 { 529 if (sc->sc_dma64) 530 dwmmc_init_descriptors64(sc); 531 else 532 dwmmc_init_descriptors32(sc); 533 } 534 535 int 536 dwmmc_intr(void *arg) 537 { 538 struct dwmmc_softc *sc = arg; 539 uint32_t stat; 540 int handled = 0; 541 542 stat = HREAD4(sc, SDMMC_IDSTS(sc)); 543 if (stat) { 544 HWRITE4(sc, SDMMC_IDSTS(sc), stat); 545 sc->sc_idsts |= stat; 546 wakeup(&sc->sc_idsts); 547 handled = 1; 548 } 549 550 stat = HREAD4(sc, SDMMC_MINTSTS); 551 if (stat & SDMMC_RINTSTS_SDIO) { 552 HWRITE4(sc, SDMMC_RINTSTS, SDMMC_RINTSTS_SDIO); 553 HCLR4(sc, SDMMC_INTMASK, SDMMC_RINTSTS_SDIO); 554 sdmmc_card_intr(sc->sc_sdmmc); 555 handled = 1; 556 } 557 558 return handled; 559 } 560 561 void 562 dwmmc_card_intr_mask(sdmmc_chipset_handle_t sch, int enable) 563 { 564 struct dwmmc_softc *sc = sch; 565 566 if (enable) 567 HSET4(sc, SDMMC_INTMASK, SDMMC_RINTSTS_SDIO); 568 else 569 HCLR4(sc, SDMMC_INTMASK, SDMMC_RINTSTS_SDIO); 570 } 571 572 void 573 dwmmc_card_intr_ack(sdmmc_chipset_handle_t sch) 574 { 575 struct dwmmc_softc *sc = sch; 576 577 HSET4(sc, SDMMC_INTMASK, SDMMC_RINTSTS_SDIO); 578 } 579 580 int 581 dwmmc_host_reset(sdmmc_chipset_handle_t sch) 582 { 583 printf("%s\n", __func__); 584 return 0; 585 } 586 587 uint32_t 588 dwmmc_host_ocr(sdmmc_chipset_handle_t sch) 589 { 590 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V; 591 } 592 593 int 594 dwmmc_host_maxblklen(sdmmc_chipset_handle_t sch) 595 { 596 return 512; 597 } 598 599 int 600 dwmmc_card_detect(sdmmc_chipset_handle_t sch) 601 { 602 struct dwmmc_softc *sc = sch; 603 uint32_t cdetect; 604 605 /* XXX treat broken-cd as non-removable */ 606 if (OF_getproplen(sc->sc_node, "non-removable") == 0 || 607 OF_getproplen(sc->sc_node, "broken-cd") == 0) 608 return 1; 609 610 if (sc->sc_gpio[0]) { 611 int inverted, val; 612 613 val = gpio_controller_get_pin(sc->sc_gpio); 614 615 inverted = (OF_getproplen(sc->sc_node, "cd-inverted") == 0); 616 return inverted ? !val : val; 617 } 618 619 cdetect = HREAD4(sc, SDMMC_CDETECT); 620 return !(cdetect & SDMMC_CDETECT_CARD_DETECT_0); 621 } 622 623 int 624 dwmmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 625 { 626 struct dwmmc_softc *sc = sch; 627 uint32_t vdd = 0; 628 629 if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) 630 vdd = 3300000; 631 632 if (sc->sc_vdd == 0 && vdd > 0) 633 dwmmc_pwrseq_pre(sc->sc_pwrseq); 634 635 if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) 636 HSET4(sc, SDMMC_PWREN, 1); 637 else 638 HCLR4(sc, SDMMC_PWREN, 0); 639 640 if (sc->sc_vdd == 0 && vdd > 0) 641 dwmmc_pwrseq_post(sc->sc_pwrseq); 642 643 sc->sc_vdd = vdd; 644 return 0; 645 } 646 647 int 648 dwmmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing) 649 { 650 struct dwmmc_softc *sc = sch; 651 int div = 0, timeout; 652 uint32_t clkena; 653 654 HWRITE4(sc, SDMMC_CLKENA, 0); 655 HWRITE4(sc, SDMMC_CLKSRC, 0); 656 657 if (freq == 0) 658 return 0; 659 660 if (sc->sc_clkbase / 1000 > freq) { 661 for (div = 1; div < 256; div++) 662 if (sc->sc_clkbase / (2 * 1000 * div) <= freq) 663 break; 664 } 665 HWRITE4(sc, SDMMC_CLKDIV, div); 666 667 /* Update clock. */ 668 HWRITE4(sc, SDMMC_CMD, SDMMC_CMD_START_CMD | 669 SDMMC_CMD_WAIT_PRVDATA_COMPLETE | 670 SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY); 671 for (timeout = 1000; timeout > 0; timeout--) { 672 if ((HREAD4(sc, SDMMC_CMD) & SDMMC_CMD_START_CMD) == 0) 673 break; 674 } 675 if (timeout == 0) { 676 printf("%s: timeout\n", __func__); 677 return ETIMEDOUT; 678 } 679 680 /* Enable clock; low power mode only for memory mode. */ 681 clkena = SDMMC_CLKENA_CCLK_ENABLE; 682 if (!sc->sc_sdio_irq) 683 clkena |= SDMMC_CLKENA_CCLK_LOW_POWER; 684 HWRITE4(sc, SDMMC_CLKENA, clkena); 685 686 /* Update clock again. */ 687 HWRITE4(sc, SDMMC_CMD, SDMMC_CMD_START_CMD | 688 SDMMC_CMD_WAIT_PRVDATA_COMPLETE | 689 SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY); 690 for (timeout = 1000; timeout > 0; timeout--) { 691 if ((HREAD4(sc, SDMMC_CMD) & SDMMC_CMD_START_CMD) == 0) 692 break; 693 } 694 if (timeout == 0) { 695 printf("%s: timeout\n", __func__); 696 return ETIMEDOUT; 697 } 698 699 delay(1000000); 700 701 return 0; 702 } 703 704 int 705 dwmmc_bus_width(sdmmc_chipset_handle_t sch, int width) 706 { 707 struct dwmmc_softc *sc = sch; 708 709 switch (width) { 710 case 1: 711 HCLR4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT|SDMMC_CTYPE_4BIT); 712 break; 713 case 4: 714 HSET4(sc, SDMMC_CTYPE, SDMMC_CTYPE_4BIT); 715 HCLR4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT); 716 break; 717 case 8: 718 HSET4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT); 719 break; 720 default: 721 return EINVAL; 722 } 723 724 return 0; 725 } 726 727 void 728 dwmmc_pio_mode(struct dwmmc_softc *sc) 729 { 730 /* Disable DMA. */ 731 HCLR4(sc, SDMMC_CTRL, SDMMC_CTRL_USE_INTERNAL_DMAC | 732 SDMMC_CTRL_DMA_ENABLE); 733 734 /* Set FIFO thresholds. */ 735 HWRITE4(sc, SDMMC_FIFOTH, 2 << SDMMC_FIFOTH_MSIZE_SHIFT | 736 (sc->sc_fifo_depth / 2 - 1) << SDMMC_FIFOTH_RXWM_SHIFT | 737 (sc->sc_fifo_depth / 2) << SDMMC_FIFOTH_TXWM_SHIFT); 738 739 sc->sc_dmamode = 0; 740 sc->sc_blklen = 0; 741 } 742 743 void 744 dwmmc_dma_mode(struct dwmmc_softc *sc) 745 { 746 int timeout; 747 748 /* Reset DMA. */ 749 HSET4(sc, SDMMC_BMOD, SDMMC_BMOD_SWR); 750 for (timeout = 1000; timeout > 0; timeout--) { 751 if ((HREAD4(sc, SDMMC_BMOD) & SDMMC_BMOD_SWR) == 0) 752 break; 753 delay(100); 754 } 755 if (timeout == 0) 756 printf("%s: DMA reset failed\n", sc->sc_dev.dv_xname); 757 758 /* Enable DMA. */ 759 HSET4(sc, SDMMC_CTRL, SDMMC_CTRL_USE_INTERNAL_DMAC | 760 SDMMC_CTRL_DMA_ENABLE); 761 HSET4(sc, SDMMC_BMOD, SDMMC_BMOD_FB | SDMMC_BMOD_DE); 762 763 sc->sc_dmamode = 1; 764 } 765 766 void 767 dwmmc_dma_setup32(struct dwmmc_softc *sc, struct sdmmc_command *cmd) 768 { 769 struct dwmmc_desc32 *desc = (void *)sc->sc_desc; 770 uint32_t flags; 771 int seg; 772 773 flags = DES0_OWN | DES0_FS | DES0_CH | DES0_DIC; 774 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 775 bus_addr_t addr = cmd->c_dmamap->dm_segs[seg].ds_addr; 776 bus_size_t len = cmd->c_dmamap->dm_segs[seg].ds_len; 777 778 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 779 flags |= DES0_LD; 780 flags &= ~DES0_DIC; 781 } 782 783 KASSERT((desc[seg].des[0] & DES0_OWN) == 0); 784 desc[seg].des[0] = flags; 785 desc[seg].des[1] = DES1_BS1(len); 786 desc[seg].des[2] = addr; 787 flags &= ~DES0_FS; 788 } 789 } 790 791 void 792 dwmmc_dma_setup64(struct dwmmc_softc *sc, struct sdmmc_command *cmd) 793 { 794 struct dwmmc_desc64 *desc = (void *)sc->sc_desc; 795 uint32_t flags; 796 int seg; 797 798 flags = DES0_OWN | DES0_FS | DES0_CH | DES0_DIC; 799 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 800 bus_addr_t addr = cmd->c_dmamap->dm_segs[seg].ds_addr; 801 bus_size_t len = cmd->c_dmamap->dm_segs[seg].ds_len; 802 803 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 804 flags |= DES0_LD; 805 flags &= ~DES0_DIC; 806 } 807 808 KASSERT((desc[seg].des[0] & DES0_OWN) == 0); 809 desc[seg].des[0] = flags; 810 desc[seg].des[2] = DES2_BS1(len); 811 desc[seg].des[4] = addr; 812 desc[seg].des[5] = (uint64_t)addr >> 32; 813 flags &= ~DES0_FS; 814 } 815 } 816 817 void 818 dwmmc_dma_setup(struct dwmmc_softc *sc, struct sdmmc_command *cmd) 819 { 820 if (sc->sc_dma64) 821 dwmmc_dma_setup64(sc, cmd); 822 else 823 dwmmc_dma_setup32(sc, cmd); 824 825 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0, PAGE_SIZE, 826 BUS_DMASYNC_PREWRITE); 827 828 sc->sc_idsts = 0; 829 } 830 831 void 832 dwmmc_dma_reset(struct dwmmc_softc *sc, struct sdmmc_command *cmd) 833 { 834 int timeout; 835 836 /* Reset DMA unit. */ 837 HSET4(sc, SDMMC_BMOD, SDMMC_BMOD_SWR); 838 for (timeout = 1000; timeout > 0; timeout--) { 839 if ((HREAD4(sc, SDMMC_BMOD) & 840 SDMMC_BMOD_SWR) == 0) 841 break; 842 delay(100); 843 } 844 845 dwmmc_pio_mode(sc); 846 847 /* Clear descriptors that were in use, */ 848 memset(sc->sc_desc, 0, PAGE_SIZE); 849 dwmmc_init_descriptors(sc); 850 } 851 852 void 853 dwmmc_fifo_setup(struct dwmmc_softc *sc, int blklen) 854 { 855 int blkdepth = blklen / sc->sc_fifo_width; 856 int txwm = sc->sc_fifo_depth / 2; 857 int rxwm, msize = 0; 858 859 /* 860 * Bursting is only possible of the block size is a multiple of 861 * the FIFO width. 862 */ 863 if (blklen % sc->sc_fifo_width == 0) 864 msize = 7; 865 866 /* Magic to calculate the maximum burst size. */ 867 while (msize > 0) { 868 if (blkdepth % (2 << msize) == 0 && 869 (sc->sc_fifo_depth - txwm) % (2 << msize) == 0) 870 break; 871 msize--; 872 } 873 rxwm = (2 << msize) - 1; 874 875 HWRITE4(sc, SDMMC_FIFOTH, 876 msize << SDMMC_FIFOTH_MSIZE_SHIFT | 877 rxwm << SDMMC_FIFOTH_RXWM_SHIFT | 878 txwm << SDMMC_FIFOTH_TXWM_SHIFT); 879 880 sc->sc_blklen = blklen; 881 } 882 883 void 884 dwmmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 885 { 886 struct dwmmc_softc *sc = sch; 887 uint32_t cmdval = SDMMC_CMD_START_CMD | SDMMC_CMD_USE_HOLD_REG; 888 uint32_t status; 889 int error, timeout; 890 int s; 891 892 #if 0 893 printf("%s: cmd %d arg 0x%x flags 0x%x data %p datalen %d blklen %d\n", 894 sc->sc_dev.dv_xname, cmd->c_opcode, cmd->c_arg, cmd->c_flags, 895 cmd->c_data, cmd->c_datalen, cmd->c_blklen); 896 #endif 897 898 s = splbio(); 899 900 for (timeout = 10000; timeout > 0; timeout--) { 901 status = HREAD4(sc, SDMMC_STATUS); 902 if ((status & SDMMC_STATUS_DATA_BUSY) == 0) 903 break; 904 delay(100); 905 } 906 if (timeout == 0) { 907 printf("%s: timeout on data busy\n", sc->sc_dev.dv_xname); 908 goto done; 909 } 910 911 if (cmd->c_opcode == MMC_STOP_TRANSMISSION) 912 cmdval |= SDMMC_CMD_STOP_ABORT_CMD; 913 else if (cmd->c_opcode != MMC_SEND_STATUS) 914 cmdval |= SDMMC_CMD_WAIT_PRVDATA_COMPLETE; 915 916 if (cmd->c_opcode == 0) 917 cmdval |= SDMMC_CMD_SEND_INITIALIZATION; 918 if (cmd->c_flags & SCF_RSP_PRESENT) 919 cmdval |= SDMMC_CMD_RESPONSE_EXPECT; 920 if (cmd->c_flags & SCF_RSP_136) 921 cmdval |= SDMMC_CMD_RESPONSE_LENGTH; 922 if (cmd->c_flags & SCF_RSP_CRC) 923 cmdval |= SDMMC_CMD_CHECK_REPONSE_CRC; 924 925 if (cmd->c_datalen > 0) { 926 HWRITE4(sc, SDMMC_TMOUT, 0xffffffff); 927 HWRITE4(sc, SDMMC_BYTCNT, cmd->c_datalen); 928 HWRITE4(sc, SDMMC_BLKSIZ, cmd->c_blklen); 929 930 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 931 /* Set card read threshold to the size of a block. */ 932 HWRITE4(sc, SDMMC_CARDTHRCTL, 933 cmd->c_blklen << SDMMC_CARDTHRCTL_RDTHR_SHIFT | 934 SDMMC_CARDTHRCTL_RDTHREN); 935 } 936 937 cmdval |= SDMMC_CMD_DATA_EXPECTED; 938 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) 939 cmdval |= SDMMC_CMD_WR; 940 if (cmd->c_datalen > cmd->c_blklen && 941 cmd->c_opcode != SD_IO_RW_EXTENDED) 942 cmdval |= SDMMC_CMD_SEND_AUTO_STOP; 943 } 944 945 if (cmd->c_datalen > 0 && !cmd->c_dmamap) { 946 HSET4(sc, SDMMC_CTRL, SDMMC_CTRL_FIFO_RESET); 947 for (timeout = 1000; timeout > 0; timeout--) { 948 if ((HREAD4(sc, SDMMC_CTRL) & 949 SDMMC_CTRL_FIFO_RESET) == 0) 950 break; 951 delay(100); 952 } 953 if (timeout == 0) 954 printf("%s: FIFO reset failed\n", sc->sc_dev.dv_xname); 955 956 /* Disable DMA if we are switching back to PIO. */ 957 if (sc->sc_dmamode) 958 dwmmc_pio_mode(sc); 959 } 960 961 if (cmd->c_datalen > 0 && cmd->c_dmamap) { 962 dwmmc_dma_setup(sc, cmd); 963 HWRITE4(sc, SDMMC_PLDMND, 1); 964 965 /* Enable DMA if we did PIO before. */ 966 if (!sc->sc_dmamode) 967 dwmmc_dma_mode(sc); 968 969 /* Reconfigure FIFO thresholds if block size changed. */ 970 if (cmd->c_blklen != sc->sc_blklen) 971 dwmmc_fifo_setup(sc, cmd->c_blklen); 972 } 973 974 HWRITE4(sc, SDMMC_RINTSTS, ~SDMMC_RINTSTS_SDIO); 975 976 HWRITE4(sc, SDMMC_CMDARG, cmd->c_arg); 977 HWRITE4(sc, SDMMC_CMD, cmdval | cmd->c_opcode); 978 979 for (timeout = 1000; timeout > 0; timeout--) { 980 status = HREAD4(sc, SDMMC_RINTSTS); 981 if (status & SDMMC_RINTSTS_CD) 982 break; 983 delay(100); 984 } 985 if (timeout == 0 || status & SDMMC_RINTSTS_RTO) { 986 cmd->c_error = ETIMEDOUT; 987 dwmmc_dma_reset(sc, cmd); 988 goto done; 989 } 990 991 if (cmd->c_flags & SCF_RSP_PRESENT) { 992 if (cmd->c_flags & SCF_RSP_136) { 993 cmd->c_resp[0] = HREAD4(sc, SDMMC_RESP0); 994 cmd->c_resp[1] = HREAD4(sc, SDMMC_RESP1); 995 cmd->c_resp[2] = HREAD4(sc, SDMMC_RESP2); 996 cmd->c_resp[3] = HREAD4(sc, SDMMC_RESP3); 997 if (cmd->c_flags & SCF_RSP_CRC) { 998 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 999 (cmd->c_resp[1] << 24); 1000 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 1001 (cmd->c_resp[2] << 24); 1002 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 1003 (cmd->c_resp[3] << 24); 1004 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 1005 } 1006 } else { 1007 cmd->c_resp[0] = HREAD4(sc, SDMMC_RESP0); 1008 } 1009 } 1010 1011 if (cmd->c_datalen > 0 && !cmd->c_dmamap) 1012 dwmmc_transfer_data(sc, cmd); 1013 1014 if (cmd->c_datalen > 0 && cmd->c_dmamap) { 1015 while (sc->sc_idsts == 0) { 1016 error = tsleep_nsec(&sc->sc_idsts, PWAIT, "idsts", 1017 SEC_TO_NSEC(1)); 1018 if (error) { 1019 cmd->c_error = error; 1020 dwmmc_dma_reset(sc, cmd); 1021 goto done; 1022 } 1023 } 1024 1025 for (timeout = 10000; timeout > 0; timeout--) { 1026 status = HREAD4(sc, SDMMC_RINTSTS); 1027 if (status & SDMMC_RINTSTS_DTO) 1028 break; 1029 delay(100); 1030 } 1031 if (timeout == 0) { 1032 cmd->c_error = ETIMEDOUT; 1033 dwmmc_dma_reset(sc, cmd); 1034 goto done; 1035 } 1036 } 1037 1038 if (cmdval & SDMMC_CMD_SEND_AUTO_STOP) { 1039 for (timeout = 10000; timeout > 0; timeout--) { 1040 status = HREAD4(sc, SDMMC_RINTSTS); 1041 if (status & SDMMC_RINTSTS_ACD) 1042 break; 1043 delay(10); 1044 } 1045 if (timeout == 0) { 1046 cmd->c_error = ETIMEDOUT; 1047 dwmmc_dma_reset(sc, cmd); 1048 goto done; 1049 } 1050 } 1051 1052 done: 1053 cmd->c_flags |= SCF_ITSDONE; 1054 #if 0 1055 printf("%s: err %d rintsts 0x%x\n", sc->sc_dev.dv_xname, cmd->c_error, 1056 HREAD4(sc, SDMMC_RINTSTS)); 1057 #endif 1058 splx(s); 1059 } 1060 1061 void 1062 dwmmc_transfer_data(struct dwmmc_softc *sc, struct sdmmc_command *cmd) 1063 { 1064 int datalen = cmd->c_datalen; 1065 u_char *datap = cmd->c_data; 1066 uint32_t status; 1067 int count, timeout; 1068 int fifodr = SDMMC_RINTSTS_DTO | SDMMC_RINTSTS_HTO; 1069 1070 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1071 fifodr |= SDMMC_RINTSTS_RXDR; 1072 else 1073 fifodr |= SDMMC_RINTSTS_TXDR; 1074 1075 while (datalen > 0) { 1076 status = HREAD4(sc, SDMMC_RINTSTS); 1077 if (status & SDMMC_RINTSTS_DATA_ERR) { 1078 cmd->c_error = EIO; 1079 return; 1080 } 1081 if (status & SDMMC_RINTSTS_DRTO) { 1082 cmd->c_error = ETIMEDOUT; 1083 return; 1084 } 1085 1086 for (timeout = 10000; timeout > 0; timeout--) { 1087 status = HREAD4(sc, SDMMC_RINTSTS); 1088 if (status & fifodr) 1089 break; 1090 delay(100); 1091 } 1092 if (timeout == 0) { 1093 cmd->c_error = ETIMEDOUT; 1094 return; 1095 } 1096 1097 count = SDMMC_STATUS_FIFO_COUNT(HREAD4(sc, SDMMC_STATUS)); 1098 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) 1099 count = sc->sc_fifo_depth - count; 1100 1101 count = MIN(datalen, count * sc->sc_fifo_width); 1102 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1103 sc->sc_read_data(sc, datap, count); 1104 else 1105 sc->sc_write_data(sc, datap, count); 1106 1107 datap += count; 1108 datalen -= count; 1109 } 1110 1111 for (timeout = 10000; timeout > 0; timeout--) { 1112 status = HREAD4(sc, SDMMC_RINTSTS); 1113 if (status & SDMMC_RINTSTS_DTO) 1114 break; 1115 delay(100); 1116 } 1117 if (timeout == 0) 1118 cmd->c_error = ETIMEDOUT; 1119 } 1120 1121 void 1122 dwmmc_read_data32(struct dwmmc_softc *sc, u_char *datap, int datalen) 1123 { 1124 while (datalen > 3) { 1125 *(uint32_t *)datap = HREAD4(sc, SDMMC_FIFO_BASE); 1126 datap += 4; 1127 datalen -= 4; 1128 } 1129 if (datalen > 0) { 1130 uint32_t rv = HREAD4(sc, SDMMC_FIFO_BASE); 1131 do { 1132 *datap++ = rv & 0xff; 1133 rv = rv >> 8; 1134 } while (--datalen > 0); 1135 } 1136 HWRITE4(sc, SDMMC_RINTSTS, SDMMC_RINTSTS_RXDR); 1137 } 1138 1139 void 1140 dwmmc_write_data32(struct dwmmc_softc *sc, u_char *datap, int datalen) 1141 { 1142 while (datalen > 3) { 1143 HWRITE4(sc, SDMMC_FIFO_BASE, *((uint32_t *)datap)); 1144 datap += 4; 1145 datalen -= 4; 1146 } 1147 if (datalen > 0) { 1148 uint32_t rv = *datap++; 1149 if (datalen > 1) 1150 rv |= *datap++ << 8; 1151 if (datalen > 2) 1152 rv |= *datap++ << 16; 1153 HWRITE4(sc, SDMMC_FIFO_BASE, rv); 1154 } 1155 HWRITE4(sc, SDMMC_RINTSTS, SDMMC_RINTSTS_TXDR); 1156 } 1157 1158 void 1159 dwmmc_read_data64(struct dwmmc_softc *sc, u_char *datap, int datalen) 1160 { 1161 while (datalen > 7) { 1162 *(uint32_t *)datap = HREAD4(sc, SDMMC_FIFO_BASE); 1163 datap += 4; 1164 datalen -= 4; 1165 *(uint32_t *)datap = HREAD4(sc, SDMMC_FIFO_BASE + 4); 1166 datap += 4; 1167 datalen -= 4; 1168 } 1169 if (datalen > 0) { 1170 uint64_t rv = HREAD4(sc, SDMMC_FIFO_BASE) | 1171 ((uint64_t)HREAD4(sc, SDMMC_FIFO_BASE + 4) << 32); 1172 do { 1173 *datap++ = rv & 0xff; 1174 rv = rv >> 8; 1175 } while (--datalen > 0); 1176 } 1177 HWRITE4(sc, SDMMC_RINTSTS, SDMMC_RINTSTS_RXDR); 1178 } 1179 1180 void 1181 dwmmc_write_data64(struct dwmmc_softc *sc, u_char *datap, int datalen) 1182 { 1183 while (datalen > 7) { 1184 HWRITE4(sc, SDMMC_FIFO_BASE, *((uint32_t *)datap)); 1185 datap += 4; 1186 datalen -= 4; 1187 HWRITE4(sc, SDMMC_FIFO_BASE + 4, *((uint32_t *)datap)); 1188 datap += 4; 1189 datalen -= 4; 1190 } 1191 if (datalen > 0) { 1192 uint32_t rv = *datap++; 1193 if (datalen > 1) 1194 rv |= *datap++ << 8; 1195 if (datalen > 2) 1196 rv |= *datap++ << 16; 1197 if (datalen > 3) 1198 rv |= *datap++ << 24; 1199 HWRITE4(sc, SDMMC_FIFO_BASE, rv); 1200 if (datalen > 4) 1201 rv = *datap++; 1202 if (datalen > 5) 1203 rv |= *datap++ << 8; 1204 if (datalen > 6) 1205 rv |= *datap++ << 16; 1206 HWRITE4(sc, SDMMC_FIFO_BASE + 4, rv); 1207 } 1208 HWRITE4(sc, SDMMC_RINTSTS, SDMMC_RINTSTS_TXDR); 1209 } 1210 1211 void 1212 dwmmc_pwrseq_pre(uint32_t phandle) 1213 { 1214 uint32_t *gpios, *gpio; 1215 int node; 1216 int len; 1217 1218 node = OF_getnodebyphandle(phandle); 1219 if (node == 0) 1220 return; 1221 1222 if (!OF_is_compatible(node, "mmc-pwrseq-simple")) 1223 return; 1224 1225 pinctrl_byname(node, "default"); 1226 1227 clock_enable(node, "ext_clock"); 1228 1229 len = OF_getproplen(node, "reset-gpios"); 1230 if (len <= 0) 1231 return; 1232 1233 gpios = malloc(len, M_TEMP, M_WAITOK); 1234 OF_getpropintarray(node, "reset-gpios", gpios, len); 1235 1236 gpio = gpios; 1237 while (gpio && gpio < gpios + (len / sizeof(uint32_t))) { 1238 gpio_controller_config_pin(gpio, GPIO_CONFIG_OUTPUT); 1239 gpio_controller_set_pin(gpio, 1); 1240 gpio = gpio_controller_next_pin(gpio); 1241 } 1242 1243 free(gpios, M_TEMP, len); 1244 } 1245 1246 void 1247 dwmmc_pwrseq_post(uint32_t phandle) 1248 { 1249 uint32_t *gpios, *gpio; 1250 int node; 1251 int len; 1252 1253 node = OF_getnodebyphandle(phandle); 1254 if (node == 0) 1255 return; 1256 1257 if (!OF_is_compatible(node, "mmc-pwrseq-simple")) 1258 return; 1259 1260 len = OF_getproplen(node, "reset-gpios"); 1261 if (len <= 0) 1262 return; 1263 1264 gpios = malloc(len, M_TEMP, M_WAITOK); 1265 OF_getpropintarray(node, "reset-gpios", gpios, len); 1266 1267 gpio = gpios; 1268 while (gpio && gpio < gpios + (len / sizeof(uint32_t))) { 1269 gpio_controller_set_pin(gpio, 0); 1270 gpio = gpio_controller_next_pin(gpio); 1271 } 1272 1273 free(gpios, M_TEMP, len); 1274 } 1275