1 /* $OpenBSD: dwmmc.c,v 1.31 2024/12/19 18:02:47 patrick Exp $ */ 2 /* 3 * Copyright (c) 2017 Mark Kettenis 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <sys/param.h> 19 #include <sys/kernel.h> 20 #include <sys/malloc.h> 21 #include <sys/systm.h> 22 23 #include <machine/bus.h> 24 #include <machine/fdt.h> 25 #include <machine/intr.h> 26 27 #include <dev/ofw/openfirm.h> 28 #include <dev/ofw/ofw_clock.h> 29 #include <dev/ofw/ofw_gpio.h> 30 #include <dev/ofw/ofw_pinctrl.h> 31 #include <dev/ofw/ofw_regulator.h> 32 #include <dev/ofw/fdt.h> 33 34 #include <dev/sdmmc/sdmmcvar.h> 35 #include <dev/sdmmc/sdmmc_ioreg.h> 36 37 #define SDMMC_CTRL 0x0000 38 #define SDMMC_CTRL_USE_INTERNAL_DMAC (1 << 25) 39 #define SDMMC_CTRL_DMA_ENABLE (1 << 5) 40 #define SDMMC_CTRL_INT_ENABLE (1 << 4) 41 #define SDMMC_CTRL_DMA_RESET (1 << 2) 42 #define SDMMC_CTRL_FIFO_RESET (1 << 1) 43 #define SDMMC_CTRL_CONTROLLER_RESET (1 << 0) 44 #define SDMMC_CTRL_ALL_RESET (SDMMC_CTRL_CONTROLLER_RESET | \ 45 SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET) 46 #define SDMMC_PWREN 0x0004 47 #define SDMMC_CLKDIV 0x0008 48 #define SDMMC_CLKSRC 0x000c 49 #define SDMMC_CLKENA 0x0010 50 #define SDMMC_CLKENA_CCLK_LOW_POWER (1 << 16) 51 #define SDMMC_CLKENA_CCLK_ENABLE (1 << 0) 52 #define SDMMC_TMOUT 0x0014 53 #define SDMMC_CTYPE 0x0018 54 #define SDMMC_CTYPE_8BIT (1 << 16) 55 #define SDMMC_CTYPE_4BIT (1 << 0) 56 #define SDMMC_BLKSIZ 0x001c 57 #define SDMMC_BYTCNT 0x0020 58 #define SDMMC_INTMASK 0x0024 59 #define SDMMC_CMDARG 0x0028 60 #define SDMMC_CMD 0x002c 61 #define SDMMC_CMD_START_CMD (1U << 31) 62 #define SDMMC_CMD_USE_HOLD_REG (1 << 29) 63 #define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY (1 << 21) 64 #define SDMMC_CMD_SEND_INITIALIZATION (1 << 15) 65 #define SDMMC_CMD_STOP_ABORT_CMD (1 << 14) 66 #define SDMMC_CMD_WAIT_PRVDATA_COMPLETE (1 << 13) 67 #define SDMMC_CMD_SEND_AUTO_STOP (1 << 12) 68 #define SDMMC_CMD_WR (1 << 10) 69 #define SDMMC_CMD_DATA_EXPECTED (1 << 9) 70 #define SDMMC_CMD_CHECK_REPONSE_CRC (1 << 8) 71 #define SDMMC_CMD_RESPONSE_LENGTH (1 << 7) 72 #define SDMMC_CMD_RESPONSE_EXPECT (1 << 6) 73 #define SDMMC_RESP0 0x0030 74 #define SDMMC_RESP1 0x0034 75 #define SDMMC_RESP2 0x0038 76 #define SDMMC_RESP3 0x003c 77 #define SDMMC_MINTSTS 0x0040 78 #define SDMMC_RINTSTS 0x0044 79 #define SDMMC_RINTSTS_SDIO (1 << 24) 80 #define SDMMC_RINTSTS_EBE (1 << 15) 81 #define SDMMC_RINTSTS_ACD (1 << 14) 82 #define SDMMC_RINTSTS_SBE (1 << 13) 83 #define SDMMC_RINTSTS_HLE (1 << 12) 84 #define SDMMC_RINTSTS_FRUN (1 << 11) 85 #define SDMMC_RINTSTS_HTO (1 << 10) 86 #define SDMMC_RINTSTS_DRTO (1 << 9) 87 #define SDMMC_RINTSTS_RTO (1 << 8) 88 #define SDMMC_RINTSTS_DCRC (1 << 7) 89 #define SDMMC_RINTSTS_RCRC (1 << 6) 90 #define SDMMC_RINTSTS_RXDR (1 << 5) 91 #define SDMMC_RINTSTS_TXDR (1 << 4) 92 #define SDMMC_RINTSTS_DTO (1 << 3) 93 #define SDMMC_RINTSTS_CD (1 << 2) 94 #define SDMMC_RINTSTS_RE (1 << 1) 95 #define SDMMC_RINTSTS_CDT (1 << 0) 96 #define SDMMC_RINTSTS_DATA_ERR (SDMMC_RINTSTS_EBE | SDMMC_RINTSTS_SBE | \ 97 SDMMC_RINTSTS_HLE | SDMMC_RINTSTS_FRUN | SDMMC_RINTSTS_DCRC) 98 #define SDMMC_RINTSTS_DATA_TO (SDMMC_RINTSTS_HTO | SDMMC_RINTSTS_DRTO) 99 #define SDMMC_STATUS 0x0048 100 #define SDMMC_STATUS_FIFO_COUNT(x) (((x) >> 17) & 0x1fff) 101 #define SDMMC_STATUS_DATA_BUSY (1 << 9) 102 #define SDMMC_FIFOTH 0x004c 103 #define SDMMC_FIFOTH_MSIZE_SHIFT 28 104 #define SDMMC_FIFOTH_RXWM_SHIFT 16 105 #define SDMMC_FIFOTH_RXWM(x) (((x) >> 16) & 0xfff) 106 #define SDMMC_FIFOTH_TXWM_SHIFT 0 107 #define SDMMC_CDETECT 0x0050 108 #define SDMMC_CDETECT_CARD_DETECT_0 (1 << 0) 109 #define SDMMC_WRTPRT 0x0054 110 #define SDMMC_TCBCNT 0x005c 111 #define SDMMC_TBBCNT 0x0060 112 #define SDMMC_DEBNCE 0x0064 113 #define SDMMC_USRID 0x0068 114 #define SDMMC_VERID 0x006c 115 #define SDMMC_HCON 0x0070 116 #define SDMMC_HCON_DATA_WIDTH(x) (((x) >> 7) & 0x7) 117 #define SDMMC_HCON_DMA64 (1 << 27) 118 #define SDMMC_UHS_REG 0x0074 119 #define SDMMC_RST_n 0x0078 120 #define SDMMC_BMOD 0x0080 121 #define SDMMC_BMOD_DE (1 << 7) 122 #define SDMMC_BMOD_FB (1 << 1) 123 #define SDMMC_BMOD_SWR (1 << 0) 124 #define SDMMC_PLDMND 0x0084 125 #define SDMMC_DBADDR 0x0088 126 #define SDMMC_IDSTS32 0x008c 127 #define SDMMC_IDSTS_NIS (1 << 8) 128 #define SDMMC_IDSTS_RI (1 << 1) 129 #define SDMMC_IDSTS_TI (1 << 0) 130 #define SDMMC_IDINTEN32 0x0090 131 #define SDMMC_IDINTEN_NI (1 << 8) 132 #define SDMMC_IDINTEN_RI (1 << 1) 133 #define SDMMC_IDINTEN_TI (1 << 0) 134 #define SDMMC_DSCADDR 0x0094 135 #define SDMMC_BUFADDR 0x0098 136 #define SDMMC_CLKSEL 0x009c 137 #define SDMMC_CARDTHRCTL 0x0100 138 #define SDMMC_CARDTHRCTL_RDTHR_SHIFT 16 139 #define SDMMC_CARDTHRCTL_RDTHREN (1 << 0) 140 #define SDMMC_BACK_END_POWER 0x0104 141 #define SDMMC_EMMC_DDR_REG 0x0108 142 #define SDMMC_FIFO_BASE 0x0200 143 144 #define SDMMC_DBADDRL 0x0088 145 #define SDMMC_DBADDRH 0x008c 146 #define SDMMC_IDSTS64 0x0090 147 #define SDMMC_IDINTEN64 0x0094 148 #define SDMMC_DSCADDRL 0x0098 149 #define SDMMC_DSCADDRH 0x009c 150 #define SDMMC_BUFADDRL 0x00a0 151 #define SDMMC_BUFADDRH 0x00a4 152 153 #define SDMMC_IDSTS(sc) \ 154 ((sc)->sc_dma64 ? SDMMC_IDSTS64 : SDMMC_IDSTS32) 155 156 #define HREAD4(sc, reg) \ 157 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) 158 #define HWRITE4(sc, reg, val) \ 159 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 160 #define HSET4(sc, reg, bits) \ 161 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits)) 162 #define HCLR4(sc, reg, bits) \ 163 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits)) 164 165 struct dwmmc_desc32 { 166 uint32_t des[4]; 167 }; 168 169 struct dwmmc_desc64 { 170 uint32_t des[8]; 171 }; 172 173 #define DWMMC_NDESC (PAGE_SIZE / sizeof(struct dwmmc_desc64)) 174 #define DWMMC_MAXSEGSZ 0x1000 175 176 #define DES0_OWN (1U << 31) 177 #define DES0_CES (1 << 30) 178 #define DES0_ER (1 << 5) 179 #define DES0_CH (1 << 4) 180 #define DES0_FS (1 << 3) 181 #define DES0_LD (1 << 2) 182 #define DES0_DIC (1 << 1) 183 184 #define DES1_BS2(sz) (((sz) & 0x1fff) << 13) 185 #define DES1_BS1(sz) (((sz) & 0x1fff) << 0) 186 #define DES2_BS2(sz) DES1_BS2(sz) 187 #define DES2_BS1(sz) DES1_BS1(sz) 188 189 struct dwmmc_softc { 190 struct device sc_dev; 191 bus_space_tag_t sc_iot; 192 bus_space_handle_t sc_ioh; 193 bus_size_t sc_size; 194 bus_dma_tag_t sc_dmat; 195 bus_dmamap_t sc_dmap; 196 int sc_node; 197 198 void *sc_ih; 199 200 uint32_t sc_clkbase; 201 uint32_t sc_fifo_depth; 202 uint32_t sc_fifo_width; 203 void (*sc_read_data)(struct dwmmc_softc *, u_char *, int); 204 void (*sc_write_data)(struct dwmmc_softc *, u_char *, int); 205 int sc_blklen; 206 207 bus_dmamap_t sc_desc_map; 208 bus_dma_segment_t sc_desc_segs[1]; 209 caddr_t sc_desc; 210 int sc_dma64; 211 int sc_dmamode; 212 uint32_t sc_idsts; 213 214 uint32_t sc_gpio[4]; 215 int sc_sdio_irq; 216 uint32_t sc_vqmmc; 217 uint32_t sc_pwrseq; 218 uint32_t sc_vdd; 219 220 struct device *sc_sdmmc; 221 }; 222 223 int dwmmc_match(struct device *, void *, void *); 224 void dwmmc_attach(struct device *, struct device *, void *); 225 226 const struct cfattach dwmmc_ca = { 227 sizeof(struct dwmmc_softc), dwmmc_match, dwmmc_attach 228 }; 229 230 struct cfdriver dwmmc_cd = { 231 NULL, "dwmmc", DV_DULL 232 }; 233 234 int dwmmc_intr(void *); 235 236 int dwmmc_host_reset(sdmmc_chipset_handle_t); 237 uint32_t dwmmc_host_ocr(sdmmc_chipset_handle_t); 238 int dwmmc_host_maxblklen(sdmmc_chipset_handle_t); 239 int dwmmc_card_detect(sdmmc_chipset_handle_t); 240 int dwmmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 241 int dwmmc_bus_clock(sdmmc_chipset_handle_t, int, int); 242 int dwmmc_bus_width(sdmmc_chipset_handle_t, int); 243 void dwmmc_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *); 244 void dwmmc_card_intr_mask(sdmmc_chipset_handle_t, int); 245 void dwmmc_card_intr_ack(sdmmc_chipset_handle_t); 246 int dwmmc_signal_voltage(sdmmc_chipset_handle_t, int); 247 248 struct sdmmc_chip_functions dwmmc_chip_functions = { 249 .host_reset = dwmmc_host_reset, 250 .host_ocr = dwmmc_host_ocr, 251 .host_maxblklen = dwmmc_host_maxblklen, 252 .card_detect = dwmmc_card_detect, 253 .bus_power = dwmmc_bus_power, 254 .bus_clock = dwmmc_bus_clock, 255 .bus_width = dwmmc_bus_width, 256 .exec_command = dwmmc_exec_command, 257 .card_intr_mask = dwmmc_card_intr_mask, 258 .card_intr_ack = dwmmc_card_intr_ack, 259 .signal_voltage = dwmmc_signal_voltage, 260 }; 261 262 void dwmmc_pio_mode(struct dwmmc_softc *); 263 int dwmmc_alloc_descriptors(struct dwmmc_softc *); 264 void dwmmc_init_descriptors(struct dwmmc_softc *); 265 void dwmmc_transfer_data(struct dwmmc_softc *, struct sdmmc_command *); 266 void dwmmc_read_data32(struct dwmmc_softc *, u_char *, int); 267 void dwmmc_write_data32(struct dwmmc_softc *, u_char *, int); 268 void dwmmc_read_data64(struct dwmmc_softc *, u_char *, int); 269 void dwmmc_write_data64(struct dwmmc_softc *, u_char *, int); 270 void dwmmc_pwrseq_pre(uint32_t); 271 void dwmmc_pwrseq_post(uint32_t); 272 273 int 274 dwmmc_match(struct device *parent, void *match, void *aux) 275 { 276 struct fdt_attach_args *faa = aux; 277 278 return (OF_is_compatible(faa->fa_node, "hisilicon,hi3660-dw-mshc") || 279 OF_is_compatible(faa->fa_node, "hisilicon,hi3670-dw-mshc") || 280 OF_is_compatible(faa->fa_node, "rockchip,rk3288-dw-mshc") || 281 OF_is_compatible(faa->fa_node, "samsung,exynos5420-dw-mshc") || 282 OF_is_compatible(faa->fa_node, "snps,dw-mshc") || 283 OF_is_compatible(faa->fa_node, "starfive,jh7110-mmc")); 284 } 285 286 void 287 dwmmc_attach(struct device *parent, struct device *self, void *aux) 288 { 289 struct dwmmc_softc *sc = (struct dwmmc_softc *)self; 290 struct fdt_attach_args *faa = aux; 291 struct sdmmcbus_attach_args saa; 292 uint32_t freq = 0, div = 0; 293 uint32_t hcon, width; 294 uint32_t fifoth; 295 int error, timeout; 296 297 if (faa->fa_nreg < 1) { 298 printf(": no registers\n"); 299 return; 300 } 301 302 sc->sc_node = faa->fa_node; 303 sc->sc_iot = faa->fa_iot; 304 sc->sc_size = faa->fa_reg[0].size; 305 306 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, 307 faa->fa_reg[0].size, 0, &sc->sc_ioh)) { 308 printf(": can't map registers\n"); 309 return; 310 } 311 312 pinctrl_byname(faa->fa_node, "default"); 313 314 clock_enable_all(faa->fa_node); 315 reset_deassert_all(faa->fa_node); 316 317 /* 318 * Determine FIFO width from hardware configuration register. 319 * We only support 32-bit and 64-bit FIFOs. 320 */ 321 hcon = HREAD4(sc, SDMMC_HCON); 322 switch (SDMMC_HCON_DATA_WIDTH(hcon)) { 323 case 1: 324 sc->sc_fifo_width = 4; 325 sc->sc_read_data = dwmmc_read_data32; 326 sc->sc_write_data = dwmmc_write_data32; 327 break; 328 case 2: 329 sc->sc_fifo_width = 8; 330 sc->sc_read_data = dwmmc_read_data64; 331 sc->sc_write_data = dwmmc_write_data64; 332 break; 333 default: 334 printf(": unsupported FIFO width\n"); 335 return; 336 } 337 338 sc->sc_fifo_depth = OF_getpropint(faa->fa_node, "fifo-depth", 0); 339 if (sc->sc_fifo_depth == 0) { 340 fifoth = HREAD4(sc, SDMMC_FIFOTH); 341 sc->sc_fifo_depth = SDMMC_FIFOTH_RXWM(fifoth) + 1; 342 } 343 344 if (hcon & SDMMC_HCON_DMA64) 345 sc->sc_dma64 = 1; 346 347 /* Some SoCs pre-divide the clock. */ 348 if (OF_is_compatible(faa->fa_node, "rockchip,rk3288-dw-mshc")) 349 div = 1; 350 if (OF_is_compatible(faa->fa_node, "hisilicon,hi3660-dw-mshc") || 351 OF_is_compatible(faa->fa_node, "hisilicon,hi3670-dw-mshc")) 352 div = 7; 353 354 /* Force the base clock to 50MHz on Rockchip SoCs. */ 355 if (OF_is_compatible(faa->fa_node, "rockchip,rk3288-dw-mshc")) 356 freq = 50000000; 357 358 freq = OF_getpropint(faa->fa_node, "clock-frequency", freq); 359 if (freq > 0) 360 clock_set_frequency(faa->fa_node, "ciu", (div + 1) * freq); 361 362 sc->sc_clkbase = clock_get_frequency(faa->fa_node, "ciu"); 363 /* if ciu clock is missing the rate is clock-frequency */ 364 if (sc->sc_clkbase == 0) 365 sc->sc_clkbase = freq; 366 if (sc->sc_clkbase == 0) { 367 printf(": no clock base\n"); 368 return; 369 } 370 div = OF_getpropint(faa->fa_node, "samsung,dw-mshc-ciu-div", div); 371 sc->sc_clkbase /= (div + 1); 372 373 sc->sc_ih = fdt_intr_establish(faa->fa_node, IPL_BIO, 374 dwmmc_intr, sc, sc->sc_dev.dv_xname); 375 if (sc->sc_ih == NULL) { 376 printf(": can't establish interrupt\n"); 377 goto unmap; 378 } 379 380 OF_getpropintarray(faa->fa_node, "cd-gpios", sc->sc_gpio, 381 sizeof(sc->sc_gpio)); 382 if (sc->sc_gpio[0]) 383 gpio_controller_config_pin(sc->sc_gpio, GPIO_CONFIG_INPUT); 384 385 sc->sc_sdio_irq = (OF_getproplen(sc->sc_node, "cap-sdio-irq") == 0); 386 sc->sc_vqmmc = OF_getpropint(sc->sc_node, "vqmmc-supply", 0); 387 sc->sc_pwrseq = OF_getpropint(sc->sc_node, "mmc-pwrseq", 0); 388 389 printf(": %d MHz base clock\n", sc->sc_clkbase / 1000000); 390 391 HSET4(sc, SDMMC_CTRL, SDMMC_CTRL_ALL_RESET); 392 for (timeout = 5000; timeout > 0; timeout--) { 393 if ((HREAD4(sc, SDMMC_CTRL) & SDMMC_CTRL_ALL_RESET) == 0) 394 break; 395 delay(100); 396 } 397 if (timeout == 0) 398 printf("%s: reset failed\n", sc->sc_dev.dv_xname); 399 400 /* Enable interrupts, but mask them all. */ 401 HWRITE4(sc, SDMMC_INTMASK, 0); 402 HWRITE4(sc, SDMMC_RINTSTS, 0xffffffff); 403 HSET4(sc, SDMMC_CTRL, SDMMC_CTRL_INT_ENABLE); 404 405 dwmmc_bus_width(sc, 1); 406 407 /* Start out in non-DMA mode. */ 408 dwmmc_pio_mode(sc); 409 410 sc->sc_dmat = faa->fa_dmat; 411 dwmmc_alloc_descriptors(sc); 412 dwmmc_init_descriptors(sc); 413 414 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, DWMMC_NDESC, 415 DWMMC_MAXSEGSZ, 0, BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW, &sc->sc_dmap); 416 if (error) { 417 printf(": can't create DMA map\n"); 418 goto unmap; 419 } 420 421 memset(&saa, 0, sizeof(saa)); 422 saa.saa_busname = "sdmmc"; 423 saa.sct = &dwmmc_chip_functions; 424 saa.sch = sc; 425 saa.dmat = sc->sc_dmat; 426 saa.dmap = sc->sc_dmap; 427 saa.caps |= SMC_CAPS_DMA; 428 429 if (OF_getproplen(sc->sc_node, "cap-mmc-highspeed") == 0) 430 saa.caps |= SMC_CAPS_MMC_HIGHSPEED; 431 if (OF_getproplen(sc->sc_node, "cap-sd-highspeed") == 0) 432 saa.caps |= SMC_CAPS_SD_HIGHSPEED; 433 434 width = OF_getpropint(faa->fa_node, "bus-width", 1); 435 if (width >= 8) 436 saa.caps |= SMC_CAPS_8BIT_MODE; 437 if (width >= 4) 438 saa.caps |= SMC_CAPS_4BIT_MODE; 439 440 sc->sc_sdmmc = config_found(self, &saa, NULL); 441 return; 442 443 unmap: 444 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_size); 445 } 446 447 int 448 dwmmc_alloc_descriptors(struct dwmmc_softc *sc) 449 { 450 int error, rseg; 451 452 /* Allocate descriptor memory */ 453 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 454 PAGE_SIZE, sc->sc_desc_segs, 1, &rseg, 455 BUS_DMA_WAITOK | BUS_DMA_ZERO); 456 if (error) 457 return error; 458 error = bus_dmamem_map(sc->sc_dmat, sc->sc_desc_segs, rseg, 459 PAGE_SIZE, &sc->sc_desc, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 460 if (error) { 461 bus_dmamem_free(sc->sc_dmat, sc->sc_desc_segs, rseg); 462 return error; 463 } 464 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 465 0, BUS_DMA_WAITOK, &sc->sc_desc_map); 466 if (error) { 467 bus_dmamem_unmap(sc->sc_dmat, sc->sc_desc, PAGE_SIZE); 468 bus_dmamem_free(sc->sc_dmat, sc->sc_desc_segs, rseg); 469 return error; 470 } 471 error = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_map, 472 sc->sc_desc, PAGE_SIZE, NULL, BUS_DMA_WAITOK | BUS_DMA_WRITE); 473 if (error) { 474 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_map); 475 bus_dmamem_unmap(sc->sc_dmat, sc->sc_desc, PAGE_SIZE); 476 bus_dmamem_free(sc->sc_dmat, sc->sc_desc_segs, rseg); 477 return error; 478 } 479 480 return 0; 481 } 482 483 void 484 dwmmc_init_descriptors32(struct dwmmc_softc *sc) 485 { 486 struct dwmmc_desc32 *desc; 487 bus_addr_t addr; 488 int i; 489 490 desc = (void *)sc->sc_desc; 491 addr = sc->sc_desc_map->dm_segs[0].ds_addr; 492 for (i = 0; i < DWMMC_NDESC; i++) { 493 addr += sizeof(struct dwmmc_desc32); 494 desc[i].des[3] = addr; 495 } 496 desc[DWMMC_NDESC - 1].des[3] = sc->sc_desc_map->dm_segs[0].ds_addr; 497 desc[DWMMC_NDESC - 1].des[0] = DES0_ER; 498 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0, 499 PAGE_SIZE, BUS_DMASYNC_PREWRITE); 500 501 HWRITE4(sc, SDMMC_IDSTS32, 0xffffffff); 502 HWRITE4(sc, SDMMC_IDINTEN32, 503 SDMMC_IDINTEN_NI | SDMMC_IDINTEN_RI | SDMMC_IDINTEN_TI); 504 HWRITE4(sc, SDMMC_DBADDR, sc->sc_desc_map->dm_segs[0].ds_addr); 505 } 506 507 void 508 dwmmc_init_descriptors64(struct dwmmc_softc *sc) 509 { 510 struct dwmmc_desc64 *desc; 511 bus_addr_t addr; 512 int i; 513 514 desc = (void *)sc->sc_desc; 515 addr = sc->sc_desc_map->dm_segs[0].ds_addr; 516 for (i = 0; i < DWMMC_NDESC; i++) { 517 addr += sizeof(struct dwmmc_desc64); 518 desc[i].des[6] = addr; 519 desc[i].des[7] = (uint64_t)addr >> 32; 520 } 521 desc[DWMMC_NDESC - 1].des[6] = sc->sc_desc_map->dm_segs[0].ds_addr; 522 desc[DWMMC_NDESC - 1].des[7] = 523 (uint64_t)sc->sc_desc_map->dm_segs[0].ds_addr >> 32; 524 desc[DWMMC_NDESC - 1].des[0] = DES0_ER; 525 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0, 526 PAGE_SIZE, BUS_DMASYNC_PREWRITE); 527 528 HWRITE4(sc, SDMMC_IDSTS64, 0xffffffff); 529 HWRITE4(sc, SDMMC_IDINTEN64, 530 SDMMC_IDINTEN_NI | SDMMC_IDINTEN_RI | SDMMC_IDINTEN_TI); 531 HWRITE4(sc, SDMMC_DBADDRL, sc->sc_desc_map->dm_segs[0].ds_addr); 532 HWRITE4(sc, SDMMC_DBADDRH, 533 (uint64_t)sc->sc_desc_map->dm_segs[0].ds_addr >> 32); 534 } 535 536 void 537 dwmmc_init_descriptors(struct dwmmc_softc *sc) 538 { 539 if (sc->sc_dma64) 540 dwmmc_init_descriptors64(sc); 541 else 542 dwmmc_init_descriptors32(sc); 543 } 544 545 int 546 dwmmc_intr(void *arg) 547 { 548 struct dwmmc_softc *sc = arg; 549 uint32_t stat; 550 int handled = 0; 551 552 stat = HREAD4(sc, SDMMC_IDSTS(sc)); 553 if (stat) { 554 HWRITE4(sc, SDMMC_IDSTS(sc), stat); 555 sc->sc_idsts |= stat; 556 wakeup(&sc->sc_idsts); 557 handled = 1; 558 } 559 560 stat = HREAD4(sc, SDMMC_MINTSTS); 561 if (stat & SDMMC_RINTSTS_SDIO) { 562 HWRITE4(sc, SDMMC_RINTSTS, SDMMC_RINTSTS_SDIO); 563 HCLR4(sc, SDMMC_INTMASK, SDMMC_RINTSTS_SDIO); 564 sdmmc_card_intr(sc->sc_sdmmc); 565 handled = 1; 566 } 567 568 return handled; 569 } 570 571 void 572 dwmmc_card_intr_mask(sdmmc_chipset_handle_t sch, int enable) 573 { 574 struct dwmmc_softc *sc = sch; 575 576 if (enable) 577 HSET4(sc, SDMMC_INTMASK, SDMMC_RINTSTS_SDIO); 578 else 579 HCLR4(sc, SDMMC_INTMASK, SDMMC_RINTSTS_SDIO); 580 } 581 582 void 583 dwmmc_card_intr_ack(sdmmc_chipset_handle_t sch) 584 { 585 struct dwmmc_softc *sc = sch; 586 587 HSET4(sc, SDMMC_INTMASK, SDMMC_RINTSTS_SDIO); 588 } 589 590 int 591 dwmmc_host_reset(sdmmc_chipset_handle_t sch) 592 { 593 printf("%s\n", __func__); 594 return 0; 595 } 596 597 uint32_t 598 dwmmc_host_ocr(sdmmc_chipset_handle_t sch) 599 { 600 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V; 601 } 602 603 int 604 dwmmc_host_maxblklen(sdmmc_chipset_handle_t sch) 605 { 606 return 512; 607 } 608 609 int 610 dwmmc_card_detect(sdmmc_chipset_handle_t sch) 611 { 612 struct dwmmc_softc *sc = sch; 613 uint32_t cdetect; 614 615 /* XXX treat broken-cd as non-removable */ 616 if (OF_getproplen(sc->sc_node, "non-removable") == 0 || 617 OF_getproplen(sc->sc_node, "broken-cd") == 0) 618 return 1; 619 620 if (sc->sc_gpio[0]) { 621 int inverted, val; 622 623 val = gpio_controller_get_pin(sc->sc_gpio); 624 625 inverted = (OF_getproplen(sc->sc_node, "cd-inverted") == 0); 626 return inverted ? !val : val; 627 } 628 629 cdetect = HREAD4(sc, SDMMC_CDETECT); 630 return !(cdetect & SDMMC_CDETECT_CARD_DETECT_0); 631 } 632 633 int 634 dwmmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 635 { 636 struct dwmmc_softc *sc = sch; 637 uint32_t vdd = 0; 638 639 if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) 640 vdd = 3300000; 641 642 if (sc->sc_vdd == 0 && vdd > 0) 643 dwmmc_pwrseq_pre(sc->sc_pwrseq); 644 645 if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) 646 HSET4(sc, SDMMC_PWREN, 1); 647 else 648 HCLR4(sc, SDMMC_PWREN, 0); 649 650 if (sc->sc_vdd == 0 && vdd > 0) 651 dwmmc_pwrseq_post(sc->sc_pwrseq); 652 653 sc->sc_vdd = vdd; 654 return 0; 655 } 656 657 int 658 dwmmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing) 659 { 660 struct dwmmc_softc *sc = sch; 661 int div = 0, timeout; 662 uint32_t clkena; 663 664 HWRITE4(sc, SDMMC_CLKENA, 0); 665 HWRITE4(sc, SDMMC_CLKSRC, 0); 666 667 if (freq == 0) 668 return 0; 669 670 if (sc->sc_clkbase / 1000 > freq) { 671 for (div = 1; div < 256; div++) 672 if (sc->sc_clkbase / (2 * 1000 * div) <= freq) 673 break; 674 } 675 HWRITE4(sc, SDMMC_CLKDIV, div); 676 677 /* Update clock. */ 678 HWRITE4(sc, SDMMC_CMD, SDMMC_CMD_START_CMD | 679 SDMMC_CMD_WAIT_PRVDATA_COMPLETE | 680 SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY); 681 for (timeout = 1000; timeout > 0; timeout--) { 682 if ((HREAD4(sc, SDMMC_CMD) & SDMMC_CMD_START_CMD) == 0) 683 break; 684 } 685 if (timeout == 0) { 686 printf("%s: timeout\n", __func__); 687 return ETIMEDOUT; 688 } 689 690 /* Enable clock; low power mode only for memory mode. */ 691 clkena = SDMMC_CLKENA_CCLK_ENABLE; 692 if (!sc->sc_sdio_irq) 693 clkena |= SDMMC_CLKENA_CCLK_LOW_POWER; 694 HWRITE4(sc, SDMMC_CLKENA, clkena); 695 696 /* Update clock again. */ 697 HWRITE4(sc, SDMMC_CMD, SDMMC_CMD_START_CMD | 698 SDMMC_CMD_WAIT_PRVDATA_COMPLETE | 699 SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY); 700 for (timeout = 1000; timeout > 0; timeout--) { 701 if ((HREAD4(sc, SDMMC_CMD) & SDMMC_CMD_START_CMD) == 0) 702 break; 703 } 704 if (timeout == 0) { 705 printf("%s: timeout\n", __func__); 706 return ETIMEDOUT; 707 } 708 709 delay(1000000); 710 711 return 0; 712 } 713 714 int 715 dwmmc_bus_width(sdmmc_chipset_handle_t sch, int width) 716 { 717 struct dwmmc_softc *sc = sch; 718 719 switch (width) { 720 case 1: 721 HCLR4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT|SDMMC_CTYPE_4BIT); 722 break; 723 case 4: 724 HSET4(sc, SDMMC_CTYPE, SDMMC_CTYPE_4BIT); 725 HCLR4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT); 726 break; 727 case 8: 728 HSET4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT); 729 break; 730 default: 731 return EINVAL; 732 } 733 734 return 0; 735 } 736 737 void 738 dwmmc_pio_mode(struct dwmmc_softc *sc) 739 { 740 /* Disable DMA. */ 741 HCLR4(sc, SDMMC_CTRL, SDMMC_CTRL_USE_INTERNAL_DMAC | 742 SDMMC_CTRL_DMA_ENABLE); 743 744 /* Set FIFO thresholds. */ 745 HWRITE4(sc, SDMMC_FIFOTH, 2 << SDMMC_FIFOTH_MSIZE_SHIFT | 746 (sc->sc_fifo_depth / 2 - 1) << SDMMC_FIFOTH_RXWM_SHIFT | 747 (sc->sc_fifo_depth / 2) << SDMMC_FIFOTH_TXWM_SHIFT); 748 749 sc->sc_dmamode = 0; 750 sc->sc_blklen = 0; 751 } 752 753 void 754 dwmmc_dma_mode(struct dwmmc_softc *sc) 755 { 756 int timeout; 757 758 /* Reset DMA. */ 759 HSET4(sc, SDMMC_BMOD, SDMMC_BMOD_SWR); 760 for (timeout = 1000; timeout > 0; timeout--) { 761 if ((HREAD4(sc, SDMMC_BMOD) & SDMMC_BMOD_SWR) == 0) 762 break; 763 delay(100); 764 } 765 if (timeout == 0) 766 printf("%s: DMA reset failed\n", sc->sc_dev.dv_xname); 767 768 /* Enable DMA. */ 769 HSET4(sc, SDMMC_CTRL, SDMMC_CTRL_USE_INTERNAL_DMAC | 770 SDMMC_CTRL_DMA_ENABLE); 771 HSET4(sc, SDMMC_BMOD, SDMMC_BMOD_FB | SDMMC_BMOD_DE); 772 773 sc->sc_dmamode = 1; 774 } 775 776 void 777 dwmmc_dma_setup32(struct dwmmc_softc *sc, struct sdmmc_command *cmd) 778 { 779 struct dwmmc_desc32 *desc = (void *)sc->sc_desc; 780 uint32_t flags; 781 int seg; 782 783 flags = DES0_OWN | DES0_FS | DES0_CH | DES0_DIC; 784 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 785 bus_addr_t addr = cmd->c_dmamap->dm_segs[seg].ds_addr; 786 bus_size_t len = cmd->c_dmamap->dm_segs[seg].ds_len; 787 788 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 789 flags |= DES0_LD; 790 flags &= ~DES0_DIC; 791 } 792 793 KASSERT((desc[seg].des[0] & DES0_OWN) == 0); 794 desc[seg].des[0] = flags; 795 desc[seg].des[1] = DES1_BS1(len); 796 desc[seg].des[2] = addr; 797 flags &= ~DES0_FS; 798 } 799 } 800 801 void 802 dwmmc_dma_setup64(struct dwmmc_softc *sc, struct sdmmc_command *cmd) 803 { 804 struct dwmmc_desc64 *desc = (void *)sc->sc_desc; 805 uint32_t flags; 806 int seg; 807 808 flags = DES0_OWN | DES0_FS | DES0_CH | DES0_DIC; 809 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 810 bus_addr_t addr = cmd->c_dmamap->dm_segs[seg].ds_addr; 811 bus_size_t len = cmd->c_dmamap->dm_segs[seg].ds_len; 812 813 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 814 flags |= DES0_LD; 815 flags &= ~DES0_DIC; 816 } 817 818 KASSERT((desc[seg].des[0] & DES0_OWN) == 0); 819 desc[seg].des[0] = flags; 820 desc[seg].des[2] = DES2_BS1(len); 821 desc[seg].des[4] = addr; 822 desc[seg].des[5] = (uint64_t)addr >> 32; 823 flags &= ~DES0_FS; 824 } 825 } 826 827 void 828 dwmmc_dma_setup(struct dwmmc_softc *sc, struct sdmmc_command *cmd) 829 { 830 if (sc->sc_dma64) 831 dwmmc_dma_setup64(sc, cmd); 832 else 833 dwmmc_dma_setup32(sc, cmd); 834 835 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0, PAGE_SIZE, 836 BUS_DMASYNC_PREWRITE); 837 838 sc->sc_idsts = 0; 839 } 840 841 void 842 dwmmc_dma_reset(struct dwmmc_softc *sc, struct sdmmc_command *cmd) 843 { 844 int timeout; 845 846 /* Reset DMA unit. */ 847 HSET4(sc, SDMMC_BMOD, SDMMC_BMOD_SWR); 848 for (timeout = 1000; timeout > 0; timeout--) { 849 if ((HREAD4(sc, SDMMC_BMOD) & 850 SDMMC_BMOD_SWR) == 0) 851 break; 852 delay(100); 853 } 854 855 dwmmc_pio_mode(sc); 856 857 /* Clear descriptors that were in use, */ 858 memset(sc->sc_desc, 0, PAGE_SIZE); 859 dwmmc_init_descriptors(sc); 860 } 861 862 void 863 dwmmc_fifo_setup(struct dwmmc_softc *sc, int blklen) 864 { 865 int blkdepth = blklen / sc->sc_fifo_width; 866 int txwm = sc->sc_fifo_depth / 2; 867 int rxwm, msize = 0; 868 869 /* 870 * Bursting is only possible of the block size is a multiple of 871 * the FIFO width. 872 */ 873 if (blklen % sc->sc_fifo_width == 0) 874 msize = 7; 875 876 /* Magic to calculate the maximum burst size. */ 877 while (msize > 0) { 878 if (blkdepth % (2 << msize) == 0 && 879 (sc->sc_fifo_depth - txwm) % (2 << msize) == 0) 880 break; 881 msize--; 882 } 883 rxwm = (2 << msize) - 1; 884 885 HWRITE4(sc, SDMMC_FIFOTH, 886 msize << SDMMC_FIFOTH_MSIZE_SHIFT | 887 rxwm << SDMMC_FIFOTH_RXWM_SHIFT | 888 txwm << SDMMC_FIFOTH_TXWM_SHIFT); 889 890 sc->sc_blklen = blklen; 891 } 892 893 void 894 dwmmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 895 { 896 struct dwmmc_softc *sc = sch; 897 uint32_t cmdval = SDMMC_CMD_START_CMD | SDMMC_CMD_USE_HOLD_REG; 898 uint32_t status; 899 int error, timeout; 900 int s; 901 902 #if 0 903 printf("%s: cmd %d arg 0x%x flags 0x%x data %p datalen %d blklen %d\n", 904 sc->sc_dev.dv_xname, cmd->c_opcode, cmd->c_arg, cmd->c_flags, 905 cmd->c_data, cmd->c_datalen, cmd->c_blklen); 906 #endif 907 908 s = splbio(); 909 910 for (timeout = 10000; timeout > 0; timeout--) { 911 status = HREAD4(sc, SDMMC_STATUS); 912 if ((status & SDMMC_STATUS_DATA_BUSY) == 0) 913 break; 914 delay(100); 915 } 916 if (timeout == 0) { 917 printf("%s: timeout on data busy\n", sc->sc_dev.dv_xname); 918 goto done; 919 } 920 921 if (cmd->c_opcode == MMC_STOP_TRANSMISSION) 922 cmdval |= SDMMC_CMD_STOP_ABORT_CMD; 923 else if (cmd->c_opcode != MMC_SEND_STATUS) 924 cmdval |= SDMMC_CMD_WAIT_PRVDATA_COMPLETE; 925 926 if (cmd->c_opcode == 0) 927 cmdval |= SDMMC_CMD_SEND_INITIALIZATION; 928 if (cmd->c_flags & SCF_RSP_PRESENT) 929 cmdval |= SDMMC_CMD_RESPONSE_EXPECT; 930 if (cmd->c_flags & SCF_RSP_136) 931 cmdval |= SDMMC_CMD_RESPONSE_LENGTH; 932 if (cmd->c_flags & SCF_RSP_CRC) 933 cmdval |= SDMMC_CMD_CHECK_REPONSE_CRC; 934 935 if (cmd->c_datalen > 0) { 936 HWRITE4(sc, SDMMC_TMOUT, 0xffffffff); 937 HWRITE4(sc, SDMMC_BYTCNT, cmd->c_datalen); 938 HWRITE4(sc, SDMMC_BLKSIZ, cmd->c_blklen); 939 940 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 941 /* Set card read threshold to the size of a block. */ 942 HWRITE4(sc, SDMMC_CARDTHRCTL, 943 cmd->c_blklen << SDMMC_CARDTHRCTL_RDTHR_SHIFT | 944 SDMMC_CARDTHRCTL_RDTHREN); 945 } 946 947 cmdval |= SDMMC_CMD_DATA_EXPECTED; 948 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) 949 cmdval |= SDMMC_CMD_WR; 950 if (cmd->c_datalen > cmd->c_blklen && 951 cmd->c_opcode != SD_IO_RW_EXTENDED) 952 cmdval |= SDMMC_CMD_SEND_AUTO_STOP; 953 } 954 955 if (cmd->c_datalen > 0 && !cmd->c_dmamap) { 956 HSET4(sc, SDMMC_CTRL, SDMMC_CTRL_FIFO_RESET); 957 for (timeout = 1000; timeout > 0; timeout--) { 958 if ((HREAD4(sc, SDMMC_CTRL) & 959 SDMMC_CTRL_FIFO_RESET) == 0) 960 break; 961 delay(100); 962 } 963 if (timeout == 0) 964 printf("%s: FIFO reset failed\n", sc->sc_dev.dv_xname); 965 966 /* Disable DMA if we are switching back to PIO. */ 967 if (sc->sc_dmamode) 968 dwmmc_pio_mode(sc); 969 } 970 971 if (cmd->c_datalen > 0 && cmd->c_dmamap) { 972 dwmmc_dma_setup(sc, cmd); 973 HWRITE4(sc, SDMMC_PLDMND, 1); 974 975 /* Enable DMA if we did PIO before. */ 976 if (!sc->sc_dmamode) 977 dwmmc_dma_mode(sc); 978 979 /* Reconfigure FIFO thresholds if block size changed. */ 980 if (cmd->c_blklen != sc->sc_blklen) 981 dwmmc_fifo_setup(sc, cmd->c_blklen); 982 } 983 984 HWRITE4(sc, SDMMC_RINTSTS, ~SDMMC_RINTSTS_SDIO); 985 986 HWRITE4(sc, SDMMC_CMDARG, cmd->c_arg); 987 HWRITE4(sc, SDMMC_CMD, cmdval | cmd->c_opcode); 988 989 for (timeout = 1000; timeout > 0; timeout--) { 990 status = HREAD4(sc, SDMMC_RINTSTS); 991 if (status & SDMMC_RINTSTS_CD) 992 break; 993 delay(100); 994 } 995 if (timeout == 0 || status & SDMMC_RINTSTS_RTO) { 996 cmd->c_error = ETIMEDOUT; 997 dwmmc_dma_reset(sc, cmd); 998 goto done; 999 } 1000 1001 if (cmd->c_flags & SCF_RSP_PRESENT) { 1002 if (cmd->c_flags & SCF_RSP_136) { 1003 cmd->c_resp[0] = HREAD4(sc, SDMMC_RESP0); 1004 cmd->c_resp[1] = HREAD4(sc, SDMMC_RESP1); 1005 cmd->c_resp[2] = HREAD4(sc, SDMMC_RESP2); 1006 cmd->c_resp[3] = HREAD4(sc, SDMMC_RESP3); 1007 if (cmd->c_flags & SCF_RSP_CRC) { 1008 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 1009 (cmd->c_resp[1] << 24); 1010 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 1011 (cmd->c_resp[2] << 24); 1012 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 1013 (cmd->c_resp[3] << 24); 1014 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 1015 } 1016 } else { 1017 cmd->c_resp[0] = HREAD4(sc, SDMMC_RESP0); 1018 } 1019 } 1020 1021 if (cmd->c_datalen > 0 && !cmd->c_dmamap) 1022 dwmmc_transfer_data(sc, cmd); 1023 1024 if (cmd->c_datalen > 0 && cmd->c_dmamap) { 1025 while (sc->sc_idsts == 0) { 1026 error = tsleep_nsec(&sc->sc_idsts, PWAIT, "idsts", 1027 SEC_TO_NSEC(1)); 1028 if (error) { 1029 cmd->c_error = error; 1030 dwmmc_dma_reset(sc, cmd); 1031 goto done; 1032 } 1033 } 1034 1035 for (timeout = 10000; timeout > 0; timeout--) { 1036 status = HREAD4(sc, SDMMC_RINTSTS); 1037 if (status & SDMMC_RINTSTS_DTO) 1038 break; 1039 delay(100); 1040 } 1041 if (timeout == 0) { 1042 cmd->c_error = ETIMEDOUT; 1043 dwmmc_dma_reset(sc, cmd); 1044 goto done; 1045 } 1046 } 1047 1048 if (cmdval & SDMMC_CMD_SEND_AUTO_STOP) { 1049 for (timeout = 10000; timeout > 0; timeout--) { 1050 status = HREAD4(sc, SDMMC_RINTSTS); 1051 if (status & SDMMC_RINTSTS_ACD) 1052 break; 1053 delay(10); 1054 } 1055 if (timeout == 0) { 1056 cmd->c_error = ETIMEDOUT; 1057 dwmmc_dma_reset(sc, cmd); 1058 goto done; 1059 } 1060 } 1061 1062 done: 1063 cmd->c_flags |= SCF_ITSDONE; 1064 #if 0 1065 printf("%s: err %d rintsts 0x%x\n", sc->sc_dev.dv_xname, cmd->c_error, 1066 HREAD4(sc, SDMMC_RINTSTS)); 1067 #endif 1068 splx(s); 1069 } 1070 1071 void 1072 dwmmc_transfer_data(struct dwmmc_softc *sc, struct sdmmc_command *cmd) 1073 { 1074 int datalen = cmd->c_datalen; 1075 u_char *datap = cmd->c_data; 1076 uint32_t status; 1077 int count, timeout; 1078 int fifodr = SDMMC_RINTSTS_DTO | SDMMC_RINTSTS_HTO; 1079 1080 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1081 fifodr |= SDMMC_RINTSTS_RXDR; 1082 else 1083 fifodr |= SDMMC_RINTSTS_TXDR; 1084 1085 while (datalen > 0) { 1086 status = HREAD4(sc, SDMMC_RINTSTS); 1087 if (status & SDMMC_RINTSTS_DATA_ERR) { 1088 cmd->c_error = EIO; 1089 return; 1090 } 1091 if (status & SDMMC_RINTSTS_DRTO) { 1092 cmd->c_error = ETIMEDOUT; 1093 return; 1094 } 1095 1096 for (timeout = 10000; timeout > 0; timeout--) { 1097 status = HREAD4(sc, SDMMC_RINTSTS); 1098 if (status & fifodr) 1099 break; 1100 delay(100); 1101 } 1102 if (timeout == 0) { 1103 cmd->c_error = ETIMEDOUT; 1104 return; 1105 } 1106 1107 count = SDMMC_STATUS_FIFO_COUNT(HREAD4(sc, SDMMC_STATUS)); 1108 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) 1109 count = sc->sc_fifo_depth - count; 1110 1111 count = MIN(datalen, count * sc->sc_fifo_width); 1112 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1113 sc->sc_read_data(sc, datap, count); 1114 else 1115 sc->sc_write_data(sc, datap, count); 1116 1117 datap += count; 1118 datalen -= count; 1119 } 1120 1121 for (timeout = 10000; timeout > 0; timeout--) { 1122 status = HREAD4(sc, SDMMC_RINTSTS); 1123 if (status & SDMMC_RINTSTS_DTO) 1124 break; 1125 delay(100); 1126 } 1127 if (timeout == 0) 1128 cmd->c_error = ETIMEDOUT; 1129 } 1130 1131 void 1132 dwmmc_read_data32(struct dwmmc_softc *sc, u_char *datap, int datalen) 1133 { 1134 while (datalen > 3) { 1135 *(uint32_t *)datap = HREAD4(sc, SDMMC_FIFO_BASE); 1136 datap += 4; 1137 datalen -= 4; 1138 } 1139 if (datalen > 0) { 1140 uint32_t rv = HREAD4(sc, SDMMC_FIFO_BASE); 1141 do { 1142 *datap++ = rv & 0xff; 1143 rv = rv >> 8; 1144 } while (--datalen > 0); 1145 } 1146 HWRITE4(sc, SDMMC_RINTSTS, SDMMC_RINTSTS_RXDR); 1147 } 1148 1149 void 1150 dwmmc_write_data32(struct dwmmc_softc *sc, u_char *datap, int datalen) 1151 { 1152 while (datalen > 3) { 1153 HWRITE4(sc, SDMMC_FIFO_BASE, *((uint32_t *)datap)); 1154 datap += 4; 1155 datalen -= 4; 1156 } 1157 if (datalen > 0) { 1158 uint32_t rv = *datap++; 1159 if (datalen > 1) 1160 rv |= *datap++ << 8; 1161 if (datalen > 2) 1162 rv |= *datap++ << 16; 1163 HWRITE4(sc, SDMMC_FIFO_BASE, rv); 1164 } 1165 HWRITE4(sc, SDMMC_RINTSTS, SDMMC_RINTSTS_TXDR); 1166 } 1167 1168 void 1169 dwmmc_read_data64(struct dwmmc_softc *sc, u_char *datap, int datalen) 1170 { 1171 while (datalen > 7) { 1172 *(uint32_t *)datap = HREAD4(sc, SDMMC_FIFO_BASE); 1173 datap += 4; 1174 datalen -= 4; 1175 *(uint32_t *)datap = HREAD4(sc, SDMMC_FIFO_BASE + 4); 1176 datap += 4; 1177 datalen -= 4; 1178 } 1179 if (datalen > 0) { 1180 uint64_t rv = HREAD4(sc, SDMMC_FIFO_BASE) | 1181 ((uint64_t)HREAD4(sc, SDMMC_FIFO_BASE + 4) << 32); 1182 do { 1183 *datap++ = rv & 0xff; 1184 rv = rv >> 8; 1185 } while (--datalen > 0); 1186 } 1187 HWRITE4(sc, SDMMC_RINTSTS, SDMMC_RINTSTS_RXDR); 1188 } 1189 1190 void 1191 dwmmc_write_data64(struct dwmmc_softc *sc, u_char *datap, int datalen) 1192 { 1193 while (datalen > 7) { 1194 HWRITE4(sc, SDMMC_FIFO_BASE, *((uint32_t *)datap)); 1195 datap += 4; 1196 datalen -= 4; 1197 HWRITE4(sc, SDMMC_FIFO_BASE + 4, *((uint32_t *)datap)); 1198 datap += 4; 1199 datalen -= 4; 1200 } 1201 if (datalen > 0) { 1202 uint32_t rv = *datap++; 1203 if (datalen > 1) 1204 rv |= *datap++ << 8; 1205 if (datalen > 2) 1206 rv |= *datap++ << 16; 1207 if (datalen > 3) 1208 rv |= *datap++ << 24; 1209 HWRITE4(sc, SDMMC_FIFO_BASE, rv); 1210 if (datalen > 4) 1211 rv = *datap++; 1212 if (datalen > 5) 1213 rv |= *datap++ << 8; 1214 if (datalen > 6) 1215 rv |= *datap++ << 16; 1216 HWRITE4(sc, SDMMC_FIFO_BASE + 4, rv); 1217 } 1218 HWRITE4(sc, SDMMC_RINTSTS, SDMMC_RINTSTS_TXDR); 1219 } 1220 1221 void 1222 dwmmc_pwrseq_pre(uint32_t phandle) 1223 { 1224 uint32_t *gpios, *gpio; 1225 int node; 1226 int len; 1227 1228 node = OF_getnodebyphandle(phandle); 1229 if (node == 0) 1230 return; 1231 1232 if (!OF_is_compatible(node, "mmc-pwrseq-simple")) 1233 return; 1234 1235 pinctrl_byname(node, "default"); 1236 1237 clock_enable(node, "ext_clock"); 1238 1239 len = OF_getproplen(node, "reset-gpios"); 1240 if (len <= 0) 1241 return; 1242 1243 gpios = malloc(len, M_TEMP, M_WAITOK); 1244 OF_getpropintarray(node, "reset-gpios", gpios, len); 1245 1246 gpio = gpios; 1247 while (gpio && gpio < gpios + (len / sizeof(uint32_t))) { 1248 gpio_controller_config_pin(gpio, GPIO_CONFIG_OUTPUT); 1249 gpio_controller_set_pin(gpio, 1); 1250 gpio = gpio_controller_next_pin(gpio); 1251 } 1252 1253 free(gpios, M_TEMP, len); 1254 } 1255 1256 void 1257 dwmmc_pwrseq_post(uint32_t phandle) 1258 { 1259 uint32_t *gpios, *gpio; 1260 int post_delay; 1261 int node; 1262 int len; 1263 1264 node = OF_getnodebyphandle(phandle); 1265 if (node == 0) 1266 return; 1267 1268 if (!OF_is_compatible(node, "mmc-pwrseq-simple")) 1269 return; 1270 1271 len = OF_getproplen(node, "reset-gpios"); 1272 if (len <= 0) 1273 return; 1274 1275 gpios = malloc(len, M_TEMP, M_WAITOK); 1276 OF_getpropintarray(node, "reset-gpios", gpios, len); 1277 1278 gpio = gpios; 1279 while (gpio && gpio < gpios + (len / sizeof(uint32_t))) { 1280 gpio_controller_set_pin(gpio, 0); 1281 gpio = gpio_controller_next_pin(gpio); 1282 } 1283 1284 post_delay = OF_getpropint(node, "post-power-on-delay-ms", 0); 1285 if (post_delay) 1286 delay(post_delay * 1000); 1287 1288 free(gpios, M_TEMP, len); 1289 } 1290 1291 int 1292 dwmmc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 1293 { 1294 struct dwmmc_softc *sc = sch; 1295 uint32_t vccq; 1296 1297 if (sc->sc_vqmmc == 0) 1298 return ENODEV; 1299 1300 switch (signal_voltage) { 1301 case SDMMC_SIGNAL_VOLTAGE_180: 1302 vccq = 1800000; 1303 break; 1304 case SDMMC_SIGNAL_VOLTAGE_330: 1305 vccq = 3300000; 1306 break; 1307 default: 1308 return EINVAL; 1309 } 1310 1311 if (regulator_get_voltage(sc->sc_vqmmc) == vccq) 1312 return 0; 1313 1314 return regulator_set_voltage(sc->sc_vqmmc, vccq); 1315 } 1316