1 /* $OpenBSD: cache.h,v 1.7 2024/03/29 21:11:32 miod Exp $ */ 2 /* $NetBSD: cache.h,v 1.3 2000/08/01 00:28:02 eeh Exp $ */ 3 4 /* 5 * Copyright (c) 1996 6 * The President and Fellows of Harvard College. All rights reserved. 7 * Copyright (c) 1992, 1993 8 * The Regents of the University of California. All rights reserved. 9 * 10 * This software was developed by the Computer Systems Engineering group 11 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 12 * contributed to Berkeley. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. All advertising materials mentioning features or use of this software 23 * must display the following acknowledgement: 24 * This product includes software developed by Aaron Brown and 25 * Harvard University. 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)cache.h 8.1 (Berkeley) 6/11/93 45 */ 46 47 /* 48 * The spitfire has a 16K two-way set associative level-1 I$ and a separate 49 * 16K level-1 D$. The I$ can be invalidated using the FLUSH instructions, 50 * so we don't really need to worry about it much. The D$ is 16K write-through 51 * direct mapped virtually addressed cache with two 16-byte sub-blocks per line. 52 * The E$ is a 512KB-4MB direct mapped physically indexed physically tagged 53 * cache. 54 * Since the level-1 caches are write-through, they don't need flushing and can 55 * be invalidated directly. 56 * 57 * The spitfire sees virtual addresses as: 58 * 59 * struct cache_va { 60 * u_int64_t :22, (unused; we only have 40-bit addresses) 61 * cva_tag:28, (tag ID) 62 * cva_line:9, (cache line number) 63 * cva_byte:5; (byte within line) 64 * }; 65 * 66 * Since there is one bit of overlap between the page offset and the line index, 67 * all we need to do is make sure that bit 14 of the va remains constant and we 68 * have no aliasing problems. 69 * 70 * Let me try again. Page size is 8K, cache size is 16K so if (va1&0x3fff != 71 * va2&0x3fff) we have a problem. Bit 14 *must* be the same for all mappings 72 * of a page to be cacheable in the D$. (The I$ is 16K 2-way associative--each 73 * bank is 8K. No conflict there.) 74 */ 75 76 /* 77 * Routines for dealing with the cache. 78 */ 79 80 /* The following are for D$ flushes and are in locore.s */ 81 #define dcache_flush_page(pa) cacheinfo.c_dcache_flush_page(pa) 82 void us_dcache_flush_page(paddr_t); /* flush page from D$ */ 83 void us3_dcache_flush_page(paddr_t); /* flush page from D$ */ 84 void no_dcache_flush_page(paddr_t); 85 86 /* The following flush a range from the D$ and I$ but not E$. */ 87 void cache_flush_virt(vaddr_t, vsize_t); 88 89 /* 90 * Cache control information. 91 */ 92 struct cacheinfo { 93 void (*c_dcache_flush_page)(paddr_t); 94 95 int ic_totalsize; /* instruction cache */ 96 int ic_linesize; 97 int dc_totalsize; /* data cache */ 98 int dc_linesize; 99 int ec_totalsize; /* external cache info */ 100 int ec_linesize; 101 }; 102 extern struct cacheinfo cacheinfo; 103