1 /* $OpenBSD: softintr.c,v 1.22 2020/10/07 12:13:23 mpi Exp $ */
2 /* $NetBSD: softintr.c,v 1.2 2003/07/15 00:24:39 lukem Exp $ */
3
4 /*
5 * Copyright (c) 2001 Wasabi Systems, Inc.
6 * All rights reserved.
7 *
8 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed for the NetBSD Project by
21 * Wasabi Systems, Inc.
22 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
23 * or promote products derived from this software without specific prior
24 * written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/mutex.h>
42 #include <sys/malloc.h>
43 #include <sys/atomic.h>
44
45 #include <uvm/uvm_extern.h>
46
47 #include <machine/intr.h>
48 #ifdef MULTIPROCESSOR
49 #include <mips64/mips_cpu.h>
50 #endif
51
52 struct soft_intrq soft_intrq[SI_NQUEUES];
53
54 /*
55 * Initialize the software interrupt system.
56 */
57 void
softintr_init(void)58 softintr_init(void)
59 {
60 struct soft_intrq *siq;
61 int i;
62
63 for (i = 0; i < SI_NQUEUES; i++) {
64 siq = &soft_intrq[i];
65 TAILQ_INIT(&siq->siq_list);
66 siq->siq_si = i;
67 mtx_init(&siq->siq_mtx, IPL_HIGH);
68 }
69 }
70
71 /*
72 * Process pending software interrupts on the specified queue.
73 *
74 * NOTE: We must already be at the correct interrupt priority level.
75 */
76 void
softintr_dispatch(int si)77 softintr_dispatch(int si)
78 {
79 struct soft_intrq *siq = &soft_intrq[si];
80 struct soft_intrhand *sih;
81
82 for (;;) {
83 mtx_enter(&siq->siq_mtx);
84 sih = TAILQ_FIRST(&siq->siq_list);
85 if (sih == NULL) {
86 mtx_leave(&siq->siq_mtx);
87 break;
88 }
89
90 TAILQ_REMOVE(&siq->siq_list, sih, sih_list);
91 sih->sih_pending = 0;
92
93 atomic_inc_int(&uvmexp.softs);
94
95 mtx_leave(&siq->siq_mtx);
96
97 (*sih->sih_func)(sih->sih_arg);
98 }
99 }
100
101 /*
102 * Register a software interrupt handler.
103 */
104 void *
softintr_establish(int ipl,void (* func)(void *),void * arg)105 softintr_establish(int ipl, void (*func)(void *), void *arg)
106 {
107 struct soft_intrhand *sih;
108 int si;
109
110 switch (ipl) {
111 case IPL_SOFTCLOCK:
112 si = SI_SOFTCLOCK;
113 break;
114 case IPL_SOFTNET:
115 si = SI_SOFTNET;
116 break;
117 case IPL_TTY: /* XXX until MI code is fixed */
118 case IPL_SOFTTTY:
119 si = SI_SOFTTTY;
120 break;
121 default:
122 printf("softintr_establish: unknown soft IPL %d\n", ipl);
123 return NULL;
124 }
125
126 sih = malloc(sizeof(*sih), M_DEVBUF, M_NOWAIT);
127 if (__predict_true(sih != NULL)) {
128 sih->sih_func = func;
129 sih->sih_arg = arg;
130 sih->sih_siq = &soft_intrq[si];
131 sih->sih_pending = 0;
132 }
133 return (sih);
134 }
135
136 /*
137 * Unregister a software interrupt handler.
138 */
139 void
softintr_disestablish(void * arg)140 softintr_disestablish(void *arg)
141 {
142 struct soft_intrhand *sih = arg;
143 struct soft_intrq *siq = sih->sih_siq;
144
145 mtx_enter(&siq->siq_mtx);
146 if (sih->sih_pending) {
147 TAILQ_REMOVE(&siq->siq_list, sih, sih_list);
148 sih->sih_pending = 0;
149 }
150 mtx_leave(&siq->siq_mtx);
151
152 free(sih, M_DEVBUF, sizeof *sih);
153 }
154
155 /*
156 * Schedule a software interrupt.
157 */
158 void
softintr_schedule(void * arg)159 softintr_schedule(void *arg)
160 {
161 struct cpu_info *ci = curcpu();
162 struct soft_intrhand *sih = (struct soft_intrhand *)arg;
163 struct soft_intrq *siq = sih->sih_siq;
164
165 mtx_enter(&siq->siq_mtx);
166 if (sih->sih_pending == 0) {
167 TAILQ_INSERT_TAIL(&siq->siq_list, sih, sih_list);
168 sih->sih_pending = 1;
169 atomic_setbits_int(&ci->ci_softpending, SINTMASK(siq->siq_si));
170 }
171 mtx_leave(&siq->siq_mtx);
172 }
173
174 void
dosoftint()175 dosoftint()
176 {
177 struct cpu_info *ci = curcpu();
178 int sir, q, mask;
179 #ifdef MULTIPROCESSOR
180 register_t sr;
181
182 /* Enable interrupts */
183 sr = getsr();
184 ENABLEIPI();
185 __mp_lock(&kernel_lock);
186 #endif
187
188 while ((sir = ci->ci_softpending) != 0) {
189 atomic_clearbits_int(&ci->ci_softpending, sir);
190
191 for (q = SI_NQUEUES - 1; q >= 0; q--) {
192 mask = SINTMASK(q);
193 if (sir & mask)
194 softintr_dispatch(q);
195 }
196 }
197
198 #ifdef MULTIPROCESSOR
199 __mp_unlock(&kernel_lock);
200 setsr(sr);
201 #endif
202 }
203