1 /* $OpenBSD: pciide_machdep.c,v 1.7 2009/01/04 10:37:40 jsg Exp $ */ 2 /* $NetBSD: pciide_machdep.c,v 1.2 1999/02/19 18:01:27 mycroft Exp $ */ 3 4 /*- 5 * Copyright (c) 2007 Juan Romero Pardines. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright (c) 1998 Christopher G. Demetriou. All rights reserved. 31 * 32 * Redistribution and use in source and binary forms, with or without 33 * modification, are permitted provided that the following conditions 34 * are met: 35 * 1. Redistributions of source code must retain the above copyright 36 * notice, this list of conditions and the following disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 3. All advertising materials mentioning features or use of this software 41 * must display the following acknowledgement: 42 * This product includes software developed by Christopher G. Demetriou 43 * for the NetBSD Project. 44 * 4. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 /* 60 * PCI IDE controller driver (i386 machine-dependent portion). 61 * 62 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 63 * sys/dev/pci/ppb.c, revision 1.16). 64 * 65 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" from the 66 * PCI SIG. 67 */ 68 69 #include <sys/param.h> 70 #include <sys/systm.h> 71 #include <sys/device.h> 72 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcivar.h> 75 #include <dev/pci/pciidereg.h> 76 #include <dev/pci/pciidevar.h> 77 78 #include <dev/isa/isavar.h> 79 80 #include <machine/cpufunc.h> 81 #include <i386/pci/pciide_gcsc_reg.h> 82 83 void gcsc_setup_channel(struct channel_softc *); 84 85 void * 86 pciide_machdep_compat_intr_establish(struct device *dev, 87 struct pci_attach_args *pa, int chan, int (*func)(void *), void *arg) 88 { 89 int irq; 90 void *cookie; 91 92 irq = PCIIDE_COMPAT_IRQ(chan); 93 cookie = isa_intr_establish(NULL, irq, IST_EDGE, IPL_BIO, func, arg, dev->dv_xname); 94 95 return (cookie); 96 } 97 98 void 99 pciide_machdep_compat_intr_disestablish(pci_chipset_tag_t pc, void *cookie) 100 { 101 isa_intr_disestablish(NULL, cookie); 102 } 103 104 void 105 gcsc_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 106 { 107 struct pciide_channel *cp; 108 pcireg_t interface; 109 bus_size_t cmdsize, ctlsize; 110 111 printf(": DMA"); 112 pciide_mapreg_dma(sc, pa); 113 114 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 115 WDC_CAPABILITY_MODE; 116 if (sc->sc_dma_ok) { 117 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 118 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 119 sc->sc_wdcdev.irqack = pciide_irqack; 120 } 121 122 sc->sc_wdcdev.PIO_cap = 4; 123 sc->sc_wdcdev.DMA_cap = 2; 124 sc->sc_wdcdev.UDMA_cap = 4; 125 sc->sc_wdcdev.set_modes = gcsc_setup_channel; 126 sc->sc_wdcdev.channels = sc->wdc_chanarray; 127 sc->sc_wdcdev.nchannels = 1; 128 129 interface = PCI_INTERFACE(pa->pa_class); 130 131 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 132 133 cp = &sc->pciide_channels[0]; 134 135 if (pciide_chansetup(sc, 0, interface) == 0) 136 return; 137 138 pciide_map_compat_intr(pa, cp, 0, interface); 139 if (cp->hw_ok == 0) 140 return; 141 142 pciide_mapchan(pa, cp, interface, 143 &cmdsize, &ctlsize, pciide_pci_intr); 144 if (cp->hw_ok == 0) { 145 pciide_unmap_compat_intr(pa, cp, 0, interface); 146 return; 147 } 148 149 gcsc_setup_channel(&cp->wdc_channel); 150 } 151 152 void 153 gcsc_setup_channel(struct channel_softc *chp) 154 { 155 struct pciide_channel *cp = (struct pciide_channel *)chp; 156 struct ata_drive_datas *drvp; 157 uint64_t reg = 0; 158 int drive, s; 159 160 pciide_channel_dma_setup(cp); 161 162 for (drive = 0; drive < 2; drive++) { 163 drvp = &chp->ch_drive[drive]; 164 if ((drvp->drive_flags & DRIVE) == 0) 165 continue; 166 167 reg = rdmsr(drive ? GCSC_ATAC_CH0D1_DMA : 168 GCSC_ATAC_CH0D0_DMA); 169 170 if (drvp->drive_flags & DRIVE_UDMA) { 171 s = splbio(); 172 drvp->drive_flags &= ~DRIVE_DMA; 173 splx(s); 174 /* Enable the Ultra DMA mode bit */ 175 reg |= GCSC_ATAC_DMA_SEL; 176 /* set the Ultra DMA mode */ 177 reg |= gcsc_udma_timings[drvp->UDMA_mode]; 178 179 wrmsr(drive ? GCSC_ATAC_CH0D1_DMA : 180 GCSC_ATAC_CH0D0_DMA, reg); 181 182 } else if (drvp->drive_flags & DRIVE_DMA) { 183 /* Enable the Multi-word DMA bit */ 184 reg &= ~GCSC_ATAC_DMA_SEL; 185 /* set the Multi-word DMA mode */ 186 reg |= gcsc_mdma_timings[drvp->DMA_mode]; 187 188 wrmsr(drive ? GCSC_ATAC_CH0D1_DMA : 189 GCSC_ATAC_CH0D0_DMA, reg); 190 } 191 192 /* Always use PIO Format 1. */ 193 wrmsr(drive ? GCSC_ATAC_CH0D1_DMA : 194 GCSC_ATAC_CH0D0_DMA, reg | GCSC_ATAC_PIO_FORMAT); 195 196 /* Set PIO mode */ 197 wrmsr(drive ? GCSC_ATAC_CH0D1_PIO : GCSC_ATAC_CH0D0_PIO, 198 gcsc_pio_timings[drvp->PIO_mode]); 199 } 200 201 pciide_print_modes(cp); 202 } 203