1 /* $OpenBSD: pciide_machdep.c,v 1.8 2009/10/05 20:37:45 deraadt Exp $ */
2 /* $NetBSD: pciide_machdep.c,v 1.2 1999/02/19 18:01:27 mycroft Exp $ */
3
4 /*-
5 * Copyright (c) 2007 Juan Romero Pardines.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 /*
30 * Copyright (c) 1998 Christopher G. Demetriou. All rights reserved.
31 *
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
34 * are met:
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
40 * 3. All advertising materials mentioning features or use of this software
41 * must display the following acknowledgement:
42 * This product includes software developed by Christopher G. Demetriou
43 * for the NetBSD Project.
44 * 4. The name of the author may not be used to endorse or promote products
45 * derived from this software without specific prior written permission
46 *
47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 */
58
59 /*
60 * PCI IDE controller driver (i386 machine-dependent portion).
61 *
62 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD
63 * sys/dev/pci/ppb.c, revision 1.16).
64 *
65 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" from the
66 * PCI SIG.
67 */
68
69 #include <sys/param.h>
70 #include <sys/systm.h>
71 #include <sys/device.h>
72
73 #include <dev/pci/pcireg.h>
74 #include <dev/pci/pcivar.h>
75 #include <dev/pci/pciidereg.h>
76 #include <dev/pci/pciidevar.h>
77
78 #include <dev/isa/isavar.h>
79
80 #include <machine/cpufunc.h>
81 #include <i386/pci/pciide_gcsc_reg.h>
82
83 void gcsc_setup_channel(struct channel_softc *);
84
85 void *
pciide_machdep_compat_intr_establish(struct device * dev,struct pci_attach_args * pa,int chan,int (* func)(void *),void * arg)86 pciide_machdep_compat_intr_establish(struct device *dev,
87 struct pci_attach_args *pa, int chan, int (*func)(void *), void *arg)
88 {
89 int irq;
90 void *cookie;
91
92 irq = PCIIDE_COMPAT_IRQ(chan);
93 cookie = isa_intr_establish(NULL, irq, IST_EDGE, IPL_BIO, func, arg,
94 dev->dv_xname);
95
96 return (cookie);
97 }
98
99 void
pciide_machdep_compat_intr_disestablish(pci_chipset_tag_t pc,void * cookie)100 pciide_machdep_compat_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
101 {
102 isa_intr_disestablish(NULL, cookie);
103 }
104
105 void
gcsc_chip_map(struct pciide_softc * sc,struct pci_attach_args * pa)106 gcsc_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
107 {
108 struct pciide_channel *cp;
109 pcireg_t interface;
110 bus_size_t cmdsize, ctlsize;
111
112 printf(": DMA");
113 pciide_mapreg_dma(sc, pa);
114
115 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
116 WDC_CAPABILITY_MODE;
117 if (sc->sc_dma_ok) {
118 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
119 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
120 sc->sc_wdcdev.irqack = pciide_irqack;
121 }
122
123 sc->sc_wdcdev.PIO_cap = 4;
124 sc->sc_wdcdev.DMA_cap = 2;
125 sc->sc_wdcdev.UDMA_cap = 4;
126 sc->sc_wdcdev.set_modes = gcsc_setup_channel;
127 sc->sc_wdcdev.channels = sc->wdc_chanarray;
128 sc->sc_wdcdev.nchannels = 1;
129
130 interface = PCI_INTERFACE(pa->pa_class);
131
132 pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
133
134 cp = &sc->pciide_channels[0];
135
136 if (pciide_chansetup(sc, 0, interface) == 0)
137 return;
138
139 pciide_map_compat_intr(pa, cp, 0, interface);
140 if (cp->hw_ok == 0)
141 return;
142
143 pciide_mapchan(pa, cp, interface,
144 &cmdsize, &ctlsize, pciide_pci_intr);
145 if (cp->hw_ok == 0) {
146 pciide_unmap_compat_intr(pa, cp, 0, interface);
147 return;
148 }
149
150 gcsc_setup_channel(&cp->wdc_channel);
151 }
152
153 void
gcsc_setup_channel(struct channel_softc * chp)154 gcsc_setup_channel(struct channel_softc *chp)
155 {
156 struct pciide_channel *cp = (struct pciide_channel *)chp;
157 struct ata_drive_datas *drvp;
158 uint64_t reg = 0;
159 int drive, s;
160
161 pciide_channel_dma_setup(cp);
162
163 for (drive = 0; drive < 2; drive++) {
164 drvp = &chp->ch_drive[drive];
165 if ((drvp->drive_flags & DRIVE) == 0)
166 continue;
167
168 reg = rdmsr(drive ? GCSC_ATAC_CH0D1_DMA :
169 GCSC_ATAC_CH0D0_DMA);
170
171 if (drvp->drive_flags & DRIVE_UDMA) {
172 s = splbio();
173 drvp->drive_flags &= ~DRIVE_DMA;
174 splx(s);
175 /* Enable the Ultra DMA mode bit */
176 reg |= GCSC_ATAC_DMA_SEL;
177 /* set the Ultra DMA mode */
178 reg |= gcsc_udma_timings[drvp->UDMA_mode];
179
180 wrmsr(drive ? GCSC_ATAC_CH0D1_DMA :
181 GCSC_ATAC_CH0D0_DMA, reg);
182
183 } else if (drvp->drive_flags & DRIVE_DMA) {
184 /* Enable the Multi-word DMA bit */
185 reg &= ~GCSC_ATAC_DMA_SEL;
186 /* set the Multi-word DMA mode */
187 reg |= gcsc_mdma_timings[drvp->DMA_mode];
188
189 wrmsr(drive ? GCSC_ATAC_CH0D1_DMA :
190 GCSC_ATAC_CH0D0_DMA, reg);
191 }
192
193 /* Always use PIO Format 1. */
194 wrmsr(drive ? GCSC_ATAC_CH0D1_DMA :
195 GCSC_ATAC_CH0D0_DMA, reg | GCSC_ATAC_PIO_FORMAT);
196
197 /* Set PIO mode */
198 wrmsr(drive ? GCSC_ATAC_CH0D1_PIO : GCSC_ATAC_CH0D0_PIO,
199 gcsc_pio_timings[drvp->PIO_mode]);
200 }
201
202 pciide_print_modes(cp);
203 }
204