1 /* $OpenBSD: k1x-pstate.c,v 1.14 2023/01/30 10:49:05 jsg Exp $ */
2 /*
3 * Copyright (c) 2011 Bryan Steele <brynet@gmail.com>
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25 /* AMD K10/K11 pstate driver */
26
27 #include <sys/param.h>
28 #include <sys/systm.h>
29 #include <sys/malloc.h>
30 #include <sys/sysctl.h>
31
32 #include <machine/cpufunc.h>
33 #include <machine/bus.h>
34
35 #include "acpicpu.h"
36
37 #if NACPICPU > 0
38 #include <dev/acpi/acpidev.h>
39 #endif
40
41 extern int setperf_prio;
42
43 #define MSR_K1X_LIMIT 0xc0010061
44 #define MSR_K1X_CONTROL 0xc0010062
45 #define MSR_K1X_STATUS 0xc0010063
46 #define MSR_K1X_CONFIG 0xc0010064
47
48 /* MSR_K1X_LIMIT */
49 #define K1X_PSTATE_MAX_VAL(x) (((x) >> 4) & 0x7)
50 #define K1X_PSTATE_LIMIT(x) (((x)) & 0x7)
51
52 /* MSR_K1X_CONFIG */
53 #define K1X_FID(x) ((x) & 0x3f)
54 #define K1X_DID(x) (((x) >> 6) & 0x07)
55
56 /* Maximum pstates */
57 #define K1X_MAX_STATES 16
58
59 struct k1x_state {
60 int freq;
61 u_int8_t fid;
62 };
63
64 struct k1x_cpu_state {
65 struct k1x_state state_table[K1X_MAX_STATES];
66 u_int n_states;
67 };
68
69 struct k1x_cpu_state *k1x_current_state;
70
71 void k1x_transition(struct k1x_cpu_state *, int);
72
73 #if NACPICPU > 0
74 void k1x_acpi_init(struct k1x_cpu_state *);
75 void k1x_acpi_states(struct k1x_cpu_state *, struct acpicpu_pss *, int);
76 #endif
77
78 void
k1x_setperf(int level)79 k1x_setperf(int level)
80 {
81 u_int i = 0;
82 struct k1x_cpu_state *cstate;
83
84 cstate = k1x_current_state;
85
86 i = ((level * cstate->n_states) + 1) / 101;
87 if (i >= cstate->n_states)
88 i = cstate->n_states - 1;
89
90 k1x_transition(cstate, i);
91 }
92
93 void
k1x_transition(struct k1x_cpu_state * cstate,int level)94 k1x_transition(struct k1x_cpu_state *cstate, int level)
95 {
96 u_int64_t msr;
97 int i, cfid, fid = cstate->state_table[level].fid;
98
99 wrmsr(MSR_K1X_CONTROL, fid);
100 for (i = 0; i < 100; i++) {
101 msr = rdmsr(MSR_K1X_STATUS);
102 cfid = K1X_FID(msr);
103 if (cfid == fid)
104 break;
105 DELAY(100);
106 }
107 if (cfid == fid) {
108 cpuspeed = cstate->state_table[level].freq;
109 #if 0
110 (void)printf("Target: %d Current: %d Pstate: %d\n",
111 cstate->state_table[level].freq,
112 cpuspeed, cfid);
113 #endif
114 }
115 }
116
117 #if NACPICPU > 0
118
119 void
k1x_acpi_states(struct k1x_cpu_state * cstate,struct acpicpu_pss * pss,int nstates)120 k1x_acpi_states(struct k1x_cpu_state *cstate, struct acpicpu_pss *pss,
121 int nstates)
122 {
123 struct k1x_state state;
124 int j, n;
125 u_int32_t ctrl;
126
127 for (n = 0; n < cstate->n_states; n++) {
128 ctrl = pss[n].pss_ctrl;
129 state.fid = K1X_FID(ctrl);
130 state.freq = pss[n].pss_core_freq;
131 j = n;
132 while (j > 0 && cstate->state_table[j - 1].freq > state.freq) {
133 memcpy(&cstate->state_table[j],
134 &cstate->state_table[j - 1],
135 sizeof(struct k1x_state));
136 --j;
137 }
138 memcpy(&cstate->state_table[j], &state,
139 sizeof(struct k1x_state));
140 }
141 }
142
143 void
k1x_acpi_init(struct k1x_cpu_state * cstate)144 k1x_acpi_init(struct k1x_cpu_state *cstate)
145 {
146 struct acpicpu_pss *pss;
147
148 cstate->n_states = acpicpu_fetch_pss(&pss);
149 if (cstate->n_states == 0)
150 return;
151
152 k1x_acpi_states(cstate, pss, cstate->n_states);
153
154 return;
155 }
156
157 #endif /* NACPICPU */
158
159 void
k1x_init(struct cpu_info * ci)160 k1x_init(struct cpu_info *ci)
161 {
162 struct k1x_cpu_state *cstate;
163 struct k1x_state *state;
164 u_int i;
165
166 if (setperf_prio > 1)
167 return;
168
169 cstate = malloc(sizeof(struct k1x_cpu_state), M_DEVBUF, M_NOWAIT);
170 if (!cstate)
171 return;
172
173 cstate->n_states = 0;
174
175 #if NACPICPU > 0
176 k1x_acpi_init(cstate);
177 #endif
178 if (cstate->n_states) {
179 printf("%s: %d MHz: speeds:",
180 ci->ci_dev->dv_xname, cpuspeed);
181 for (i = cstate->n_states; i > 0; i--) {
182 state = &cstate->state_table[i-1];
183 printf(" %d", state->freq);
184 }
185 printf(" MHz\n");
186 k1x_current_state = cstate;
187 cpu_setperf = k1x_setperf;
188 setperf_prio = 1;
189 return;
190 }
191 free(cstate, M_DEVBUF, sizeof(*cstate));
192 }
193