1 /* $OpenBSD: pci_550.c,v 1.23 2015/07/26 05:09:44 miod Exp $ */ 2 /* $NetBSD: pci_550.c,v 1.18 2000/06/29 08:58:48 mrg Exp $ */ 3 4 /*- 5 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center, and by Andrew Gallatin. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 36 * All rights reserved. 37 * 38 * Author: Chris G. Demetriou 39 * 40 * Permission to use, copy, modify and distribute this software and 41 * its documentation is hereby granted, provided that both the copyright 42 * notice and this permission notice appear in all copies of the 43 * software, derivative works or modified versions, and any portions 44 * thereof, and that both notices appear in supporting documentation. 45 * 46 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 47 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 48 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 49 * 50 * Carnegie Mellon requests users of this software to return to 51 * 52 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 53 * School of Computer Science 54 * Carnegie Mellon University 55 * Pittsburgh PA 15213-3890 56 * 57 * any improvements or extensions that they make and grant Carnegie the 58 * rights to redistribute these changes. 59 */ 60 61 #include <sys/types.h> 62 #include <sys/param.h> 63 #include <sys/time.h> 64 #include <sys/systm.h> 65 #include <sys/errno.h> 66 #include <sys/malloc.h> 67 #include <sys/device.h> 68 #include <sys/syslog.h> 69 70 #include <uvm/uvm_extern.h> 71 72 #include <machine/autoconf.h> 73 #include <machine/rpb.h> 74 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/ppbreg.h> 78 #include <dev/pci/pciidereg.h> 79 #include <dev/pci/pciidevar.h> 80 81 #include <alpha/pci/ciareg.h> 82 #include <alpha/pci/ciavar.h> 83 84 #include <alpha/pci/pci_550.h> 85 86 #include "sio.h" 87 #if NSIO 88 #include <alpha/pci/siovar.h> 89 #endif 90 91 int dec_550_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 92 const char *dec_550_intr_string(void *, pci_intr_handle_t); 93 int dec_550_intr_line(void *, pci_intr_handle_t); 94 void *dec_550_intr_establish(void *, pci_intr_handle_t, 95 int, int (*func)(void *), void *, const char *); 96 void dec_550_intr_disestablish(void *, void *); 97 98 void *dec_550_pciide_compat_intr_establish(void *, struct device *, 99 struct pci_attach_args *, int, int (*)(void *), void *); 100 void dec_550_pciide_compat_intr_disestablish(void *, void *); 101 102 #define DEC_550_PCI_IRQ_BEGIN 8 103 #define DEC_550_MAX_IRQ (64 - DEC_550_PCI_IRQ_BEGIN) 104 105 /* 106 * The Miata has a Pyxis, which seems to have problems with stray 107 * interrupts. Work around this by just ignoring strays. 108 */ 109 #define PCI_STRAY_MAX 0 110 111 /* 112 * Some Miata models, notably models with a Cypress PCI-ISA bridge, have 113 * a PCI device (the OHCI USB controller) with interrupts tied to ISA IRQ 114 * lines. This IRQ is encoded as: line = FLAG | isa_irq. Usually FLAG 115 * is 0xe0, however it can be 0xf0. We don't allow 0xf0 | irq15. 116 */ 117 #define DEC_550_LINE_IS_ISA(line) ((line) >= 0xe0 && (line) <= 0xfe) 118 #define DEC_550_LINE_ISA_IRQ(line) ((line) & 0x0f) 119 120 struct alpha_shared_intr *dec_550_pci_intr; 121 122 void dec_550_iointr(void *arg, unsigned long vec); 123 void dec_550_intr_enable(int irq); 124 void dec_550_intr_disable(int irq); 125 126 void 127 pci_550_pickintr(ccp) 128 struct cia_config *ccp; 129 { 130 bus_space_tag_t iot = &ccp->cc_iot; 131 pci_chipset_tag_t pc = &ccp->cc_pc; 132 #if 0 133 char *cp; 134 #endif 135 int i; 136 137 pc->pc_intr_v = ccp; 138 pc->pc_intr_map = dec_550_intr_map; 139 pc->pc_intr_string = dec_550_intr_string; 140 pc->pc_intr_line = dec_550_intr_line; 141 pc->pc_intr_establish = dec_550_intr_establish; 142 pc->pc_intr_disestablish = dec_550_intr_disestablish; 143 144 pc->pc_pciide_compat_intr_establish = 145 dec_550_pciide_compat_intr_establish; 146 pc->pc_pciide_compat_intr_disestablish = 147 dec_550_pciide_compat_intr_disestablish; 148 149 /* 150 * DEC 550's interrupts are enabled via the Pyxis interrupt 151 * mask register. Nothing to map. 152 */ 153 154 for (i = 0; i < DEC_550_MAX_IRQ; i++) 155 dec_550_intr_disable(i); 156 157 dec_550_pci_intr = alpha_shared_intr_alloc(DEC_550_MAX_IRQ); 158 for (i = 0; i < DEC_550_MAX_IRQ; i++) { 159 alpha_shared_intr_set_maxstrays(dec_550_pci_intr, i, 160 PCI_STRAY_MAX); 161 alpha_shared_intr_set_private(dec_550_pci_intr, i, ccp); 162 } 163 164 #if NSIO 165 sio_intr_setup(pc, iot); 166 #endif 167 } 168 169 int 170 dec_550_intr_map(pa, ihp) 171 struct pci_attach_args *pa; 172 pci_intr_handle_t *ihp; 173 { 174 int buspin, line = pa->pa_intrline; 175 176 /* 177 * There are two main variants of Miata: Miata 1 (Intel SIO) 178 * and Miata {1.5,2} (Cypress). 179 * 180 * The Miata 1 has a CMD PCI IDE wired to compatibility mode at 181 * device 4 of bus 0. This variant apparently also has the 182 * Pyxis DMA bug. 183 * 184 * On the Miata 1.5 and Miata 2, the Cypress PCI-ISA bridge lives 185 * on device 7 of bus 0. This device has PCI IDE wired to 186 * compatibility mode on functions 1 and 2. 187 * 188 * There will be no interrupt mapping for these devices, so just 189 * bail out now. 190 */ 191 if (pa->pa_bus == 0) { 192 if ((hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) { 193 /* Miata 1 */ 194 if (pa->pa_device == 7) 195 panic("dec_550_intr_map: SIO device"); 196 else if (pa->pa_device == 4) 197 return (1); 198 } else { 199 /* Miata 1.5 or Miata 2 */ 200 if (pa->pa_device == 7) { 201 if (pa->pa_function == 0) 202 panic("dec_550_intr_map: SIO device"); 203 if (pa->pa_function == 1 || 204 pa->pa_function == 2) 205 return (1); 206 } 207 } 208 } 209 210 /* 211 * The console places the interrupt mapping in the "line" value. 212 * We trust it whenever possible. 213 */ 214 if (line >= 0 && line < DEC_550_MAX_IRQ) { 215 *ihp = line; 216 return 0; 217 } 218 if (DEC_550_LINE_IS_ISA(line)) { 219 #if NSIO > 0 220 *ihp = line; 221 return 0; 222 #else 223 printf("dec_550_intr_map: ISA IRQ %d for %d/%d/%d\n", 224 DEC_550_LINE_ISA_IRQ(line), 225 pa->pa_bus, pa->pa_device, pa->pa_function); 226 return 1; 227 #endif 228 } 229 230 if (pa->pa_bridgetag) { 231 buspin = PPB_INTERRUPT_SWIZZLE(pa->pa_rawintrpin, 232 pa->pa_device); 233 if (pa->pa_bridgeih[buspin - 1] != 0) { 234 *ihp = pa->pa_bridgeih[buspin - 1]; 235 return 0; 236 } 237 } 238 239 return 1; 240 } 241 242 const char * 243 dec_550_intr_string(ccv, ih) 244 void *ccv; 245 pci_intr_handle_t ih; 246 { 247 #if 0 248 struct cia_config *ccp = ccv; 249 #endif 250 static char irqstr[16]; /* 12 + 2 + NULL + sanity */ 251 252 #if NSIO 253 if (DEC_550_LINE_IS_ISA(ih)) 254 return (sio_intr_string(NULL /*XXX*/, 255 DEC_550_LINE_ISA_IRQ(ih))); 256 #endif 257 258 if (ih >= DEC_550_MAX_IRQ) 259 panic("dec_550_intr_string: bogus 550 IRQ 0x%lx", ih); 260 snprintf(irqstr, sizeof irqstr, "dec 550 irq %ld", ih); 261 return (irqstr); 262 } 263 264 int 265 dec_550_intr_line(ccv, ih) 266 void *ccv; 267 pci_intr_handle_t ih; 268 { 269 #if NSIO 270 if (DEC_550_LINE_IS_ISA(ih)) 271 return (sio_intr_line(NULL /*XXX*/, DEC_550_LINE_ISA_IRQ(ih))); 272 #endif 273 274 return (ih); 275 } 276 277 void * 278 dec_550_intr_establish(ccv, ih, level, func, arg, name) 279 void *ccv, *arg; 280 pci_intr_handle_t ih; 281 int level; 282 int (*func)(void *); 283 const char *name; 284 { 285 #if 0 286 struct cia_config *ccp = ccv; 287 #endif 288 void *cookie; 289 290 #if NSIO 291 if (DEC_550_LINE_IS_ISA(ih)) 292 return (sio_intr_establish(NULL /*XXX*/, 293 DEC_550_LINE_ISA_IRQ(ih), IST_LEVEL, level, func, arg, 294 name)); 295 #endif 296 297 if (ih >= DEC_550_MAX_IRQ) 298 panic("dec_550_intr_establish: bogus dec 550 IRQ 0x%lx", ih); 299 300 cookie = alpha_shared_intr_establish(dec_550_pci_intr, ih, IST_LEVEL, 301 level, func, arg, name); 302 303 if (cookie != NULL && 304 alpha_shared_intr_firstactive(dec_550_pci_intr, ih)) { 305 scb_set(0x900 + SCB_IDXTOVEC(ih), dec_550_iointr, NULL); 306 dec_550_intr_enable(ih); 307 } 308 return (cookie); 309 } 310 311 void 312 dec_550_intr_disestablish(ccv, cookie) 313 void *ccv, *cookie; 314 { 315 struct cia_config *ccp = ccv; 316 struct alpha_shared_intrhand *ih = cookie; 317 unsigned int irq = ih->ih_num; 318 int s; 319 320 #if NSIO 321 /* 322 * We have to determine if this is an ISA IRQ or not! We do this 323 * by checking to see if the intrhand points back to an intrhead 324 * that points to our cia_config. If not, it's an ISA IRQ. Pretty 325 * disgusting, eh? 326 */ 327 if (ih->ih_intrhead->intr_private != ccp) { 328 sio_intr_disestablish(NULL /*XXX*/, cookie); 329 return; 330 } 331 #endif 332 333 s = splhigh(); 334 335 alpha_shared_intr_disestablish(dec_550_pci_intr, cookie); 336 if (alpha_shared_intr_isactive(dec_550_pci_intr, irq) == 0) { 337 dec_550_intr_disable(irq); 338 alpha_shared_intr_set_dfltsharetype(dec_550_pci_intr, irq, 339 IST_NONE); 340 scb_free(0x900 + SCB_IDXTOVEC(irq)); 341 } 342 343 splx(s); 344 } 345 346 void * 347 dec_550_pciide_compat_intr_establish(v, dev, pa, chan, func, arg) 348 void *v; 349 struct device *dev; 350 struct pci_attach_args *pa; 351 int chan; 352 int (*func)(void *); 353 void *arg; 354 { 355 pci_chipset_tag_t pc = pa->pa_pc; 356 void *cookie = NULL; 357 int bus, irq; 358 359 pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 360 361 /* 362 * If this isn't PCI bus #0, all bets are off. 363 */ 364 if (bus != 0) 365 return (NULL); 366 367 irq = PCIIDE_COMPAT_IRQ(chan); 368 #if NSIO 369 cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO, 370 func, arg, dev->dv_xname); 371 #endif 372 return (cookie); 373 } 374 375 void 376 dec_550_pciide_compat_intr_disestablish(v, cookie) 377 void *v; 378 void *cookie; 379 { 380 sio_intr_disestablish(NULL, cookie); 381 } 382 383 void 384 dec_550_iointr(arg, vec) 385 void *arg; 386 unsigned long vec; 387 { 388 int irq; 389 390 irq = SCB_VECTOIDX(vec - 0x900); 391 392 if (irq >= DEC_550_MAX_IRQ) 393 panic("550_iointr: vec 0x%lx out of range", vec); 394 395 if (!alpha_shared_intr_dispatch(dec_550_pci_intr, irq)) { 396 alpha_shared_intr_stray(dec_550_pci_intr, irq, 397 "dec 550 irq"); 398 if (ALPHA_SHARED_INTR_DISABLE(dec_550_pci_intr, irq)) 399 dec_550_intr_disable(irq); 400 } else 401 alpha_shared_intr_reset_strays(dec_550_pci_intr, irq); 402 } 403 404 void 405 dec_550_intr_enable(irq) 406 int irq; 407 { 408 409 cia_pyxis_intr_enable(irq + DEC_550_PCI_IRQ_BEGIN, 1); 410 } 411 412 void 413 dec_550_intr_disable(irq) 414 int irq; 415 { 416 417 cia_pyxis_intr_enable(irq + DEC_550_PCI_IRQ_BEGIN, 0); 418 } 419