1 /* $OpenBSD: pci_550.c,v 1.24 2017/09/08 05:36:51 deraadt Exp $ */
2 /* $NetBSD: pci_550.c,v 1.18 2000/06/29 08:58:48 mrg Exp $ */
3
4 /*-
5 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10 * NASA Ames Research Center, and by Andrew Gallatin.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 /*
35 * Copyright (c) 1995, 1996 Carnegie-Mellon University.
36 * All rights reserved.
37 *
38 * Author: Chris G. Demetriou
39 *
40 * Permission to use, copy, modify and distribute this software and
41 * its documentation is hereby granted, provided that both the copyright
42 * notice and this permission notice appear in all copies of the
43 * software, derivative works or modified versions, and any portions
44 * thereof, and that both notices appear in supporting documentation.
45 *
46 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
47 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
48 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
49 *
50 * Carnegie Mellon requests users of this software to return to
51 *
52 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
53 * School of Computer Science
54 * Carnegie Mellon University
55 * Pittsburgh PA 15213-3890
56 *
57 * any improvements or extensions that they make and grant Carnegie the
58 * rights to redistribute these changes.
59 */
60
61 #include <sys/param.h>
62 #include <sys/time.h>
63 #include <sys/systm.h>
64 #include <sys/errno.h>
65 #include <sys/malloc.h>
66 #include <sys/device.h>
67 #include <sys/syslog.h>
68
69 #include <uvm/uvm_extern.h>
70
71 #include <machine/autoconf.h>
72 #include <machine/rpb.h>
73
74 #include <dev/pci/pcireg.h>
75 #include <dev/pci/pcivar.h>
76 #include <dev/pci/ppbreg.h>
77 #include <dev/pci/pciidereg.h>
78 #include <dev/pci/pciidevar.h>
79
80 #include <alpha/pci/ciareg.h>
81 #include <alpha/pci/ciavar.h>
82
83 #include <alpha/pci/pci_550.h>
84
85 #include "sio.h"
86 #if NSIO
87 #include <alpha/pci/siovar.h>
88 #endif
89
90 int dec_550_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
91 const char *dec_550_intr_string(void *, pci_intr_handle_t);
92 int dec_550_intr_line(void *, pci_intr_handle_t);
93 void *dec_550_intr_establish(void *, pci_intr_handle_t,
94 int, int (*func)(void *), void *, const char *);
95 void dec_550_intr_disestablish(void *, void *);
96
97 void *dec_550_pciide_compat_intr_establish(void *, struct device *,
98 struct pci_attach_args *, int, int (*)(void *), void *);
99 void dec_550_pciide_compat_intr_disestablish(void *, void *);
100
101 #define DEC_550_PCI_IRQ_BEGIN 8
102 #define DEC_550_MAX_IRQ (64 - DEC_550_PCI_IRQ_BEGIN)
103
104 /*
105 * The Miata has a Pyxis, which seems to have problems with stray
106 * interrupts. Work around this by just ignoring strays.
107 */
108 #define PCI_STRAY_MAX 0
109
110 /*
111 * Some Miata models, notably models with a Cypress PCI-ISA bridge, have
112 * a PCI device (the OHCI USB controller) with interrupts tied to ISA IRQ
113 * lines. This IRQ is encoded as: line = FLAG | isa_irq. Usually FLAG
114 * is 0xe0, however it can be 0xf0. We don't allow 0xf0 | irq15.
115 */
116 #define DEC_550_LINE_IS_ISA(line) ((line) >= 0xe0 && (line) <= 0xfe)
117 #define DEC_550_LINE_ISA_IRQ(line) ((line) & 0x0f)
118
119 struct alpha_shared_intr *dec_550_pci_intr;
120
121 void dec_550_iointr(void *arg, unsigned long vec);
122 void dec_550_intr_enable(int irq);
123 void dec_550_intr_disable(int irq);
124
125 void
pci_550_pickintr(ccp)126 pci_550_pickintr(ccp)
127 struct cia_config *ccp;
128 {
129 bus_space_tag_t iot = &ccp->cc_iot;
130 pci_chipset_tag_t pc = &ccp->cc_pc;
131 #if 0
132 char *cp;
133 #endif
134 int i;
135
136 pc->pc_intr_v = ccp;
137 pc->pc_intr_map = dec_550_intr_map;
138 pc->pc_intr_string = dec_550_intr_string;
139 pc->pc_intr_line = dec_550_intr_line;
140 pc->pc_intr_establish = dec_550_intr_establish;
141 pc->pc_intr_disestablish = dec_550_intr_disestablish;
142
143 pc->pc_pciide_compat_intr_establish =
144 dec_550_pciide_compat_intr_establish;
145 pc->pc_pciide_compat_intr_disestablish =
146 dec_550_pciide_compat_intr_disestablish;
147
148 /*
149 * DEC 550's interrupts are enabled via the Pyxis interrupt
150 * mask register. Nothing to map.
151 */
152
153 for (i = 0; i < DEC_550_MAX_IRQ; i++)
154 dec_550_intr_disable(i);
155
156 dec_550_pci_intr = alpha_shared_intr_alloc(DEC_550_MAX_IRQ);
157 for (i = 0; i < DEC_550_MAX_IRQ; i++) {
158 alpha_shared_intr_set_maxstrays(dec_550_pci_intr, i,
159 PCI_STRAY_MAX);
160 alpha_shared_intr_set_private(dec_550_pci_intr, i, ccp);
161 }
162
163 #if NSIO
164 sio_intr_setup(pc, iot);
165 #endif
166 }
167
168 int
dec_550_intr_map(pa,ihp)169 dec_550_intr_map(pa, ihp)
170 struct pci_attach_args *pa;
171 pci_intr_handle_t *ihp;
172 {
173 int buspin, line = pa->pa_intrline;
174
175 /*
176 * There are two main variants of Miata: Miata 1 (Intel SIO)
177 * and Miata {1.5,2} (Cypress).
178 *
179 * The Miata 1 has a CMD PCI IDE wired to compatibility mode at
180 * device 4 of bus 0. This variant apparently also has the
181 * Pyxis DMA bug.
182 *
183 * On the Miata 1.5 and Miata 2, the Cypress PCI-ISA bridge lives
184 * on device 7 of bus 0. This device has PCI IDE wired to
185 * compatibility mode on functions 1 and 2.
186 *
187 * There will be no interrupt mapping for these devices, so just
188 * bail out now.
189 */
190 if (pa->pa_bus == 0) {
191 if ((hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) {
192 /* Miata 1 */
193 if (pa->pa_device == 7)
194 panic("dec_550_intr_map: SIO device");
195 else if (pa->pa_device == 4)
196 return (1);
197 } else {
198 /* Miata 1.5 or Miata 2 */
199 if (pa->pa_device == 7) {
200 if (pa->pa_function == 0)
201 panic("dec_550_intr_map: SIO device");
202 if (pa->pa_function == 1 ||
203 pa->pa_function == 2)
204 return (1);
205 }
206 }
207 }
208
209 /*
210 * The console places the interrupt mapping in the "line" value.
211 * We trust it whenever possible.
212 */
213 if (line >= 0 && line < DEC_550_MAX_IRQ) {
214 *ihp = line;
215 return 0;
216 }
217 if (DEC_550_LINE_IS_ISA(line)) {
218 #if NSIO > 0
219 *ihp = line;
220 return 0;
221 #else
222 printf("dec_550_intr_map: ISA IRQ %d for %d/%d/%d\n",
223 DEC_550_LINE_ISA_IRQ(line),
224 pa->pa_bus, pa->pa_device, pa->pa_function);
225 return 1;
226 #endif
227 }
228
229 if (pa->pa_bridgetag) {
230 buspin = PPB_INTERRUPT_SWIZZLE(pa->pa_rawintrpin,
231 pa->pa_device);
232 if (pa->pa_bridgeih[buspin - 1] != 0) {
233 *ihp = pa->pa_bridgeih[buspin - 1];
234 return 0;
235 }
236 }
237
238 return 1;
239 }
240
241 const char *
dec_550_intr_string(ccv,ih)242 dec_550_intr_string(ccv, ih)
243 void *ccv;
244 pci_intr_handle_t ih;
245 {
246 #if 0
247 struct cia_config *ccp = ccv;
248 #endif
249 static char irqstr[16]; /* 12 + 2 + NULL + sanity */
250
251 #if NSIO
252 if (DEC_550_LINE_IS_ISA(ih))
253 return (sio_intr_string(NULL /*XXX*/,
254 DEC_550_LINE_ISA_IRQ(ih)));
255 #endif
256
257 if (ih >= DEC_550_MAX_IRQ)
258 panic("dec_550_intr_string: bogus 550 IRQ 0x%lx", ih);
259 snprintf(irqstr, sizeof irqstr, "dec 550 irq %ld", ih);
260 return (irqstr);
261 }
262
263 int
dec_550_intr_line(ccv,ih)264 dec_550_intr_line(ccv, ih)
265 void *ccv;
266 pci_intr_handle_t ih;
267 {
268 #if NSIO
269 if (DEC_550_LINE_IS_ISA(ih))
270 return (sio_intr_line(NULL /*XXX*/, DEC_550_LINE_ISA_IRQ(ih)));
271 #endif
272
273 return (ih);
274 }
275
276 void *
dec_550_intr_establish(ccv,ih,level,func,arg,name)277 dec_550_intr_establish(ccv, ih, level, func, arg, name)
278 void *ccv, *arg;
279 pci_intr_handle_t ih;
280 int level;
281 int (*func)(void *);
282 const char *name;
283 {
284 #if 0
285 struct cia_config *ccp = ccv;
286 #endif
287 void *cookie;
288
289 #if NSIO
290 if (DEC_550_LINE_IS_ISA(ih))
291 return (sio_intr_establish(NULL /*XXX*/,
292 DEC_550_LINE_ISA_IRQ(ih), IST_LEVEL, level, func, arg,
293 name));
294 #endif
295
296 if (ih >= DEC_550_MAX_IRQ)
297 panic("dec_550_intr_establish: bogus dec 550 IRQ 0x%lx", ih);
298
299 cookie = alpha_shared_intr_establish(dec_550_pci_intr, ih, IST_LEVEL,
300 level, func, arg, name);
301
302 if (cookie != NULL &&
303 alpha_shared_intr_firstactive(dec_550_pci_intr, ih)) {
304 scb_set(0x900 + SCB_IDXTOVEC(ih), dec_550_iointr, NULL);
305 dec_550_intr_enable(ih);
306 }
307 return (cookie);
308 }
309
310 void
dec_550_intr_disestablish(ccv,cookie)311 dec_550_intr_disestablish(ccv, cookie)
312 void *ccv, *cookie;
313 {
314 struct cia_config *ccp = ccv;
315 struct alpha_shared_intrhand *ih = cookie;
316 unsigned int irq = ih->ih_num;
317 int s;
318
319 #if NSIO
320 /*
321 * We have to determine if this is an ISA IRQ or not! We do this
322 * by checking to see if the intrhand points back to an intrhead
323 * that points to our cia_config. If not, it's an ISA IRQ. Pretty
324 * disgusting, eh?
325 */
326 if (ih->ih_intrhead->intr_private != ccp) {
327 sio_intr_disestablish(NULL /*XXX*/, cookie);
328 return;
329 }
330 #endif
331
332 s = splhigh();
333
334 alpha_shared_intr_disestablish(dec_550_pci_intr, cookie);
335 if (alpha_shared_intr_isactive(dec_550_pci_intr, irq) == 0) {
336 dec_550_intr_disable(irq);
337 alpha_shared_intr_set_dfltsharetype(dec_550_pci_intr, irq,
338 IST_NONE);
339 scb_free(0x900 + SCB_IDXTOVEC(irq));
340 }
341
342 splx(s);
343 }
344
345 void *
dec_550_pciide_compat_intr_establish(v,dev,pa,chan,func,arg)346 dec_550_pciide_compat_intr_establish(v, dev, pa, chan, func, arg)
347 void *v;
348 struct device *dev;
349 struct pci_attach_args *pa;
350 int chan;
351 int (*func)(void *);
352 void *arg;
353 {
354 pci_chipset_tag_t pc = pa->pa_pc;
355 void *cookie = NULL;
356 int bus, irq;
357
358 pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL);
359
360 /*
361 * If this isn't PCI bus #0, all bets are off.
362 */
363 if (bus != 0)
364 return (NULL);
365
366 irq = PCIIDE_COMPAT_IRQ(chan);
367 #if NSIO
368 cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO,
369 func, arg, dev->dv_xname);
370 #endif
371 return (cookie);
372 }
373
374 void
dec_550_pciide_compat_intr_disestablish(v,cookie)375 dec_550_pciide_compat_intr_disestablish(v, cookie)
376 void *v;
377 void *cookie;
378 {
379 sio_intr_disestablish(NULL, cookie);
380 }
381
382 void
dec_550_iointr(arg,vec)383 dec_550_iointr(arg, vec)
384 void *arg;
385 unsigned long vec;
386 {
387 int irq;
388
389 irq = SCB_VECTOIDX(vec - 0x900);
390
391 if (irq >= DEC_550_MAX_IRQ)
392 panic("550_iointr: vec 0x%lx out of range", vec);
393
394 if (!alpha_shared_intr_dispatch(dec_550_pci_intr, irq)) {
395 alpha_shared_intr_stray(dec_550_pci_intr, irq,
396 "dec 550 irq");
397 if (ALPHA_SHARED_INTR_DISABLE(dec_550_pci_intr, irq))
398 dec_550_intr_disable(irq);
399 } else
400 alpha_shared_intr_reset_strays(dec_550_pci_intr, irq);
401 }
402
403 void
dec_550_intr_enable(irq)404 dec_550_intr_enable(irq)
405 int irq;
406 {
407
408 cia_pyxis_intr_enable(irq + DEC_550_PCI_IRQ_BEGIN, 1);
409 }
410
411 void
dec_550_intr_disable(irq)412 dec_550_intr_disable(irq)
413 int irq;
414 {
415
416 cia_pyxis_intr_enable(irq + DEC_550_PCI_IRQ_BEGIN, 0);
417 }
418